CN105116952B - Programmable current reference circuit - Google Patents
Programmable current reference circuit Download PDFInfo
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- CN105116952B CN105116952B CN201510430665.0A CN201510430665A CN105116952B CN 105116952 B CN105116952 B CN 105116952B CN 201510430665 A CN201510430665 A CN 201510430665A CN 105116952 B CN105116952 B CN 105116952B
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Abstract
The invention discloses a programmable current reference circuit which comprises a PTAT current circuit 100, a TIND current circuit 200, a decoding unit 300 and a logical arithmetic unit 400, wherein the PTAT current circuit is electrically connected with the logical arithmetic unit and is used for providing a PTAT current for the logical arithmetic unit; the TIND current circuit is electrically connected with the logical arithmetic unit and is used for providing a TIND current for the logical arithmetic unit; the decoding unit is electrically connected with the logic unit and is used for programming the PTAT current and the TIND current; the logical arithmetic unit is used for performing addition and subtraction operations on the PTAT current and the TIND current. The invention provides the programmable current reference circuit by aiming at the defects that a conventional current reference circuit is single in output current, cannot be reused and adjusted and the like, and the programmable current reference circuit has the characteristics of programmability, fine adjustment, rough adjustment, wide output current range, small area, reusability and the like and cannot be affected by a power supply.
Description
Technical field
The invention belongs to integrated circuit fields, are related to the programmable current reference circuit of a class, output current has all the way
Programmable and temperature independent the characteristics of, another road output current, have the characteristics of may be programmed and be directly proportional to temperature, Ke Yiying
In the circuits such as high-speed, high precision D and D/A converter, manostat, transceiver, temperature sensor.
Background technology
Along with the appearance of Internet of Things, the development of temperature sensor technology, following PTAT have been promoted
(Proportional To Absolute Temperature, i.e., be directly proportional to temperature) current reference circuit has obtained substantial amounts of
With current reference circuit is as the basic modular unit in integrated circuit, most important to whole chip system.Produce benchmark
The simplest mode of electric current is to act on resistance pressure-dividing network to realize by reference voltage, and current reference circuit passes through temperature system
The parameters such as number, PSRR, power consumption, noise judging performance, the electric current of low-temperature coefficient generally using PTAT current with
The mode of CTAT (Complementary To Absolute Temperature) electric current summation realizes, the electricity that high power supply suppresses
Stream reference circuit compensates loop using amplifier using the circuit framework unrelated with supply voltage.
The content of the invention
In consideration of it, the present invention provides a kind of programmable current reference circuit, the current reference circuit solves chip life
Puerperal affects the problem of performance because changing bias current size, ensures that chip with optimum stable performance work
Make.
To reach above-mentioned purpose, the present invention provides following technical scheme：A kind of programmable current reference circuit, including
PTAT current circuit 100, TIND current circuits 200, decoding unit 300 and ALU 400；The PTAT current circuit
Electrically connect with ALU, for providing PTAT current to ALU；The TIND current circuits are transported with logic
Unit electrical connection is calculated, for TIND electric currents being provided to ALU；The decoding unit is electrically connected with logical block, is used for
Operation is programmed to PTAT current circuit and TIND current circuits；The ALU is for PTAT current and TIND
Electric current carries out signed magnitude arithmetic(al).
Preferably, the PTAT current circuit includes the first amplifier, the first PMOS and the first NMOS tube, first fortune
The reverse input end put is connected with reference voltage terminal, the positive input of the first amplifier be connected with the drain electrode of the first PMOS after Jing
First resistor R is connected with the drain electrode of the first NMOS tube, and the outfan of the first amplifier is connected with the output offset side of the first PMOS,
The drain electrode of first NMOS tube is connected with the grid of the first NMOS tube, the source ground of the first NMOS tube, the first PMOS
Grid connects supply voltage.
Preferably, the TIND current circuits include the second amplifier, the second PMOS and the second NMOS tube, second fortune
The reverse input end put is connected with reference voltage terminal, the positive input of the second amplifier be connected with the drain electrode of the second PMOS after Jing
Second resistance R is connected with the drain electrode of the second NMOS tube, and the outfan of the second amplifier is connected with the output offset side of the second PMOS,
The drain electrode of second NMOS tube is connected with the grid of the second NMOS tube, the source ground of the second NMOS tube, the second PMOS
Grid connects supply voltage.
Preferably, the logical algorithm unit includes PMOS additive operation unit, NMOS tube additive operation unit, subtraction
Arithmetic element, programmable PMOS additive operation unit and programmable NMOS tube additive operation unit.
Preferably, the PMOS additive operation unit includes the first current source and N+1 PMOS, and the N+1 is individual
The grid connection of PMOS, the source electrode of N+1 PMOS connect supply voltage；First current source respectively with one of PMOS
The drain electrode of pipe, grid connection, the drain electrode of remaining PMOS are connected with outfan, the first power supply stream minus earth.
Preferably, the NMOS tube additive operation unit includes the second current source and N+1 NMOS tube, and the N+1 is individual
The grid connection of NMOS tube, the source ground of N+1 NMOS tube；Second current source leakage respectively with one of NMOS tube
Pole, grid connection, the drain electrode of remaining NMOS tube are connected with outfan；The second current source positive pole connects supply voltage.
Preferably, the subtraction unit includes the 3rd current source, the 4th current source, two PMOSs and two NMOS
Pipe, the grid connection of two PMOSs, the source electrode of two PMOSs are connected with supply voltage respectively, and the 3rd current source is just
Pole drain electrode respectively with one of PMOS, grid are connected, the minus earth of the 3rd current source；The drain electrode of another PMOS
It is connected with outfan；The grid connection of two NMOS tubes, the source electrode of two NMOS tubes are connected to ground respectively, and the 4th current source is just
Pole connects supply voltage, and the drain electrode respectively with one of NMOS tube of the negative pole of the 4th current source, grid are connected, another NMOS tube
Drain electrode be connected with outfan.
Preferably, the programmable PMOS additive operation unit includes the 5th current source and N+1 PMOS, described
The grid connection of N+1 PMOS；The source electrode of the N+1 PMOS connects supply voltage；The positive pole of the 5th current source respectively with
The drain electrode of one of PMOS, grid connection, the minus earth of the 5th current source, the drain electrode point of remaining N number of PMOS
It is not connected with outfan through a transmission gate.
Preferably, the programmable NMOS tube additive operation unit includes the 6th current source and N+1 NMOS tube, described
The grid connection of N+1 NMOS tube；The source electrode of N+1 NMOS tube is grounded respectively, and the 6th current source positive pole connects supply voltage,
The drain electrode respectively with one of NMOS tube of the negative pole of the 6th current source, grid are connected, the source electrode difference Jing of remaining N number of NMOS tube
One transmission gate is connected with outfan.
As a result of above technical scheme, the present invention has following Advantageous Effects：
The present invention for conventional current reference circuit output current it is single, not reusable, it is unadjustable the shortcomings of, design
The programmable current reference circuit of one class, with programmable, fine setting, coarse adjustment, broad output current scope, do not affected by power supply,
The features such as area is little, reusable, can configure different output currents, its technique effect as needed：
(1), in the present invention, current reference circuit can realize the optional TIND electric currents of wide scope by controlling decoding unit.
(2) reference current circuit obtains PTAT current (1 ± B) the * A of wide scope by controlling decoding unit, and can be with
Be finely adjusted, coarse adjustment, i.e., parameter A and B can be adjusted as needed.
(3) the programmable characteristic of reference current circuit output current is determined and be may be multiplexed.
Description of the drawings
In order that the object, technical solutions and advantages of the present invention are clearer, below in conjunction with accompanying drawing the present invention is made into
The detailed description of one step, wherein：
Fig. 1 is current reference circuit structural representation；
Fig. 2 is PTAT current electrical block diagram；
Fig. 3 is TIND current circuit structural representations；
Fig. 4 is decoding unit port schematic diagram；
Fig. 5 is PMOS adder operation circuit structural representation；
Fig. 6 is NMOS tube adder operation circuit structural representation；
Fig. 7 is subtraction electrical block diagram；
Fig. 8 is programmable PMOS adder operation circuit structural representation；
Fig. 9 is programmable NMOS tube adder operation circuit structural representation；
Figure 10 is PTAT current waveform diagram；
Figure 11 is TIND current waveform schematic diagrams.
Specific embodiment
Below with reference to accompanying drawing, the preferred embodiments of the present invention are described in detail；It should be appreciated that preferred embodiment
Only for the explanation present invention, rather than in order to limit the scope of the invention.
Fig. 1 is programmable current reference circuit structural representation, including PTAT current circuit 100, TIND current circuits
200th, decoding unit 300, ALU 400.PTAT current circuit 100 is electrically connected with ALU 400, and to patrolling
Collect arithmetic element 400 and PTAT current is provided；TIND current circuits 200 are electrically connected with ALU 400, and to logical operationss
Unit 400 provides TIND electric currents；Decoding unit 300 is electrically connected with ALU 400, and PTAT current and TIND electric currents are entered
Row programming operation；ALU 400 carries out addition and subtraction to PTAT current and TIND electric currents under the control of decoding unit 300
Computing, so as to export different TIND electric currents ITIND and PTAT current IPTAT.
It is the structural representation of TIND current circuits that Fig. 2 is PTAT current electrical block diagram, Fig. 3, both circuits
Structure is the same, and simply the parameter value of device is different, therefore the present embodiment is only said by taking PTAT current circuit as an example
It is bright.Described PTAT current circuit includes the first amplifier OPA, the first NMOS tube MNA, the first PMOS MPA and first resistor R；
The negative pole of the first amplifier OPA is connected with input reference voltage end VIN, and the positive input of the first amplifier OPA is respectively with first
The drain electrode of PMOS MPA, the positive pole of first resistor R are connected, the grid of the outfan of the first amplifier OPA and the first PMOS MPA
Pole, the outfan VBP of the first PMOS are connected, and the source electrode of the first PMOS MPA is connected with supply voltage VDD, and first
The grid of NMOS tube MNA, drain electrode are connected with the negative pole of first resistor R, and the source electrode of the first NMOS tube MNA is connected with ground terminal GND
Connect, reference voltage acts on resistance R and the first NMOS tube MNA by the first amplifier OPA, PTAT is exported from the first PMOS MPA
Electric current.
Fig. 4 is decoding unit port schematic diagram, by with it is non-, or the gate such as non-, phase inverter constitute.3 input port A0,
A1, A2,8 output ports Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, and with thermometer coding form output signal, for controlling
ALU realizes signed magnitude arithmetic(al), and multiple decoding units are used in current reference circuit.
Fig. 5 is PMOS adder operation circuit structural representation, including a current source IP0With N+1 PMOS MP0,
MP1、、、、、、MPn.Current source IP0Positive pole is connected with the grid of the grid of PMOS MP0, drain electrode, remaining N number of PMOS, electricity
Stream source IP0Minus earth GND, the drain electrode of remaining N number of PMOS are connected with outfan IBP, the source electrode of all of PMOS with
Supply voltage VDD is connected, output current IPTTo flow through N number of pmos current sum, IPT=IP1+IP2+……+IPn。
Fig. 6 is NMOS tube adder operation circuit structural representation, including a current source IN0With N+1 NMOS tube MN0,
MN1、、、、、、MNn.Current source IN0Negative pole is connected with the grid of the grid of NMOS tube MN0, drain electrode, remaining N number of NMOS tube, electricity
Stream source IN0Positive pole meets supply voltage VDD, and the drain electrode of remaining N number of NMOS tube is connected with outfan IBN, the source of all of NMOS tube
Extremely it is connected with ground terminal GND, output current INTTo flow through N number of NMOS tube electric current sum, INT=IN1+IN2+……+INn。
Fig. 7 is subtraction electrical block diagram, including the 3rd current source IPA0, the 4th current source INA0, two PMOS
Pipe MPA0, MPA1, two NMOS tubes MNA0, MNA1.3rd current source IPA0Positive pole and first PMOS MPA0 grid,
Drain electrode, the grid of second PMOS MPA1 are connected, the 3rd current source IPA0Negative pole be connected with ground terminal GND, two PMOS
The source electrode of pipe is connected with supply voltage VDD, the 4th current source INA0Negative pole and the grid of first NMOS tube MNA0, drain electrode,
The grid of second NMOS tube MNA1 is connected, the 4th current source INA0Positive pole be connected with supply voltage VDD, two NMOS
The source electrode of pipe is connected with ground terminal GND, the drain electrode, the outfan that drain with the second NMOS tube MNA1 of second PMOS MPA1
IBPN is connected, output current IMTo flow through second pmos current IPA1With flow through second NMOS tube electric current INA1Difference.
Fig. 8 is programmable PMOS adder operation circuit structural representation, including the 5th current source IPB0, N+1 PMOS
Pipe MPB0, MPB1,,, MPBn, N number of transmission gate TRIP1, TRIP2,,, TRIPn.5th positive pole and a PMOS
Grid, drain electrode, the grid of remaining N number of PMOS are connected, the 5th IPB0Minus earth GND, the drain electrode point of remaining N number of PMOS
It is not connected with the positive pole of N number of transmission gate, the negative pole of N number of transmission gate is connected with outfan IBPB, and the grid end of N number of transmission gate is just
Pole is connected with decoding unit outfan, and the connect signal of grid negative pole and positive signal are in logic conversely, all of PMOS
Source electrode is connected with supply voltage VDD, by the output end current I that decoding unit is controlledPBTTo flow through N number of pmos current
Sum, IPBT=IPB1+IPB2+……+IPBn。
Fig. 9 is programmable NMOS tube adder operation circuit structural representation, including the 6th current source INC0, N+1 NMOS
Pipe MNC0, MNC1,,, MNCn, N number of transmission gate TRIN1, TRI2,,, TRIn.The grid of the 6th negative pole and a NMOS tube
Pole, drain electrode, the grid of remaining N number of NMOS tube are connected, the 6th INC0Positive pole meets supply voltage VDD, the leakage of remaining N number of NMOS tube
Pole is connected with the positive pole of N number of transmission gate respectively, and the negative pole of N number of transmission gate is connected with outfan IBNC, the grid of N number of transmission gate
Proper pole is connected with decoding unit outfan, and the connect signal of grid negative pole is with positive signal in logic conversely, all of NMOS
The source electrode of pipe is connected with ground terminal GND, by the output end current I that decoding unit is controlledNCTTo flow through N number of NMOS tube electric current
Sum, INCT=INC1+INC2+……+INCn。
Figure 10 is PTAT current waveform diagram, and output current is IPTAT, can carry out coarse adjustment and micro- by decoding unit
Adjust, coarse unit electric current is I, it is possible to achieve the output current of IPTAT-nI to IPTAT+nI；Fine setting unit is Δ I, Ke Yishi
The output current of existing IPTAT-n Δ I to IPTAT+n Δ I, n is natural number.
Figure 11 is TIND current waveform schematic diagrams, and output current is ITIND, can be adjusted by decoding unit, is adjusted
Section unitary current is Δ I, it is possible to achieve the output current of ITIND-n Δ I to ITIND+n Δ I, n is natural number.
The preferred embodiments of the present invention are the foregoing is only, the present invention is not limited to, it is clear that those skilled in the art
Member the present invention can be carried out it is various change and modification without departing from the spirit and scope of the present invention.So, if the present invention
These modifications and modification belong within the scope of the claims in the present invention and its equivalent technologies, then the present invention is also intended to comprising these
Including change and modification.
Claims (3)
1. a kind of programmable current reference circuit, it is characterised in that：Including PTAT current circuit（100）, TIND current circuits
（200）, decoding unit（300）And ALU（400）,
The PTAT current circuit is electrically connected with ALU, for providing PTAT current to ALU；
The TIND current circuits are electrically connected with ALU, for providing TIND electric currents to ALU；
The decoding unit is electrically connected with logical block, for being programmed behaviour to PTAT current circuit and TIND current circuits
Make；
The ALU is for carrying out signed magnitude arithmetic(al) to PTAT current and TIND electric currents；
The logical algorithm unit include PMOS additive operation unit, NMOS tube additive operation unit, subtraction unit, can
The PMOS additive operation unit of programming and programmable NMOS tube additive operation unit；The PMOS additive operation unit bag
The first current source and N+1 PMOS are included, the grid connection of the N+1 PMOS, the source electrode of N+1 PMOS connect power supply electricity
Pressure；First current source drain electrode respectively with one of PMOS, grid are connected, the drain electrode of remaining PMOS and outfan
Connection, the first power supply stream minus earth；The NMOS tube additive operation unit includes the second current source and N+1 NMOS
Pipe, the grid connection of the N+1 NMOS tube, the source ground of N+1 NMOS tube；Second current source is respectively with wherein one
The drain electrode of individual NMOS tube, grid connection, the drain electrode of remaining NMOS tube are connected with outfan；The second current source positive pole connects power supply
Voltage；The subtraction unit includes the 3rd current source, the 4th current source, two PMOSs and two NMOS tubes, two
The grid connection of PMOS, the source electrode of two PMOSs are connected with supply voltage respectively, the positive pole difference of the 3rd current source
Drain electrode, grid with one of PMOS is connected, the minus earth of the 3rd current source；The drain electrode of another PMOS and output
End connection；
The grid connection of two NMOS tubes, the source electrode of two NMOS tubes are connected to ground respectively, and the positive pole of the 4th current source connects power supply
Voltage, the drain electrode respectively with one of NMOS tube of the negative pole of the 4th current source, grid are connected, the drain electrode of another NMOS tube with
Outfan connects；The programmable PMOS additive operation unit includes the 5th current source and N+1 PMOS, the N+1
The grid connection of individual PMOS；The source electrode of the N+1 PMOS connects supply voltage；The positive pole of the 5th current source respectively with wherein
The drain electrode of one PMOS, grid connection, the minus earth of the 5th current source, the drain electrode difference Jing of remaining N number of PMOS
Cross a transmission gate to be connected with outfan；The programmable NMOS tube additive operation unit includes the 6th current source and N+1
NMOS tube, the grid connection of the N+1 NMOS tube；The source electrode of N+1 NMOS tube is grounded respectively, the 6th current source positive pole
Connect supply voltage, the drain electrode respectively with one of NMOS tube of the negative pole of the 6th current source, grid are connected, remaining N number of NMOS tube
Source electrode difference mono- transmission gate of Jing be connected with outfan.
2. programmable current reference circuit according to claim 1, it is characterised in that：The PTAT current circuit includes
First amplifier, the first PMOS and the first NMOS tube, the reverse input end of first amplifier are connected with reference voltage terminal, and first
After the positive input of amplifier is connected with the drain electrode of the first PMOS, Jing first resistors R are connected with the drain electrode of the first NMOS tube, the
The outfan of one amplifier is connected with the output offset side of the first PMOS, drain electrode and first NMOS tube of first NMOS tube
Grid connects, and the source ground of the first NMOS tube, the grid of the first PMOS connect supply voltage.
3. programmable current reference circuit according to claim 1, it is characterised in that：The TIND current circuits include
Second amplifier, the second PMOS and the second NMOS tube, the reverse input end of second amplifier are connected with reference voltage terminal, and second
After the positive input of amplifier is connected with the drain electrode of the second PMOS, Jing second resistances R are connected with the drain electrode of the second NMOS tube, the
The outfan of two amplifiers is connected with the output offset side of the second PMOS, drain electrode and second NMOS tube of second NMOS tube
Grid connects, and the source ground of the second NMOS tube, the grid of the second PMOS connect supply voltage.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510430665.0A CN105116952B (en) | 2015-07-21 | 2015-07-21 | Programmable current reference circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510430665.0A CN105116952B (en) | 2015-07-21 | 2015-07-21 | Programmable current reference circuit |
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| CN105116952A CN105116952A (en) | 2015-12-02 |
| CN105116952B true CN105116952B (en) | 2017-04-12 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US10473531B2 (en) * | 2017-09-05 | 2019-11-12 | Novatek Microelectronics Corp. | Temperature sensor and method of detecting temperature |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6791858B2 (en) * | 2002-08-26 | 2004-09-14 | Micron Technology, Inc. | Power reduction in CMOS imagers by trimming of master current reference |
| JP3810364B2 (en) * | 2002-12-19 | 2006-08-16 | 松下電器産業株式会社 | Display device driver |
| CN2914164Y (en) * | 2005-11-03 | 2007-06-20 | 西安华迅微电子有限公司 | Programmable analog integrated circuit chip able to reduce power consumption |
| CN201984371U (en) * | 2010-10-09 | 2011-09-21 | 中国电子科技集团公司第五十八研究所 | Programmable reference source circuit |
| CN201846321U (en) * | 2010-11-16 | 2011-05-25 | 深圳市富满电子有限公司南山分公司 | Segmented temperature compensation reference circuit |
| KR20140071176A (en) * | 2012-12-03 | 2014-06-11 | 현대자동차주식회사 | Current generation circuit |
| CN104062999A (en) * | 2013-03-21 | 2014-09-24 | 中国人民解放军理工大学 | Self-starting high-matching band-gap reference voltage source chip design |
| CN203909653U (en) * | 2014-01-02 | 2014-10-29 | 意法半导体研发(深圳)有限公司 | Reference current generator circuit |
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