TWI587626B - Operational amplifier circuit - Google Patents
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Description
本揭露是有關於一種運算放大器電路。 The present disclosure relates to an operational amplifier circuit.
習知的運算放大器電路廣泛地應用於積體電路中，用以根據差動訊號產生一放大後的輸出訊號。運算放大器電路通常會偏壓在一電壓供應端VDD。然而電壓供應端VDD之電壓位準不同或改變，可能會導致運算放大器電路的輸出端隨著電壓供應端之電壓變化而有不同的電壓位準或電流變化，可能會導致雜訊的產生而影響到輸出端上的輸出訊號，造成運算放大器的輸出有誤差或不精準的情形。因此，有必要提供一種能控制運算放大器電路的輸出端之電壓位準的運算放大器電路。 Conventional operational amplifier circuits are widely used in integrated circuits to generate an amplified output signal based on a differential signal. The operational amplifier circuit is typically biased at a voltage supply VDD. However, the voltage level of the voltage supply terminal VDD is different or changed, which may cause the output terminal of the operational amplifier circuit to have different voltage levels or current changes as the voltage of the voltage supply terminal changes, which may cause noise to be generated. The output signal to the output causes the output of the op amp to be inaccurate or inaccurate. Therefore, it is necessary to provide an operational amplifier circuit capable of controlling the voltage level at the output of an operational amplifier circuit.
根據本揭露的一實施例，提供一種運算放大器電路。運算放大器電路包含一運算放大器及一共模回饋電路。運算放大器電路包含一第一電晶體、一第二電晶體、一第一電阻、一第二電阻、一第三電阻、一第四電阻及一第五電阻。第一電晶體的控制端耦接至一第一輸入端。第二電晶體的第二端耦接至第一電晶體的第二端，第二電晶體的控制端耦接至一第二輸入端。第一電阻耦接在第一電晶體的第二端與一接地端之間。第二電阻的第一端耦接至一電壓供應端。第三電阻的第一端耦接至電壓供應端。第四電阻的第一端耦接至第二電阻的第二端，第四電阻的第二端耦接 至第一電晶體的第一端。第五電阻的第一端耦接至第三電阻的第二端，第五電阻的第二端耦接至第二電晶體的第一端。共模回饋電路包含一控制電路及一電流鏡電路。控制電路依據第四電阻的第一端之電壓位準、第五電阻的第一端之電壓位準、及電壓供應端之電壓位準提供一參考電壓。電流鏡電路的一第一端接收控制電路提供的參考電壓以在電流鏡電路的第一端與接地端之間產生一第一電流。電流鏡電路的一第二端耦接至第四電阻的第二端以在電流鏡電路的第二端與接地端之間產生一第二電流。電流鏡電路的一第三端耦接至第五電阻的第二端以在電流鏡電路的第三端與接地端之間產生一第三電流。 In accordance with an embodiment of the present disclosure, an operational amplifier circuit is provided. The operational amplifier circuit includes an operational amplifier and a common mode feedback circuit. The operational amplifier circuit includes a first transistor, a second transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor. The control end of the first transistor is coupled to a first input end. The second end of the second transistor is coupled to the second end of the first transistor, and the control end of the second transistor is coupled to a second input. The first resistor is coupled between the second end of the first transistor and a ground. The first end of the second resistor is coupled to a voltage supply terminal. The first end of the third resistor is coupled to the voltage supply terminal. The first end of the fourth resistor is coupled to the second end of the second resistor, and the second end of the fourth resistor is coupled To the first end of the first transistor. The first end of the fifth resistor is coupled to the second end of the third resistor, and the second end of the fifth resistor is coupled to the first end of the second transistor. The common mode feedback circuit includes a control circuit and a current mirror circuit. The control circuit provides a reference voltage according to the voltage level of the first end of the fourth resistor, the voltage level of the first end of the fifth resistor, and the voltage level of the voltage supply terminal. A first end of the current mirror circuit receives a reference voltage provided by the control circuit to generate a first current between the first end of the current mirror circuit and the ground. A second end of the current mirror circuit is coupled to the second end of the fourth resistor to generate a second current between the second end of the current mirror circuit and the ground. A third end of the current mirror circuit is coupled to the second end of the fifth resistor to generate a third current between the third end of the current mirror circuit and the ground.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。 The above described features and advantages of the invention will be apparent from the following description.
100、200‧‧‧運算放大器電路 100, 200‧‧‧Operation Amplifier Circuit
110‧‧‧運算放大器 110‧‧‧Operational Amplifier
120‧‧‧共模回饋電路 120‧‧‧Common mode feedback circuit
122、222‧‧‧控制電路 122, 222‧‧‧ control circuit
124、224‧‧‧電流鏡電路 124, 224‧‧‧ current mirror circuit
Q1~Q9‧‧‧電晶體 Q1~Q9‧‧‧Optoelectronics
VDD、Vin1、Vin2、Vout1、Vout2、N1、N2‧‧‧端點 VDD, Vin1, Vin2, Vout1, Vout2, N1, N2‧‧‧ endpoints
Vref‧‧‧參考電壓 Vref‧‧‧reference voltage
I1~I3‧‧‧電流 I1~I3‧‧‧ Current
R1~R6‧‧‧電阻 R1~R6‧‧‧ resistor
第1圖繪示依據本揭露第一實施例的一運算放大器電路的示意圖。 FIG. 1 is a schematic diagram of an operational amplifier circuit according to a first embodiment of the present disclosure.
第2圖繪示依據本揭露第二實施例的一運算放大器電路的電路圖。 FIG. 2 is a circuit diagram of an operational amplifier circuit according to a second embodiment of the present disclosure.
第1圖繪示依據本揭露第一實施例的一運算放大器電路100的示意圖。運算放大器電路100包含一運算放大器110及一共模回饋電路120。運算放大器電路100具有輸入端Vin1及輸入端Vin2，用以接收一差動輸入訊號。運算放大器電路100更具有輸出端Vout及輸出端Vout2，提供一組輸出電壓。運算放大器110包含電晶體Q1~Q2及電阻R1~R5。電晶體Q1的一控制端作為運算放大器電路100的輸入端Vin1，電晶體Q1的一 第一端作為運算放大器電路100的輸出端Vout1，電晶體Q1的一第二端耦接至電阻R4的一第一端。電晶體Q2的一控制端作為運算放大器電路100的輸入端Vin2，電晶體Q2的一第一端作為運算放大器電路100的輸出端Vout2，電晶體Q2的一第二端耦接至電阻R4的一第一端。電阻R4耦接在電晶體Q1的第二端與接地端之間。電阻R2的一第一端耦接至電壓供應端VDD，電阻R2的一第二端耦接至電阻R4的一第一端(即端點N1)。電阻R3的一第一端耦接至電壓供應端VDD，電阻R3的一第二端耦接至電阻R5的一第一端(即端點N2)。電阻R4的一第二端耦接至電晶體Q1的第一端。電阻R5的一第二端耦接至電晶體Q2的一第一端。可視實際應用調整電阻R2~R5的電阻值以決定端點N1~N2之電壓位準以及流經電晶體Q1~Q2的電流。在此實施例中，電晶體Q1及Q2為一N型金氧半電晶體，電晶體Q1及Q2的第一端為汲極端，電晶體Q1及Q2的第二端為源極端，電晶體Q1及Q2的控制端為閘極端。然而，本揭露不以此為限，在其他實施例中，可以使用其他種電晶體來實施電晶體Q1及Q2。 FIG. 1 is a schematic diagram of an operational amplifier circuit 100 in accordance with a first embodiment of the present disclosure. The operational amplifier circuit 100 includes an operational amplifier 110 and a common mode feedback circuit 120. The operational amplifier circuit 100 has an input terminal Vin1 and an input terminal Vin2 for receiving a differential input signal. The operational amplifier circuit 100 further has an output terminal Vout and an output terminal Vout2 to provide a set of output voltages. The operational amplifier 110 includes transistors Q1 to Q2 and resistors R1 to R5. A control terminal of the transistor Q1 serves as the input terminal Vin1 of the operational amplifier circuit 100, and one of the transistors Q1 The first end is the output terminal Vout1 of the operational amplifier circuit 100, and the second end of the transistor Q1 is coupled to a first end of the resistor R4. A control terminal of the transistor Q2 is used as the input terminal Vin2 of the operational amplifier circuit 100, a first end of the transistor Q2 is used as the output terminal Vout2 of the operational amplifier circuit 100, and a second terminal of the transistor Q2 is coupled to the resistor R4. First end. The resistor R4 is coupled between the second end of the transistor Q1 and the ground. A first end of the resistor R2 is coupled to the voltage supply terminal VDD, and a second end of the resistor R2 is coupled to a first end of the resistor R4 (ie, the terminal end N1). A first end of the resistor R3 is coupled to the voltage supply terminal VDD, and a second end of the resistor R3 is coupled to a first end of the resistor R5 (ie, the terminal end N2). A second end of the resistor R4 is coupled to the first end of the transistor Q1. A second end of the resistor R5 is coupled to a first end of the transistor Q2. The resistance values of the resistors R2 to R5 can be adjusted according to the actual application to determine the voltage level of the terminals N1 to N2 and the current flowing through the transistors Q1 to Q2. In this embodiment, the transistors Q1 and Q2 are an N-type MOS transistor, the first ends of the transistors Q1 and Q2 are 汲 extremes, the second ends of the transistors Q1 and Q2 are source terminals, and the transistor Q1 And the control terminal of Q2 is the gate terminal. However, the disclosure is not limited thereto, and in other embodiments, other types of transistors may be used to implement the transistors Q1 and Q2.
在此實施例中，共模回饋電路120控制輸出端Vout1之電壓位準、輸出端Vout2之電壓位準、流經電晶體Q1的電流以及流經電晶體Q2的電流。共模回饋電路120包含一控制電路122及一電流鏡電路124。在此實施例中，控制電路122依據電阻R4的第一端(端點N1)之電壓位準、電阻R5的第一端(端點N2)之電壓位準、及電壓供應端VDD之電壓位準提供一參考電壓Vref。電流鏡電路124的一第一端接收控制電路122提供的參考電壓Vref以在電流鏡電路124的第一端與接地端之間產生一電流I1，電流鏡電路124依據參考電壓Vref決定電流I1的大小。電流鏡電路 124的一第二端耦接至電阻R4的第二端(即輸出端Vout1)以在電流鏡電路124的第二端與接地端之間產生一電流I2，且電流鏡電路124的一第三端耦接至電阻R5的第二端(即輸出端Vout2)以在電流鏡電路124的第三端與接地端之間產生一電流I3。電流鏡電路124依據參考電壓Vref產生電流I2及電流I3，電流I2與電流I3實質上相同。 In this embodiment, the common mode feedback circuit 120 controls the voltage level of the output terminal Vout1, the voltage level of the output terminal Vout2, the current flowing through the transistor Q1, and the current flowing through the transistor Q2. The common mode feedback circuit 120 includes a control circuit 122 and a current mirror circuit 124. In this embodiment, the control circuit 122 is based on the voltage level of the first end (end point N1) of the resistor R4, the voltage level of the first end (end point N2) of the resistor R5, and the voltage level of the voltage supply terminal VDD. A reference voltage Vref is provided. A first end of the current mirror circuit 124 receives the reference voltage Vref provided by the control circuit 122 to generate a current I1 between the first end and the ground of the current mirror circuit 124. The current mirror circuit 124 determines the current I1 according to the reference voltage Vref. size. Current mirror circuit A second end of the 124 is coupled to the second end of the resistor R4 (ie, the output terminal Vout1) to generate a current I2 between the second end of the current mirror circuit 124 and the ground, and a third of the current mirror circuit 124. The terminal is coupled to the second end of the resistor R5 (ie, the output terminal Vout2) to generate a current I3 between the third end of the current mirror circuit 124 and the ground. The current mirror circuit 124 generates a current I2 and a current I3 according to the reference voltage Vref, and the current I2 is substantially the same as the current I3.
因此，在此實施例中，共模回饋電路120和電阻R2~R5形成提供共模回饋的一迴路以控制輸出端Vout1之電壓位準及輸出端Vout2之電壓位準。舉例來說，當電壓供應端VDD之電壓位準由1.8V增加到2.8V時，端點N1和端點N2之電壓位準也由1.5V增加到2.5V，也就是說，控制電路122所接收之端點N1之電壓位準、端點N2之電壓位準、及電壓供應端VDD之電壓位準都增加了，則控制電路122提供的參考電壓Vref之電壓位準也會增加。由於控制電路122提供的參考電壓Vref之電壓位準增加了，電流鏡電路124依據參考電壓Vref所產生之電流I2及電流I3也因此增加了。又因為從輸出端Vout1及輸出端Vout2流出之電流I2及電流I3增加了，因此輸出端Vout1及輸出端Vout2之電壓位準會下降，也因此輸出端Vout1及輸出端Vout2之電壓位準可保持在一固定的電壓位準，例如1.4V。另一方面，因為有電流I2及電流I3分別從輸出端Vout1及輸出端Vout2流入電流鏡電路124，流經電晶體Q1的電壓位準的電流不會增加。並且，輸出端Vout1及輸出端Vout2之電壓位準也會接近，流經電晶體Q1的電壓位準的電流也會相近於流經電晶體Q2的電壓位準的電流。因此，共模回饋電路120可控制運算放大器的兩輸出端之電壓位準，以及並且控制運算放大器的兩輸出端之電流，而使運算放大器的輸出端不會隨著電壓供應端之 電壓變化而有不同的電壓位準或電流變化，而可避免雜訊的產生，更不會能影響到輸出端上的輸出訊號的精確度。 Therefore, in this embodiment, the common mode feedback circuit 120 and the resistors R2 R R5 form a loop that provides common mode feedback to control the voltage level of the output terminal Vout1 and the voltage level of the output terminal Vout2. For example, when the voltage level of the voltage supply terminal VDD is increased from 1.8V to 2.8V, the voltage levels of the terminal N1 and the terminal N2 are also increased from 1.5V to 2.5V, that is, the control circuit 122 The voltage level of the receiving terminal N1, the voltage level of the terminal N2, and the voltage level of the voltage supply terminal VDD are all increased, and the voltage level of the reference voltage Vref provided by the control circuit 122 is also increased. Since the voltage level of the reference voltage Vref provided by the control circuit 122 is increased, the current I2 and the current I3 generated by the current mirror circuit 124 according to the reference voltage Vref are also increased. Moreover, since the current I2 and the current I3 flowing from the output terminal Vout1 and the output terminal Vout2 are increased, the voltage levels of the output terminal Vout1 and the output terminal Vout2 are lowered, so that the voltage levels of the output terminal Vout1 and the output terminal Vout2 can be maintained. At a fixed voltage level, for example 1.4V. On the other hand, since the current I2 and the current I3 flow from the output terminal Vout1 and the output terminal Vout2 to the current mirror circuit 124, respectively, the current flowing through the voltage level of the transistor Q1 does not increase. Moreover, the voltage levels of the output terminal Vout1 and the output terminal Vout2 are also close, and the current flowing through the voltage level of the transistor Q1 is also close to the current flowing through the voltage level of the transistor Q2. Therefore, the common mode feedback circuit 120 can control the voltage levels of the two output terminals of the operational amplifier, and control the currents of the two output terminals of the operational amplifier, so that the output of the operational amplifier does not follow the voltage supply end. The voltage changes and there are different voltage levels or current changes, which can avoid the generation of noise, and can not affect the accuracy of the output signal at the output.
第2圖繪示依據本揭露第二實施例的一運算放大器電路200的電路圖。在此實施例中，運算放大器電路200包含一共模回體電路，共模回饋電路包含一控制電路222及一電流鏡電路224。電流鏡電路224包含電晶體Q3~Q5及一電阻R6。電晶體Q3的一第一端耦接至電晶體Q3的一控制端，電晶體Q3的一第二端耦接至電阻R6。電晶體Q3為導通並依據參考電壓Vref產生電流I1。電晶體Q4的一第一端耦接至電阻R4的第二端(即輸出端Vout1)，電晶體Q4的一第二端端耦接至接地端，且電晶體Q4的一控制端耦接至電晶體Q3的一控制端。電晶體Q4為導通並依據參考電壓Vref產生電流I2。電晶體Q5的一第一端耦接至電阻R5的第二端(即輸出端Vout2)，電晶體Q5的一第二端端耦接至接地端，且電晶體Q5的一控制端耦接至電晶體Q3的控制端。電晶體Q5為導通並依據參考電壓Vref產生電流I3。因為電晶體Q4的閘極端之電壓位準與電晶體Q5的閘極端之電壓位準相同(又等於參考電壓Vref)，電流I2與電流I3實質上相同。電阻R6耦接在電晶體Q3的一第二端以及接地端之間。在此實施例中，電晶體Q3~Q5為一N型金氧半電晶體，電晶體Q3~Q5的第一端為汲極端，電晶體Q3~Q5的第二端為源極端，電晶體Q3~Q5的控制端為閘極端。然而，本揭露不以此為限，在其他實施例中，可以使用其他種電晶體來實施電晶體Q3~Q5，也可以使用其他元件的組合來實施電流鏡電路224。 FIG. 2 is a circuit diagram of an operational amplifier circuit 200 in accordance with a second embodiment of the present disclosure. In this embodiment, the operational amplifier circuit 200 includes a common mode return circuit, and the common mode feedback circuit includes a control circuit 222 and a current mirror circuit 224. The current mirror circuit 224 includes transistors Q3 to Q5 and a resistor R6. A first end of the transistor Q3 is coupled to a control terminal of the transistor Q3, and a second end of the transistor Q3 is coupled to the resistor R6. The transistor Q3 is turned on and generates a current I1 in accordance with the reference voltage Vref. A first end of the transistor Q4 is coupled to the second end of the resistor R4 (ie, the output terminal Vout1), a second end of the transistor Q4 is coupled to the ground, and a control end of the transistor Q4 is coupled to A control terminal of the transistor Q3. The transistor Q4 is turned on and generates a current I2 in accordance with the reference voltage Vref. A first end of the transistor Q5 is coupled to the second end of the resistor R5 (ie, the output terminal Vout2), a second end of the transistor Q5 is coupled to the ground, and a control end of the transistor Q5 is coupled to The control terminal of transistor Q3. The transistor Q5 is turned on and generates a current I3 in accordance with the reference voltage Vref. Since the voltage level of the gate terminal of the transistor Q4 is the same as the voltage level of the gate terminal of the transistor Q5 (again equal to the reference voltage Vref), the current I2 is substantially the same as the current I3. The resistor R6 is coupled between a second end of the transistor Q3 and the ground. In this embodiment, the transistors Q3~Q5 are an N-type gold oxide semi-transistor, the first end of the transistors Q3~Q5 is the 汲 terminal, the second end of the transistor Q3~Q5 is the source terminal, and the transistor Q3 The control terminal of ~Q5 is the gate terminal. However, the disclosure is not limited thereto. In other embodiments, the transistors Q3 to Q5 may be implemented using other kinds of transistors, and the current mirror circuit 224 may be implemented using a combination of other elements.
在此實施例中，控制電路222包含電晶體Q6~Q7。電晶體Q6和電晶體Q7耦接在電壓供應端VDD與電流鏡電路224之間。電晶體 Q6的一控制端耦接至電阻R7的第一端(即端點N1)。電晶體Q7的一控制端耦接至電阻R8的第一端(即端點N2)。然而，本揭露不以此為限，在其他實施例中，可以使用其他元件的組合來實施控制電路222。 In this embodiment, control circuit 222 includes transistors Q6-Q7. The transistor Q6 and the transistor Q7 are coupled between the voltage supply terminal VDD and the current mirror circuit 224. Transistor A control terminal of Q6 is coupled to the first end of the resistor R7 (ie, the terminal N1). A control terminal of the transistor Q7 is coupled to the first end of the resistor R8 (ie, the terminal N2). However, the disclosure is not limited thereto, and in other embodiments, the control circuit 222 can be implemented using a combination of other components.
在一實施例中，控制電路222更包含電晶體Q8。電晶體Q11的一第一端耦接至電晶體Q8的一控制端，電晶體Q8的一第二端耦接至電晶體Q6的第一端以及電晶體Q7的第一端。 In an embodiment, the control circuit 222 further includes a transistor Q8. A first end of the transistor Q11 is coupled to a control terminal of the transistor Q8, and a second end of the transistor Q8 is coupled to the first end of the transistor Q6 and the first end of the transistor Q7.
在一實施例中，控制電路222更包含電晶體Q9。電晶體Q9的一第一端耦接至電壓供應端VDD，電晶體Q9的一第二端耦接至電晶體Q8的第一端，電晶體Q9的一控制端耦接至電晶體Q9的第一端。 In an embodiment, the control circuit 222 further includes a transistor Q9. A first end of the transistor Q9 is coupled to the voltage supply terminal VDD, a second end of the transistor Q9 is coupled to the first end of the transistor Q8, and a control terminal of the transistor Q9 is coupled to the transistor Q9. One end.
在此實施例中，電晶體Q6~Q9為一N型金氧半電晶體，電晶體Q6~Q9的第一端為汲極端，電晶體Q6~Q9的第二端為源極端，電晶體Q6~Q9的控制端為閘極端。然而，本揭露不以此為限，在其他實施例中，可以使用其他種電晶體來實施電晶體Q6~Q9。 In this embodiment, the transistors Q6~Q9 are an N-type gold-oxygen semi-transistor, the first end of the transistors Q6~Q9 is the 汲 terminal, the second end of the transistor Q6~Q9 is the source terminal, and the transistor Q6 The control terminal of ~Q9 is the gate terminal. However, the disclosure is not limited thereto. In other embodiments, transistors Q6 to Q9 may be implemented using other kinds of transistors.
在此實施例中，電晶體Q3~Q7及電阻R4~R6形成提供共模回饋的一迴路以控制輸出端Vout1之電壓位準及輸出端Vout2之電壓位準。舉例來說，當電壓供應端VDD之電壓位準由1.8V增加到2.8V時，端點N1和端點N2之電壓位準也由1.5V增加到2.5V，也就是說，電晶體Q6的閘極端之電壓位準、電晶體Q7的閘極端之電壓位準都增加了。並且因為電壓供應端VDD之電壓位準增加了，電晶體Q6的汲極端之電壓位準和電晶體Q7的汲極端之電壓位準也增加了。因此流經電晶體Q6的電流和流經電晶體Q7的電流也會隨之增加，使得電晶體Q6的源極端之電壓位準和電晶體Q7的源極端(即參考電壓Vref)之電壓位準也會增加。由於控制電路 222提供的參考電壓Vref之電壓位準(即電晶體Q3~Q5的閘極端之電壓位準)增加了，也就是說電晶體Q4和電晶體Q5的Vgs增加了，電流鏡電路224產生之電流I2及電流I3也因此增加了。又因為從輸出端Vout1及輸出端Vout2流出之電流I2及電流I3增加了，因此輸出端Vout1及輸出端Vout2之電壓位準會下降，故輸出端Vout1之電壓位準及輸出端Vout2之電壓位準可保持在一固定電壓位準，例如1.4V。另一方面，因為有電流I2及電流I3分別從輸出端Vout1及輸出端Vout2流入電流鏡電路224，且電流I2與電流I3實質上相同，因此流經電晶體Q1的電流也會相近於流經電晶體Q2的電流。據此，共模回饋電路可控制運算放大器的兩輸出端之電壓位準，以及並且控制運算放大器的兩輸出端之電流，而使運算放大器的輸出端不會隨著電壓供應端之電壓變化而有不同的電壓位準或電流變化，而可避免雜訊的產生，更不會能影響到輸出端上的輸出訊號的精確度。 In this embodiment, the transistors Q3~Q7 and the resistors R4~R6 form a loop that provides common mode feedback to control the voltage level of the output terminal Vout1 and the voltage level of the output terminal Vout2. For example, when the voltage level of the voltage supply terminal VDD is increased from 1.8V to 2.8V, the voltage level of the terminal N1 and the terminal N2 is also increased from 1.5V to 2.5V, that is, the transistor Q6 The voltage level of the gate terminal and the voltage level of the gate terminal of the transistor Q7 are increased. And because the voltage level of the voltage supply terminal VDD is increased, the voltage level of the 汲 terminal of the transistor Q6 and the voltage level of the 汲 terminal of the transistor Q7 are also increased. Therefore, the current flowing through the transistor Q6 and the current flowing through the transistor Q7 also increase, so that the voltage level of the source terminal of the transistor Q6 and the voltage level of the source terminal of the transistor Q7 (ie, the reference voltage Vref) Will also increase. Control circuit The voltage level of the reference voltage Vref provided by 222 (i.e., the voltage level of the gate terminals of the transistors Q3 to Q5) is increased, that is, the Vgs of the transistor Q4 and the transistor Q5 are increased, and the current generated by the current mirror circuit 224 is increased. Therefore, I2 and current I3 are also increased. Moreover, since the current I2 and the current I3 flowing from the output terminal Vout1 and the output terminal Vout2 are increased, the voltage levels of the output terminal Vout1 and the output terminal Vout2 are lowered, so the voltage level of the output terminal Vout1 and the voltage level of the output terminal Vout2. It can be maintained at a fixed voltage level, such as 1.4V. On the other hand, since the current I2 and the current I3 flow from the output terminal Vout1 and the output terminal Vout2 to the current mirror circuit 224, respectively, and the current I2 is substantially the same as the current I3, the current flowing through the transistor Q1 is also close to flowing through. Current of transistor Q2. Accordingly, the common mode feedback circuit can control the voltage levels of the two output terminals of the operational amplifier and control the currents of the two output terminals of the operational amplifier, so that the output of the operational amplifier does not change with the voltage of the voltage supply terminal. There are different voltage levels or current changes to avoid noise, and it will not affect the accuracy of the output signal at the output.
在一實施例中，運算放大器電路200全部的電晶體Q1~Q9都以N型高電子移動率電晶體(High-electron-mobility transistor，HEMT)來實施，可在高電子移動率電晶體的製程限制下，不需要使用P型高電子移動率電晶體仍可提供輸出端電壓穩定且電流穩定之運算放大器。 In one embodiment, all of the transistors Q1 to Q9 of the operational amplifier circuit 200 are implemented by an N-type high-electron-mobility transistor (HEMT), which can be processed in a high electron mobility transistor. Under the restriction, it is not necessary to use a P-type high electron mobility transistor to provide an operational amplifier with stable output voltage and stable current.
根據上述實施例，提供了多種運算放大器電路。本揭露的偏壓電路包含共模回饋電路，藉由控制電路偵測運算放大器的兩端點之電壓位準提供參考電壓至電流鏡電路，電流鏡電路再從運算放大器的兩輸出端點產生兩路電流，而可控制運算放大器的兩輸出端之電壓位準，以及並且控制運算放大器的兩輸出端之電流，而使運算放大器的輸出端不會隨著電壓供應端之電壓變化而有不同的電壓位準或電流變化，而可避免雜訊的產 生，更不會能影響到輸出端上的輸出訊號的精確度。並且，本揭露更可在製程的限制下，全部使用N型電晶體取代P型電晶體來實施一偏壓電路。 According to the above embodiment, various operational amplifier circuits are provided. The bias circuit of the present disclosure includes a common mode feedback circuit, and the control circuit detects the voltage level of the two ends of the operational amplifier to provide a reference voltage to the current mirror circuit, and the current mirror circuit is generated from the two output terminals of the operational amplifier. Two currents that control the voltage level at the two outputs of the op amp and control the current at the two outputs of the op amp so that the output of the op amp does not vary with the voltage at the voltage supply Voltage level or current change to avoid noise production Health, it will not affect the accuracy of the output signal on the output. Moreover, the present disclosure can further implement a bias circuit by using an N-type transistor instead of a P-type transistor under the limitation of the process.
綜上所述，雖然本揭露已以多個實施例揭露如上，然其並非用以限定本揭露。本揭露所屬技術領域中具有通常知識者，在不脫離本揭露之精神和範圍內，當可作各種之更動與潤飾。因此，本揭露之保護範圍當視後附之申請專利範圍所界定者為準。 In summary, although the disclosure has been disclosed in the above embodiments, it is not intended to limit the disclosure. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the disclosure. Therefore, the scope of protection of this disclosure is subject to the definition of the scope of the appended claims.
100‧‧‧運算放大器電路 100‧‧‧Operation Amplifier Circuit
110‧‧‧運算放大器 110‧‧‧Operational Amplifier
120‧‧‧共模回饋電路 120‧‧‧Common mode feedback circuit
122‧‧‧控制電路 122‧‧‧Control circuit
124‧‧‧電流鏡電路 124‧‧‧current mirror circuit
Q1、Q2‧‧‧電晶體 Q1, Q2‧‧‧O crystal
VDD、Vin1、Vin2、Vout1、Vout2、N1、N2‧‧‧端點 VDD, Vin1, Vin2, Vout1, Vout2, N1, N2‧‧‧ endpoints
Vref‧‧‧參考電壓 Vref‧‧‧reference voltage
I1~I3‧‧‧電流 I1~I3‧‧‧ Current
R1~R5‧‧‧電阻 R1~R5‧‧‧ resistance
Claims (5)
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| CN201610984316.8A CN106505953B (en) | 2016-07-05 | 2016-11-09 | Operational amplifier circuit |
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| US201662358564P | 2016-07-05 | 2016-07-05 | |
| US62/358,564 | 2016-07-05 |
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| US5455539A (en) * | 1993-02-26 | 1995-10-03 | Sgs-Thomson Microelectronics S.A. | Device for regulating the common mode voltage at the output of a balanced amplifier |
| US5568089A (en) * | 1993-06-15 | 1996-10-22 | Nec Corporation | Fully differential amplifier including common mode feedback circuit |
| US7142057B2 (en) * | 2003-09-03 | 2006-11-28 | Broadcom Corporation | System to accelerate settling of an amplifier |
| TW200803159A (en) * | 2006-06-16 | 2008-01-01 | Realtek Semiconductor Corp | Amplifier with common-mode feedback circuit |
| US7683716B2 (en) * | 2008-06-04 | 2010-03-23 | Texas Instruments Incorporated | Constant output common mode voltage of a pre-amplifier circuit |
| US7924095B2 (en) * | 2009-06-26 | 2011-04-12 | Broadcom Corporation | Operational amplifiers having low-power unconditionally-stable common-mode feedback |
| US20120306574A1 (en) * | 2011-05-31 | 2012-12-06 | Texas Instruments Incorporated | Wide bandwidth class c amplifier with common-mode feedback |
| US20160190998A1 (en) * | 2013-09-13 | 2016-06-30 | Alps Electric Co., Ltd. | Amplifier circuit |
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- 2016-10-20 TW TW105133884A patent/TWI587626B/en active
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|---|---|---|---|---|
| US5455539A (en) * | 1993-02-26 | 1995-10-03 | Sgs-Thomson Microelectronics S.A. | Device for regulating the common mode voltage at the output of a balanced amplifier |
| US5568089A (en) * | 1993-06-15 | 1996-10-22 | Nec Corporation | Fully differential amplifier including common mode feedback circuit |
| US7142057B2 (en) * | 2003-09-03 | 2006-11-28 | Broadcom Corporation | System to accelerate settling of an amplifier |
| TW200803159A (en) * | 2006-06-16 | 2008-01-01 | Realtek Semiconductor Corp | Amplifier with common-mode feedback circuit |
| US7683716B2 (en) * | 2008-06-04 | 2010-03-23 | Texas Instruments Incorporated | Constant output common mode voltage of a pre-amplifier circuit |
| US7924095B2 (en) * | 2009-06-26 | 2011-04-12 | Broadcom Corporation | Operational amplifiers having low-power unconditionally-stable common-mode feedback |
| US20120306574A1 (en) * | 2011-05-31 | 2012-12-06 | Texas Instruments Incorporated | Wide bandwidth class c amplifier with common-mode feedback |
| US20160190998A1 (en) * | 2013-09-13 | 2016-06-30 | Alps Electric Co., Ltd. | Amplifier circuit |
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