CN105097836A - Display substrate, a manufacture method thereof, and a display device - Google Patents
Display substrate, a manufacture method thereof, and a display device Download PDFInfo
- Publication number
- CN105097836A CN105097836A CN201510416554.4A CN201510416554A CN105097836A CN 105097836 A CN105097836 A CN 105097836A CN 201510416554 A CN201510416554 A CN 201510416554A CN 105097836 A CN105097836 A CN 105097836A
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- layer
- black matrix
- base plate
- display base
- pixel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Abstract
The invention relates to a display substrate, comprising a colored-film layer, comprising a plurality of sub pixels, a common electrode which is arranged on the colored-film layer and corresponds to a junction of adjacent sub pixels in the plurality of sub pixels, and a black matrix which is arranged on the common electrode. According to the technical solution of the invention, by arranging the black matrix at the common electrode, because the common electrode corresponds to the junction of the adjacent sub pixels, namely that the black matrix on the common electrode corresponds the junction of the adjacent sub pixels, a separating effect of the black matrix to the adjacent sub pixels is ensured. Because the black matrix is far away from a thin film transistor, the influence to electrical properties of the thin film transistor is avoided.
Description
Technical field
The present invention relates to Display Technique field, in particular to a kind of display base plate, a kind of display unit and a kind of display base plate manufacture method.
Background technology
COA and Color-filteronArray is the technology color rete and array (Array) substrate integrated.Coat the color rete of the upper formation of completed array (Array) by chromatic photoresist, the aperture opening ratio of pixel can be improved, and realize the autoregistration of color rete and array base palte.
But, the black matrix adopted in existing COA technology forms primarily of the organic resin of coated carbon black granules, by be coated with carbon black granules black arranged in matrix on array base palte time, complex process, and as shown in Figure 1, public electrode 1 of the prior art covers on array base palte, as shown in Figures 2 and 3, black matrix 2 wherein and data wire 8 and grid line 9 only one to two, interval Rotating fields, distance TFT (thin-film transistor) is nearer, the TFT performance of easy meeting array substrate impacts, and causes the reduction of producing yield.
Summary of the invention
Technical problem to be solved by this invention is, how to avoid the performance of black matrix to thin-film transistor in color rete to impact.
For this purpose, the present invention proposes a kind of display base plate, comprising:
Color rete, comprises multiple sub-pixel;
Public electrode, is arranged on described color film layer, corresponding with the intersection of adjacent subpixels in described multiple sub-pixel;
Black matrix, is arranged on described public electrode.
Preferably, the reflectivity of described black matrix is less than default reflectivity.
Preferably, the anti-corrosion scale of described black matrix is lower than the anti-corrosion scale of described public electrode.
Preferably, described black matrix is metal simple-substance, or metal alloy, or the composite bed that metal simple-substance and metal alloy are formed, or the composite bed that metal oxide, nitride and nitrogen oxide are formed, or the composite bed that metal alloy oxide, nitride and nitrogen oxide are formed.
Preferably, also comprise:
Substrate;
Thin-film transistor, is arranged on described substrate;
First passivation layer, is arranged on described thin-film transistor, and wherein, described color rete is arranged on described first passivation layer;
Pixel electrode, is arranged on described color film layer;
Second passivation layer, is arranged on described pixel electrode, and wherein, described public electrode is arranged on described second passivation layer.
Preferably, also comprise:
Flatness layer, is arranged on described color film layer, and wherein, described pixel electrode is arranged on described flatness layer.
Preferably, described public electrode with the extended line of the boundary of adjacent subpixels in described multiple sub-pixel for symmetry axis.
The invention allows for a kind of display unit, comprise display base plate described above.
The invention allows for a kind of display base plate manufacture method, comprising:
Form color rete, wherein, described color rete comprises multiple sub-pixel;
Form common electrode layer in described color film layer, on described common electrode layer, form black matrix layer;
Described common electrode layer and black matrix layer are etched, to form the public electrode corresponding with the intersection of adjacent subpixels in described multiple sub-pixel and black matrix.
Preferably, also comprised before the described color rete of formation:
Substrate forms thin-film transistor;
On described thin-film transistor, form the first passivation layer, wherein, described color rete is formed on described first passivation layer;
Pixel electrode is formed in described color film layer;
On described pixel electrode, form the second passivation layer, wherein, described public electrode is formed on described second passivation layer.
Preferably, form flatness layer in described color film layer, wherein, described pixel electrode is formed on described flatness layer.
According to technique scheme, by by black arranged in matrix on public electrode, wherein public electrode is corresponding with the intersection of adjacent subpixels, also the black matrix be namely arranged on public electrode is also corresponding with the intersection of adjacent subpixels, ensure that the compartmentation of black matrix to adjacent subpixels, and because black matrix is away from thin-film transistor, avoids and the electrology characteristic of thin-film transistor is impacted.
Accompanying drawing explanation
Can understanding the features and advantages of the present invention clearly by reference to accompanying drawing, accompanying drawing is schematic and should not be construed as and carry out any restriction to the present invention, in the accompanying drawings:
Fig. 1 shows the plan structure schematic diagram of common array substrate in prior art;
Fig. 2 to show in Fig. 1 array base palte along the schematic cross-section of AA ';
Fig. 3 to show in Fig. 1 array base palte along the schematic cross-section of BB ';
Fig. 4 show according to an embodiment of the invention display base plate perpendicular to the schematic cross-section of data wire;
Fig. 5 show according to an embodiment of the invention display base plate perpendicular to the schematic cross-section of grid line;
Fig. 6 shows the relation schematic diagram of public electrode position and transmitance;
Fig. 7 shows the schematic flow diagram of display base plate manufacture method according to an embodiment of the invention;
Fig. 8 to Figure 11 shows the concrete schematic flow diagram of display base plate manufacture method according to an embodiment of the invention;
The technique number of times that Figure 12 shows prior art and one embodiment of the invention contrasts schematic diagram;
Drawing reference numeral illustrates:
1-public electrode; The black matrix of 2-; 3-substrate; 4-first passivation layer; 5-pixel electrode; 6-second passivation layer; 7-flatness layer; 8-data wire; 9-grid line; 10-gate insulation layer; 11-first sub-pixel; 12-second sub-pixel.
Embodiment
In order to more clearly understand above-mentioned purpose of the present invention, feature and advantage, below in conjunction with the drawings and specific embodiments, the present invention is further described in detail.It should be noted that, when not conflicting, the feature in the embodiment of the application and embodiment can combine mutually.
Set forth a lot of detail in the following description so that fully understand the present invention; but; the present invention can also adopt other to be different from other modes described here and implement, and therefore, protection scope of the present invention is not by the restriction of following public specific embodiment.
As shown in Figure 4 and Figure 5, display base plate according to an embodiment of the invention, comprising:
Color rete, comprises multiple sub-pixel, illustrate only the first sub-pixel 11 and the second sub-pixel 12, can also comprise other sub-pixels in Fig. 4;
Public electrode 1, is arranged on color film layer, corresponding with the intersection of adjacent subpixels in multiple sub-pixel;
Black matrix 2, is arranged on public electrode 1.
The present embodiment is by being arranged on public electrode 1 by black matrix 2, wherein public electrode 1 is corresponding with the intersection of adjacent subpixels, also the black matrix 1 be namely arranged on public electrode 2 is also corresponding with the intersection of adjacent subpixels, ensure that the compartmentation of black matrix 1 pair of adjacent subpixels, and because black matrix 1 is away from thin-film transistor, avoids and the performance of thin-film transistor is impacted.
And black matrix 1 is arranged on public electrode 2, because black matrix of the present invention is metal or the metal composite layer relative to public electrode 1 with excellent conductive performance, the effect of conduction current can be played together with public electrode 1, therefore the conduction uniformity of public electrode 1 can be improved, and then improve Greenish, improve display effect.
It should be noted that, the public electrode 2 in the present embodiment not directly contacts with color rete, is just spatially positioned at above color rete.
Preferably, the reflectivity of black matrix 2 is less than default reflectivity.
Black matrix 2 there is lower reflectivity, effectively can reduce the reflection of black matrix 2 pairs of surround lightings, prevent the reduction of the display comparison degree caused due to reflection of ambient light, improve display effect.Such as can make black matrix 2 by selecting certain material, the reflectivity of black matrix 2 being limited to less than 10% (namely presetting reflectivity is 10%).Such as the thickness of black matrix 2 can also be set to
, to ensure that it has good shaded effect, and then ensure the sub-pixel of black matrix 2 separating adjacent well.
Preferably, the anti-corrosion scale of black matrix 2 is lower than the anti-corrosion scale of public electrode.
In the present embodiment, black matrix 2 and public electrode 1 is made by selecting certain material, black matrix 2 can be made more easily to be etched than public electrode 1, formed in the technical process of common pattern of electrodes by a masking process, can carry out etching to common electrode layer and black matrix layer simultaneously form public electrode and black matrix, and after etching, the width of black matrix 2 is less than the width of public electrode 1.
Usually, the width of black matrix 2 is less than the width of public electrode 11 to 2 micron.
Preferably, black matrix 2 is metal simple-substance, such as Al, Cr, Cu, Mo or Ti;
Or metal alloy, such as Al/Nd alloy, Cu/Mo alloy, Mo/Ta alloy, Al/Mo alloy or Mo/Nb alloy;
Or the composite bed that metal simple-substance and metal alloy are formed, the composite bed be such as made up of Mo/Al/Mo, the composite bed be made up of Cu/ITO/Ti or the composite bed be made up of Mo/Cu/Ti;
Or composite bed, the composite bed be such as made up of Mo/MoON or the composite bed be made up of Cu/CuMoN that the composite bed that forms of metal oxide, nitride and nitrogen oxide or metal alloy oxide, nitride and nitrogen oxide are formed.
Make black matrix 2 by above-mentioned material, can ensure that black matrix 2 easily etches than public electrode (such as ITO), and reflectivity is less than default reflectivity, transmitance is less than default transmitance.
Preferably, also comprise:
Substrate 3;
Thin-film transistor (not shown), be arranged on substrate 3, comprising structures such as grid, source electrode, drain electrode, active layers, grid is electrically connected with grid line 9, be provided with gate insulation layer 10 on grid line 9, on gate insulation layer 10, be provided with the first passivation layer 4;
First passivation layer 4, is arranged on thin-film transistor, such as, can be arranged on the gate insulation layer 10 in thin-film transistor, and wherein, color rete is arranged on the first passivation layer 4;
Pixel electrode 5, is arranged on color film layer;
Second passivation layer 6, is arranged on pixel electrode 5, and wherein, public electrode 1 is arranged on the second passivation layer 6.
Pixel electrode 5 in the present embodiment and public electrode 1 are all positioned at display base plate, the such as display base plate of ADS pattern or IPS, public electrode 1 wherein for gap electrode width be 2 ~ 3um, the electric field being parallel to substrate produced mainly through edge makes liquid crystal deflect, electric field directly over public electrode 1 is then more weak, liquid crystal is made to deflect hardly, therefore transmitance is very low, as shown in Figure 6, be provided with the position transmitance of public electrode 1 below 20%, and because the width of the black matrix 2 arranged above public electrode 1 is less than public electrode 1 width, width is less than 1um, therefore the transmitance that black matrix 2 also affects substrate is hardly set above public electrode 1.
Preferably, also comprise:
Flatness layer 7, is arranged on color film layer, and wherein, pixel electrode 5 is arranged on flatness layer 7.
Because the color rete upper surface formed is not generally smooth, by arranging flatness layer 7 in color film layer, planarization conditions can be provided for the formation of succeeding layer structure.
Preferably, described public electrode 1 with the extended line of the boundary of adjacent subpixels in described multiple sub-pixel for symmetry axis.
Display unit comprises above-mentioned display base plate according to an embodiment of the invention.
It should be noted that, the display unit in the present embodiment can be: any product or parts with Presentation Function such as Electronic Paper, mobile phone, panel computer, television set, notebook computer, DPF, navigator.
As shown in Figure 7, display base plate manufacture method according to an embodiment of the invention, comprising:
S3, forms color rete, and wherein, color rete comprises multiple sub-pixel;
S6, forms common electrode layer in color film layer, forms black matrix layer, as shown in Figure 8 on common electrode layer; And then black matrix forms photoresist 20, as shown in Figure 9;
S7, etches common electrode layer and black matrix layer, to form the public electrode 1 corresponding with the intersection of adjacent subpixels in multiple sub-pixel and black matrix 2, as shown in Figure 10, then removes photoresist 20, as shown in figure 11.
Preferably, also comprised before the color rete of formation:
S1, substrate 3 forms thin-film transistor;
S2, forms the first passivation layer 4 on thin-film transistor, and wherein, color rete is formed on the first passivation layer 4;
S4, forms pixel electrode 5 in color film layer;
S5, forms the second passivation layer 6 on pixel electrode 5, and wherein, public electrode 1 is formed on the second passivation layer 6.
Preferably, form flatness layer 7 in color film layer, wherein, pixel electrode 5 is formed on flatness layer 7.
Wherein, the formation process that above-mentioned flow process adopts such as can comprise: the patterning processes such as film-forming process and etching such as deposition, sputtering.
As shown in figure 12, black matrix 1 of the prior art is arranged in color rete, needs to form red, green, blue sub-pixel and black matrix respectively, totally four masking process when forming color rete.And in the present embodiment, formed when black matrix 1 can form the figure of public electrode 2, decrease a masking process, thus simplify Making programme. simultaneously
More than be described with reference to the accompanying drawings technical scheme of the present invention, considered in existing COA technology, black matrix distance thin-film transistor is comparatively near, easily impacts the performance of thin-film transistor.The present invention passes through black arranged in matrix on public electrode, wherein public electrode is corresponding with the intersection of adjacent subpixels, also the black matrix be namely arranged on public electrode is also corresponding with the intersection of adjacent subpixels, ensure that the compartmentation of black matrix to adjacent subpixels, and because black matrix is away from thin-film transistor, avoids and the electrology characteristic of thin-film transistor is impacted.
It is pointed out that in the accompanying drawings, in order to the illustrated clear size that may be exaggerated layer and region.And be appreciated that when element or layer be called as another element or layer " on " time, directly on other elements, or can there is middle layer in it.In addition, being appreciated that when element or layer are called as at another element or layer D score, directly under other elements, or can there is layer or the element of more than one centre in it.In addition, be further appreciated that when layer or element be called as two-layer or two elements " between " time, it can be two-layer or layer only between two elements, maybe can also there is more than one intermediate layer or element.Reference marker similar in the whole text indicates similar element.
In the present invention, term " first ", " second " only for describing object, and can not be interpreted as instruction or hint relative importance.Term " multiple " refers to two or more, unless otherwise clear and definite restriction.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1. a display base plate, is characterized in that, comprising:
Color rete, comprises multiple sub-pixel;
Public electrode, is arranged on described color film layer, corresponding with the intersection of adjacent subpixels in described multiple sub-pixel;
Black matrix, is arranged on described public electrode.
2. display base plate according to claim 1, is characterized in that, the reflectivity of described black matrix is less than default reflectivity.
3. display base plate according to claim 2, is characterized in that, the anti-corrosion scale of described black matrix is lower than the anti-corrosion scale of described public electrode.
4. display base plate according to claim 3, it is characterized in that, described black matrix is metal simple-substance, or metal alloy, or the composite bed that metal simple-substance and metal alloy are formed, or the composite bed that metal oxide, nitride and nitrogen oxide are formed, or the composite bed that metal alloy oxide, nitride and nitrogen oxide are formed.
5. display base plate according to any one of claim 1 to 4, is characterized in that, also comprises:
Substrate;
Thin-film transistor, is arranged on described substrate;
First passivation layer, is arranged on described thin-film transistor, and wherein, described color rete is arranged on described first passivation layer;
Pixel electrode, is arranged on described color film layer;
Second passivation layer, is arranged on described pixel electrode, and wherein, described public electrode is arranged on described second passivation layer.
6. display base plate according to claim 5, is characterized in that, also comprises:
Flatness layer, is arranged on described color film layer, and wherein, described pixel electrode is arranged on described flatness layer.
7. display base plate according to any one of claim 1 to 4, is characterized in that, described public electrode with the extended line of the boundary of adjacent subpixels in described multiple sub-pixel for symmetry axis.
8. a display unit, is characterized in that, comprises the display base plate according to any one of claim 1 to 7.
9. a display base plate manufacture method, is characterized in that, comprising:
Form color rete, wherein, described color rete comprises multiple sub-pixel;
Form common electrode layer in described color film layer, on described common electrode layer, form black matrix layer;
Described common electrode layer and black matrix layer are etched, to form the public electrode corresponding with the intersection of adjacent subpixels in described multiple sub-pixel and black matrix.
10. display base plate manufacture method according to claim 9, is characterized in that, also comprises before the described color rete of formation:
Substrate forms thin-film transistor;
On described thin-film transistor, form the first passivation layer, wherein, described color rete is formed on described first passivation layer;
Pixel electrode is formed in described color film layer;
On described pixel electrode, form the second passivation layer, wherein, described public electrode is formed on described second passivation layer.
11. display base plate manufacture methods according to claim 10, is characterized in that, form flatness layer in described color film layer, wherein, described pixel electrode is formed on described flatness layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510416554.4A CN105097836B (en) | 2015-07-15 | 2015-07-15 | Display base plate and preparation method thereof and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510416554.4A CN105097836B (en) | 2015-07-15 | 2015-07-15 | Display base plate and preparation method thereof and display device |
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| CN105097836A true CN105097836A (en) | 2015-11-25 |
| CN105097836B CN105097836B (en) | 2019-02-22 |
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| CN201510416554.4A Active CN105097836B (en) | 2015-07-15 | 2015-07-15 | Display base plate and preparation method thereof and display device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105629544A (en) * | 2016-01-14 | 2016-06-01 | 京东方科技集团股份有限公司 | Display base plate and manufacturing method of display base plate as well as display panel and display device |
| CN109239994A (en) * | 2018-10-25 | 2019-01-18 | 京东方科技集团股份有限公司 | array substrate and display device |
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| US20020101557A1 (en) * | 2001-01-29 | 2002-08-01 | Hitachi, Ltd. | Liquid crystal display device |
| CN101398572A (en) * | 2007-09-29 | 2009-04-01 | 北京京东方光电科技有限公司 | LCD and method for making conductive spacer therein |
| CN103353699A (en) * | 2013-06-24 | 2013-10-16 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display device |
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2015
- 2015-07-15 CN CN201510416554.4A patent/CN105097836B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020101557A1 (en) * | 2001-01-29 | 2002-08-01 | Hitachi, Ltd. | Liquid crystal display device |
| CN101398572A (en) * | 2007-09-29 | 2009-04-01 | 北京京东方光电科技有限公司 | LCD and method for making conductive spacer therein |
| CN103353699A (en) * | 2013-06-24 | 2013-10-16 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105629544A (en) * | 2016-01-14 | 2016-06-01 | 京东方科技集团股份有限公司 | Display base plate and manufacturing method of display base plate as well as display panel and display device |
| CN105629544B (en) * | 2016-01-14 | 2019-11-01 | 京东方科技集团股份有限公司 | Display base plate and its manufacturing method, display panel and display device |
| CN109239994A (en) * | 2018-10-25 | 2019-01-18 | 京东方科技集团股份有限公司 | array substrate and display device |
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| Publication number | Publication date |
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| CN105097836B (en) | 2019-02-22 |
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