CN105097505A - Manufacture method of polysilicon emitter of transistor - Google Patents
Manufacture method of polysilicon emitter of transistor Download PDFInfo
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- CN105097505A CN105097505A CN201410160444.1A CN201410160444A CN105097505A CN 105097505 A CN105097505 A CN 105097505A CN 201410160444 A CN201410160444 A CN 201410160444A CN 105097505 A CN105097505 A CN 105097505A
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Abstract
The invention relates to a manufacture method of a polysilicon emitter of a transistor. The manufacture method comprises that the surface, which comprises an N type collection region, a P type base region, a first oxide layer and a second oxide layer, of a substrate is lithographed and etched to form an emission region window and expose the P type base region whose width is the same with that of the emission region window; un-doped polysilicon is deposited at the surfaces of the first oxide layer and the second oxide layer and in the emission region window so that the un-doped polysilicon completely covers the emission region window; the surface, deposited with the un-doped polysilicon, of the substrate is lithographed and etched to remove un-doped polysilicon beyond the emission region window; doped elements are injected into the un-doped polysilicon in the emission region window by ion implantation technology; and first heat treatment is carried out on the substrate with injected doped elements so that the doped elements in the polysilicon in the emission region window are diffused to the surface layer of the exposed P type base region to form an N type diffusion region.
Description
Technical field
The present invention relates to semiconductor device processing technology field, the method that the polysilicon emitter particularly relating to a kind of transistor manufactures.
Background technology
Bipolar transistor is made up of emitter region, base, collector region.According to its conduction type, bipolar transistor can be divided into NPN transistor and PNP transistor, wherein the emitter region of NPN transistor and collector region are N type semiconductor, base is P type semiconductor, according to the type of its emitter region, transistor can be categorized as monocrystalline emitter transistor and polysilicon emitter transistor, the former emitter region is the monocrystalline silicon of N-type doping, the emitter region of the latter is the polysilicon of N-type doping, wherein polysilicon emitter transistor is mainly used in high frequency field, and its cross-sectional view as shown in Figure 1.
Polysilicon emitter transistor shown in Fig. 1 comprises N-type collector region 11, P type base 12, and the emitter region to be jointly made up of N-type diffusion region 13 and N-type polycrystalline silicon, wherein, N-type polycrystalline silicon to be positioned among silicon dioxide window (being referred to as " emitter window 14 ") and directly to contact with the surface of P type base 12 bottom it.In practiced processes, N-type diffusion region 13 is formed to the top layer of P type base 12 by the thermal diffusion under uniform temperature environment of the doped chemical (phosphorus, arsenic or antimony) in N-type polycrystalline silicon.The region that thick oxide layer 15 shown in Fig. 1 covers is place, and the region that thin oxide layer 16 covers is active area.
Semiconductor fabrication process is the series of process step implemented on a semiconductor wafer, and semiconductor crystal wafer is the semiconductor monocrystal of disc, comprises silicon, germanium wafer etc.The method of the polysilicon emitter of existing making polysilicon emitter transistor comprises:
Including N-type collector region 11, P type base 12, thick oxide layer 15, photoetching is carried out on the surface of the substrate of thin oxide layer 16, etching technics forms emitter window 14, expose the P type base 12 in emitter window 14 region, then the unadulterated polysilicon of deposit, then ion implantation technology is adopted to adulterate to polysilicon, form N-type polycrystalline silicon, then heat-treat, the doped chemical in the polysilicon in emitter window 14 is made to diffuse among the top layer of P type base 12, form N-type diffusion region 13, then photoetching is carried out, etching technics removes the polysilicon of the exterior domain in described emitter window region, form polysilicon emitter (not marking in Fig. 1).For ensureing when a small amount of deviation of the alignment appears in photoetching process, polysilicon emitter still can cover emitter window 14 region completely, and the width (distance between left side wall 17 and right-side wall 18) of polysilicon emitter is all greater than the width of emitter window 14 usually.
Because polysilicon is made up of numerous little crystal grain, the technological temperature of the unadulterated polysilicon of deposit is generally 600-650 degree Celsius, more much lower than above-mentioned heat treated temperature (being generally greater than 900 degrees Celsius), therefore in process of thermal treatment process, crystal grain in polysilicon can become large, can recrystallization be there is in the surface of polycrystalline silicon membrane, these all can cause polysilicon to produce stress to emitter window 14, cause semiconductor crystal wafer generation deformation, to such an extent as to the alignment precision of above-mentioned polysilicon layer photoetching is not high, in order to ensure when larger deviation of the alignment appears in photoetching process, polysilicon emitter still can cover emitter window 14 region completely, the width that must design polysilicon emitter is more much larger than the width of emitter window 14, this just causes chip area to become large, cost up.
Summary of the invention
The method that the polysilicon emitter that the invention provides a kind of transistor manufactures, causes in order to the stress realizing avoiding heat treatment to produce the problem that polysilicon layer lithography alignment accuracy is not high, thus reduces chip area, saving process costs.
The method that the polysilicon emitter that the invention provides a kind of transistor manufactures, comprising:
Include N-type collector region, P type base, the first oxide layer, the second oxide layer substrate surface carry out photoetching, etching, formed emitter window, expose the P type base region identical with emitter window width;
The unadulterated polysilicon of deposit in the surface and emitter window of the first oxide layer, the second oxide layer, covers emitter window region completely to make unadulterated polysilicon;
Substrate surface after the unadulterated polysilicon of deposit carries out photoetching, etching, and remove the unadulterated polysilicon of the exterior domain in emitter window region, the width of the unadulterated polysilicon of reservation is more than or equal to the width of emitter window;
Adopt ion implantation technology to the unadulterated polysilicon dopant implant element in emitter window;
First heat treatment is carried out to the substrate after dopant implant element, among the top layer in the region, P type base making the doped chemical in the polysilicon in emitter window diffuse to expose, forms N-type diffusion region.
The method of the polysilicon emitter manufacture of transistor of the present invention, by including N-type collector region, P type base, first oxide layer, the substrate surface of the second oxide layer carries out photoetching, etching, after exposing the P type base in emitter window region, the unadulterated polysilicon of deposit, unadulterated polysilicon is made to cover emitter window region completely, photoetching is carried out again by the substrate surface after the unadulterated polysilicon of deposit, etching, remove the unadulterated polysilicon of the exterior domain in emitter window region, then to the unadulterated polysilicon dopant implant element in emitter window, and carry out the first heat treatment, among the top layer in the region, P type base making the doped chemical in the polysilicon in emitter window diffuse to expose, form N-type diffusion region, obtain the polysilicon emitter of transistor.By above-mentioned after polysilicon deposition, first carry out photoetching, etching, then just carry out the first heat treatment, the stress that efficiently avoid because of heat treatment generation causes the technical problem that the alignment precision of polysilicon layer photoetching is not high, thus realizes reducing chip area, saving process costs.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of polysilicon emitter transistor;
Fig. 2 is the flow chart of the embodiment one of the method that the polysilicon emitter of transistor of the present invention manufactures;
Fig. 3 is the cross-sectional view after the emitter window of the embodiment of the present invention one is formed;
Fig. 4 is the cross-sectional view after the unadulterated polysilicon of deposit of the embodiment of the present invention one;
Fig. 5 is the embodiment of the present invention one photoetching, etch unadulterated polysilicon after cross-sectional view;
Fig. 6 is the cross-sectional view after the dopant implant element of the embodiment of the present invention one;
Fig. 7 is the cross-sectional view after the first heat treatment of the embodiment of the present invention one;
Fig. 8 is the cross-sectional view after performing step 104 after the step 102 of the embodiment of the present invention one;
Fig. 9 is the flow chart of the embodiment two of the method that the polysilicon emitter of transistor of the present invention manufactures.
Embodiment
Fig. 2 is the flow chart of the embodiment one of the method that the polysilicon emitter of transistor of the present invention manufactures, and as shown in Figure 2, the method for the present embodiment comprises:
Step 101, including N-type collector region 11, the substrate surface of P type base 12, first oxide layer 15, second oxide layer 16 carries out photoetching, etching, form emitter window 14, expose P type base 12 region identical with emitter window 14 width, the cross-sectional view after concrete structure is formed see the emitter window of Fig. 3.
Semiconductor fabrication process is the series of process step implemented on a semiconductor wafer, and semiconductor crystal wafer is the semiconductor monocrystal of disc, comprises silicon, germanium wafer etc.
First on single crystal wafer, produce N-type collector region 11, then make silicon dioxide oxide layer on top layer, existing N-type collector region 11, obtain the first oxide layer 15, define place; Again by doping process, do not produced P type base 12 by the top layer, N-type collector region 11 of the active area of the first oxide layer 15 region overlay; Again forming N-type collector region 11, the top layer of P type base 12 and the first oxide layer 15 grows the second oxide layer 16, wherein, the second oxide layer 16 to the first oxide layer 15 is thin, and the first oxidated layer thickness scope 5000 to 20000 dust, is commonly referred to thick oxide layer; Second oxidated layer thickness scope 200 to 4000 dust, is commonly referred to thin oxide layer; Preferred: the second oxidated layer thickness 1000 dust, the first oxidated layer thickness 10000 dust.
Thus form the substrate including N-type collector region 11, P type base 12, first oxide layer 15, second oxide layer 16.
Then, including N-type collector region 11, the substrate surface of P type base 12, first oxide layer 15, second oxide layer 16 carries out photoetching and etching technics, wherein photoetching and etching technics comprise: the operation such as crystal column surface cleaning, drying, linging, spin coating photoresist, soft baking, aligning exposure, rear baking, development, hard baking, etching, detection, and photoetching can adopt the methods such as contact exposure, proximity printing or projection exposure; Etching can adopt dry etching or wet etching.Wafer top layer after photoetching and etching forms emitter window 14, and exposes the region, part P type base 12 of width same with emitter window 14.
Step 102, in the surface and this emitter window 14 of this first oxide layer 15, second oxide layer 16 the unadulterated polysilicon 19 of deposit, to make unadulterated polysilicon 19 cover this emitter window 14 region completely, concrete structure is see the cross-sectional view after the unadulterated polysilicon of Fig. 4 deposit.
Step 103, substrate surface after the unadulterated polysilicon 19 of this deposit carry out photoetching, etching, remove the unadulterated polysilicon 19 of the exterior domain in this emitter window 14 region, the width of unadulterated polysilicon 19 retained is more than or equal to the width of emitter window 14, concrete structure see Fig. 5 photoetching, etch the cross-sectional view after unadulterated polysilicon.
Photoetching herein, etching technics are referred to as again polysilicon layer photoetching, etching, and this technique is the polysilicon in order to remove the region outside emitter window 14 region, thus form polysilicon emitter.When for ensureing to occur a small amount of deviation of the alignment in a lithographic process, polysilicon emitter still can cover the region of emitter window 14 completely, and the width (distance between left side wall 17 and right-side wall 18) of polysilicon emitter is all greater than the width of emitter window 14 usually.The deviation surplus reserved for the alignment procedures of photoetching process in the present embodiment is: the width of the unadulterated polysilicon 19 of reservation exceeds 0.1 to 0.5 micron, emitter window 14 edge, thus makes the polysilicon still retaining intact covering in the emitter window 14 after polysilicon layer photoetching, etching.
Step 104, employing ion implantation technology are to the unadulterated polysilicon dopant implant element 20 in this emitter window, and concrete structure is see the cross-sectional view after Fig. 6 dopant implant element.
Ion implantation technology is adopted to adulterate to polysilicon, doped chemical 20 is phosphorus, arsenic or antimony, namely ion implantation is carried out to the substrate formed in step 103, in the region being coated with polysilicon, doped chemical 20 is injected among polysilicon, and not by the region that polysilicon covers, doped chemical is injected among oxide layer, due to oxide layer among transistor just as insulating barrier, being filled with doped chemical 20 does not affect its function as insulating barrier.
Step 105, the first heat treatment is carried out to the substrate after dopant implant element 20, diffuse among the top layer in the region, P type base 12 that this exposes to make the doped chemical 20 in the polysilicon in this emitter window 14, form N-type diffusion region 13, concrete structure is see the cross-sectional view after Fig. 7 first heat treatment.
First heat treatment is carried out to the substrate after dopant implant element 20, makes doped chemical 20 at sufficiently high temperature, have electroactive, thus among the top layer diffusing to the region, P type base 12 of exposing, define N-type diffusion region 13.In order to the shortening heat processing time, namely the speed of heat treatment heating-cooling is accelerated, thus obtain less process heat budget, first heat treatment of the present embodiment can adopt rapid thermal treatment (RapidThermalProcess, be called for short: RTP), first heat treated temperature is 900 to 1150 degrees Celsius, and the time is 10 to 200 seconds.Wherein, preferably, can arrange the first heat treated temperature is 1000 degrees Celsius, and the time is 30 seconds; Or temperature is 1020 degrees Celsius, the time is 20-40 second; Or temperature is 1050 degrees Celsius, the time is 20 seconds, to obtain best doped chemical diffusion effect.
It should be noted that, the order of step 103 and step 104 can be exchanged, if the ion implantation technology of step 104 is before the photoetching, etching technics of step 103, then when ion implantation, because the substrate surface formed after step 102 is all covered by polysilicon, therefore doped chemical is just injected among polysilicon, can not be injected among oxide layer, therefore, the polysilicon emitter structure obtained after above-mentioned two sequence of steps displacement is the same.The cross-sectional view after the dopant implant element technique of step 104 is performed see Fig. 8 after step 102; The cross-sectional view performed after step 104 after the photoetching of step 103, etching technics is identical with Fig. 6.
The present embodiment is by including N-type collector region, P type base, first oxide layer, the substrate surface of the second oxide layer carries out photoetching, etching, after exposing the P type base in emitter window region, the unadulterated polysilicon of deposit, unadulterated polysilicon is made to cover emitter window region completely, photoetching is carried out again by the substrate surface after the unadulterated polysilicon of deposit, etching, remove the unadulterated polysilicon of the exterior domain in emitter window region, then to the unadulterated polysilicon dopant implant element in emitter window, and carry out the first heat treatment, among the top layer in the region, P type base making the doped chemical in the polysilicon in emitter window diffuse to expose, form N-type diffusion region, obtain the polysilicon emitter of transistor.By above-mentioned after polysilicon deposition, first carry out photoetching, etching, then just carry out the first heat treatment, the stress effectively avoided because of heat treatment generation causes the technical problem that the alignment precision of polysilicon layer photoetching is not high, thus realizes reducing chip area, saving process costs.
Fig. 9 is the flow chart of the embodiment two of the method that the polysilicon emitter of transistor of the present invention manufactures, and as shown in Figure 9, the method for the present embodiment comprises:
Step 201, including N-type collector region 11, the substrate surface of P type base 12, first oxide layer 15, second oxide layer 16 carries out photoetching, etching, form emitter window 14, expose P type base 12 region identical with this emitter window 14 width, the cross-sectional view after concrete structure is formed see the emitter window of Fig. 3.
The specific implementation process of this step, see the step 101 in embodiment one, repeats no more herein.
Step 202, the second heat treatment is carried out to the substrate exposed after region, P type base 12, to repair the damage in region, P type base 12.
Form the etching technics of emitter window 14, make to produce damage on the top layer of the P type base 12 in emitter window 14 region, when carrying out the first heat treatment, doped chemical (phosphorus in polysilicon, arsenic or antimony) very fast along the Speed of diffusion of damage field, the depth ratio of the N-type diffusion region 13 formed is larger, cause the operating frequency of transistor less, in order to ensure that transistor has sufficiently high operating frequency in practice, require that the degree of depth of the N-type diffusion region 13 among top layer, P type base 12 is tried one's best shallow, so the present embodiment is in photoetching, after etching forms emitter window 14, second heat treatment is carried out to the substrate exposed after region, P type base 12, make impaired in etching technics and the lattice of confusion is recombinated, reach the effect of the damage that reparation is formed on top layer, P type base 12 due to etching technics, thus the thermal diffusion among the top layer of P type base that there is damage of the doped chemical in existing method in polysilicon can be avoided very fast, the depth ratio of the N-type diffusion region formed is larger, cause the problem that the operating frequency of transistor is less.
Second heat treatment of the present embodiment can adopt rapid thermal treatment, and the temperature of the second rapid thermal treatment is 950 to 1150 degrees Celsius, and the time is 10 to 200 seconds.Preferably, can arrange the second heat treated temperature is 1050 degrees Celsius, and the time is 60 seconds; Or temperature is 1100 degrees Celsius, the time is 30 seconds; Or temperature is 1150 degrees Celsius, the time is 50 seconds.To obtain the effect of best reparation damage.In addition, the second heat treatment can also adopt boiler tube heat treatment, and temperature is 800 to 1150 degrees Celsius, and the time is 10 to 300 minutes.Preferably, can arrange the second heat treated temperature is 980 degrees Celsius, and the time is 30 minutes; Or temperature is 1050 degrees Celsius, the time is 50 minutes; Or temperature is 1100 degrees Celsius, the time is 90 minutes, to obtain the effect of best reparation damage.
Step 203, in the surface and this emitter window 14 of this first oxide layer 15, second oxide layer 16 the unadulterated polysilicon 19 of deposit, to make unadulterated polysilicon 19 cover emitter window 14 region completely, concrete structure is see the cross-sectional view after the unadulterated polysilicon of Fig. 4 deposit.
Step 204, substrate surface after the unadulterated polysilicon 19 of this deposit carry out photoetching, etching, remove the unadulterated polysilicon 19 of the exterior domain in emitter window 14 region, the width of unadulterated polysilicon 19 retained is more than or equal to the width of emitter window 14, concrete structure see Fig. 5 photoetching, etch the cross-sectional view after unadulterated polysilicon.
The specific implementation process of this step, see the step 103 in embodiment one, repeats no more herein.
Step 205, employing ion implantation technology are to the unadulterated polysilicon 19 dopant implant element 20 in this emitter window 14, and concrete structure is see the cross-sectional view after Fig. 6 dopant implant element.
The specific implementation process of this step, see the step 104 in embodiment one, repeats no more herein.
Step 206, the first heat treatment is carried out to the substrate after dopant implant element 20, diffuse among the top layer in the region, P type base 12 that this exposes to make the doped chemical 20 in the polysilicon in this emitter window 14, form N-type diffusion region 13, concrete structure is see the cross-sectional view after Fig. 7 first heat treatment.
The specific implementation process of this step, see the step 105 in embodiment one, repeats no more herein.
It should be noted that, the order of step 204 and step 205 can be exchanged, and reason is identical with the reason that step 104 is replaced with the step 103 in embodiment one, does not repeat them here.
The present embodiment by include N-type collector region, P type base, the first oxide layer, the second oxide layer substrate surface carry out photoetching, etching, after exposing the P type base in emitter window region, second heat treatment is carried out to the substrate exposed after region, P type base, thus repair the damage in region, P type base, ensure that transistor has sufficiently high operating frequency; Then by the unadulterated polysilicon of deposit, unadulterated polysilicon is made to cover emitter window region completely, photoetching, etching is carried out again by the substrate surface after the unadulterated polysilicon of deposit, remove the unadulterated polysilicon of the exterior domain in emitter window region, then to the unadulterated polysilicon dopant implant element in emitter window, and carry out the first heat treatment, among the top layer in the region, P type base making the doped chemical in the polysilicon in emitter window diffuse to expose, form N-type diffusion region, obtain the polysilicon emitter of transistor.By above-mentioned after polysilicon deposition, first carry out photoetching, etching, then just carry out the first heat treatment, the stress that efficiently avoid because of heat treatment generation causes the technical problem that the alignment precision of polysilicon layer photoetching is not high, thus realizes reducing chip area, saving process costs.
Further, also comprise after step 206: the 3rd heat treatment is carried out, to discharge the stress in wafer to the substrate formed after N-type diffusion region.
In the first process of thermal treatment process; crystal grain in polysilicon can become greatly, the surface of polycrystalline silicon membrane recrystallization can occur; these all can cause polysilicon to produce stress to emitter window; because the first process of thermal treatment time is shorter; stress is made to be difficult to evenly discharge at short notice; therefore semiconductor crystal wafer generation deformation is caused; to such an extent as to the alignment precision of subsequent layers photoetching is not high; in order to discharge the stress in wafer; 3rd heat treatment is carried out to the substrate formed after N-type diffusion region, and the 3rd heat treated temperature is far smaller than the first heat treated temperature.3rd heat treated temperature is 350 to 700 degrees Celsius, and the time is 30 to 300 minutes.Preferably, can arrange the 3rd heat treated temperature is 475 degrees Celsius, and the time is 60 minutes; Or temperature is 550 degrees Celsius, the time is 30-90 minute; Or temperature is 650 degrees Celsius, the time is 30-90 minute, to obtain the effect of best release stress.
Can the stress that produces due to the first heat treatment of slow releasing by the 3rd heat treatment, thus the alignment precision of each photoetching after improving polysilicon emitter technique, reduce technology difficulty.
One of ordinary skill in the art will appreciate that: all or part of step realizing above-mentioned each embodiment of the method can have been come by the hardware that program command is relevant.Aforesaid program can be stored in a computer read/write memory medium.This program, when performing, performs the step comprising above-mentioned each embodiment of the method; And aforesaid storage medium comprises: ROM, RAM, magnetic disc or CD etc. various can be program code stored medium.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (10)
1. a method for the polysilicon emitter manufacture of transistor, is characterized in that, comprising:
Include N-type collector region, P type base, the first oxide layer, the second oxide layer substrate surface carry out photoetching, etching, formed emitter window, expose the P type base region identical with described emitter window width;
The unadulterated polysilicon of deposit in the surface and described emitter window of described first oxide layer, the second oxide layer, covers described emitter window region completely to make described unadulterated polysilicon;
Substrate surface after the unadulterated polysilicon of described deposit carries out photoetching, etching, removes the unadulterated polysilicon of the exterior domain in described emitter window region, and the width of the unadulterated polysilicon of reservation is more than or equal to the width of emitter window;
Adopt ion implantation technology to the unadulterated polysilicon dopant implant element in described emitter window;
First heat treatment is carried out to the substrate after dopant implant element, with make the doped chemical in the polysilicon in described emitter window diffuse to described among the top layer in region, P type base of exposing, form N-type diffusion region.
2. method according to claim 1, is characterized in that, in the described surface in described first oxide layer, the second oxide layer and described emitter window before the unadulterated polysilicon of deposit, also comprises:
Second heat treatment is carried out to the substrate exposed after region, P type base, to repair the damage in region, described P type base.
3. method according to claim 2, is characterized in that, described second heat treatment is rapid thermal treatment, and temperature is 950 to 1150 degrees Celsius, and the time is 10 to 200 seconds.
4. method according to claim 2, is characterized in that, described second heat treatment is boiler tube heat treatment, and temperature is 800 to 1150 degrees Celsius, and the time is 10 to 300 minutes.
5. method according to claim 1, is characterized in that, after described formation N-type diffusion region, also comprises:
3rd heat treatment is carried out, to discharge the stress in wafer to the substrate formed after N-type diffusion region.
6. method according to claim 5, is characterized in that, described 3rd heat treated temperature is 350 to 700 degrees Celsius, and the time is 30 to 300 minutes.
7. method according to claim 5, is characterized in that, described 3rd heat treated temperature is less than described first heat treated temperature.
8. the method according to any one of claim 1-7, is characterized in that, described first heat treatment is rapid thermal treatment.
9. method according to claim 8, is characterized in that, described first heat treated temperature is 900 to 1150 degrees Celsius, and the time is 10 to 200 seconds.
10. the method according to any one of claim 1-7, is characterized in that, the width of the unadulterated polysilicon of described reservation exceeds 0.1 to 0.5 micron, emitter window edge.
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