CN110391138A - A kind of ion injection method of memory - Google Patents
A kind of ion injection method of memory Download PDFInfo
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- CN110391138A CN110391138A CN201810347983.4A CN201810347983A CN110391138A CN 110391138 A CN110391138 A CN 110391138A CN 201810347983 A CN201810347983 A CN 201810347983A CN 110391138 A CN110391138 A CN 110391138A
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- 230000015654 memory Effects 0.000 title claims abstract description 70
- 238000002347 injection Methods 0.000 title claims abstract description 40
- 239000007924 injection Substances 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims abstract description 40
- 230000002093 peripheral effect Effects 0.000 claims abstract description 110
- 238000003860 storage Methods 0.000 claims abstract description 92
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 58
- 229920005591 polysilicon Polymers 0.000 claims abstract description 58
- 238000002360 preparation method Methods 0.000 claims abstract description 52
- 238000005530 etching Methods 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000005516 engineering process Methods 0.000 claims abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims description 35
- 239000010410 layer Substances 0.000 claims description 32
- 238000000137 annealing Methods 0.000 claims description 31
- 238000001259 photo etching Methods 0.000 claims description 15
- 239000011229 interlayer Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 238000004904 shortening Methods 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 55
- 230000000694 effects Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000004151 rapid thermal annealing Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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Abstract
The invention discloses a kind of ion injection methods of memory.This method comprises: the storage control gate of preparation peripheral polysilicon gate and storage unit in one side of substrate surface formation peripheral components, wherein preparation periphery polysilicon gate limits the source and drain injection region of storage unit with storage control gate；Source and drain ion implanting is lightly doped using self-registered technology progress storage unit；The peripheral polysilicon gate of preparation is performed etching, forms peripheral polysilicon gate in the setting control unit area of peripheral components；Carry out peripheral components is lightly doped source and drain ion implanting.The embodiment of the present invention limits the source and drain injection region of storage unit using the peripheral polysilicon gate of preparation and storage control gate; source and drain ion implanting is lightly doped using self-aligned technology progress storage unit; before ion implantation; without the need for the mask plate of protection peripheral components; simplify the preparation process flow of memory; the manufacturing cycle for shortening memory improves the preparation efficiency of memory.
Description
Technical field
The present embodiments relate to flash memories technology more particularly to a kind of ion injection methods of memory.
Background technique
For the 90/65nm node and NOR flash memory memory below of traditional handicraft production, Programming Principle is to pass through
To the drain terminal of the storage unit chosen and control grid while applying high voltage, channel is connected, in horizontal and vertical strong electrical field
Collective effect under, the thermoelectron that certain probability occurs near drain terminal for the carrier in channel is injected into floating gate, to change
The state of storage unit.When reading the state of certain storage unit chosen, every other non-selected storage on same root bit line
The electric leakage of unit must all obtain optimal control, otherwise may cause to choose storage unit " 0 " status error is read as "
1”。
To solve this problem, after the control gate of NOR flash memory memory is etched and to be formed, it is also necessary to memory cell region
Increase LDD (Lightly Doped Drain, source and drain is lightly doped) ion implantation technology, memory is adjusted by ion implanting
The doping concentration and Impurity Distribution of drain terminal, to guarantee the good programing effect of storage region and electric leakage control ability.
Fig. 1 is the flow chart of the ion injection method of existing memory, and Fig. 2 is the corresponding storage of step 11 in Fig. 1
The sectional view of device, Fig. 3 are the sectional views of the corresponding memory of step 12 in Fig. 1, and Fig. 4, which is that the step 13 in Fig. 1 is corresponding, to be deposited
The sectional view of reservoir, Fig. 5 are the sectional views of the corresponding memory of step 14 in Fig. 1, and Fig. 6, which is that step 15 is corresponding in Fig. 1, to be deposited
The sectional view of reservoir.As shown in figures 1 to 6, the memory ion injection method the following steps are included: step 11, in substrate 100
The surface of side forms the storage control gate of the preparation peripheral polysilicon gate and memory cell areas of peripheral components；Step 12, externally
It encloses prepared control unit to perform etching, forms peripheral polysilicon gate in the setting control unit area of peripheral components；Step 13, to peripheral device
The lightly-doped source of part leaks into row ion implanting；Step 14 is coated with and patterns photoresist in peripheral polysilicon gate, is deposited with limiting
The source and drain injection region of storage unit；Step 15 leaks into row ion implanting to the lightly-doped source of storage unit.As it can be seen that being stored
When source and drain ion implanting is lightly doped of unit area, for avoid storage unit be lightly doped source and drain ion implanting to high drive and
The peripheral components such as low voltage logic have an impact, and need to increase an additional mask and corresponding photoetching work in peripheral region
Skill, this will lead to memory, and the production cost increases, generates cycle stretch-out.
Summary of the invention
The present invention provides a kind of ion injection method of memory, to reduce the production cost and growth cycle of memory.
This method comprises:
The storage control gate of preparation the periphery polysilicon gate and storage unit of peripheral components is formed on one side of substrate surface,
In, the peripheral polysilicon gate of preparation and the source and drain injection region for storing control gate and limiting the storage unit；
Source and drain ion implanting is lightly doped using what self-registered technology carried out the storage unit；
The peripheral polysilicon gate of the preparation is performed etching, it is more to form periphery in the setting control unit area of the peripheral components
Crystal silicon grid；
Carry out the peripheral components is lightly doped source and drain ion implanting.
Further, the peripheral polysilicon gate of the preparation includes the gate insulating layer stacked gradually and peripheral gates layer, institute
Stating storage control gate includes the tunnel oxide stacked gradually, floating gate layer, interlayer insulating film and control grid layer；
The gate insulating layer and the tunnel oxide are prepared in different process, the peripheral gates layer and the control
Grid layer processed is prepared in same technique.
Further, the storage of the preparation peripheral polysilicon gate and storage unit that form peripheral components on one side of substrate surface
Control gate includes:
The peripheral polysilicon gate of preparation and storage control are formed on one side of substrate surface using photoetching, etching technics
Grid.
Further, include: using the source and drain ion implanting that is lightly doped that self-registered technology carries out the storage unit
Using the peripheral polysilicon gate of preparation and the control grid layer of the storage unit as exposure mask, to the lining exposed
Bottom carries out ion implanting；Alternatively,
Using the remaining photoresist after using the first photoetching, etching technics to form the storage control gate as exposure mask, to exposure
The substrate out carries out ion implanting.
Further, photoetching, etching are carried out to the peripheral polysilicon gate of the preparation, is controlled in the setting of the peripheral components
Area, portion forms peripheral polysilicon gate
The peripheral gates of the peripheral components are formed in the setting control unit area using photoetching, etching technics.
Further, the periphery of the peripheral components is being formed in the setting control unit area using photoetching, etching technics
After grid further include:
First annealing is carried out to the memory.
Further, the source and drain ion implanting that is lightly doped for carrying out the peripheral components includes:
Form the second photoresist, wherein storage unit described in second photoresist overlay, and second photoresist limits
Make the source and drain injection region of the peripheral components；
Using second photoresist as exposure mask, ion implanting at least once is carried out to the substrate exposed.
Further, after each ion implanting further include:
Second annealing is carried out to the memory.
The embodiment of the present invention is limited after forming storage control gate using the peripheral polysilicon gate of preparation and storage control gate
The source and drain injection region of storage unit is lightly doped source and drain ion implanting using self-aligned technology progress storage unit, infuses in ion
Before entering, without the need for the mask plate of protection peripheral components, the preparation process flow of memory is simplified, the system of memory is shortened
In the standby period, improve the preparation efficiency of memory.
Detailed description of the invention
Fig. 1 is the flow chart of the ion injection method of existing memory；
Fig. 2 is the sectional view of the corresponding memory of step 11 in Fig. 1；
Fig. 3 is the sectional view of the corresponding memory of step 12 in Fig. 1；
Fig. 4 is the sectional view of the corresponding memory of step 13 in Fig. 1；
Fig. 5 is the sectional view of the corresponding memory of step 14 in Fig. 1；
Fig. 6 is the sectional view of the corresponding memory of step 15 in Fig. 1；
Fig. 7 is the flow chart that source and drain ion injection method is lightly doped of memory provided in an embodiment of the present invention；
Fig. 8 is the sectional view of the corresponding memory of step 22 in Fig. 7 provided in an embodiment of the present invention；
Fig. 9 is the sectional view of the corresponding memory of step 23 in Fig. 7 provided in an embodiment of the present invention；
Figure 10 is the sectional view of the corresponding memory of step 24 in Fig. 7 provided in an embodiment of the present invention；
Figure 11 is the another sectional view of the corresponding memory of step 22 in Fig. 7 provided in an embodiment of the present invention.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limiting the invention.It also should be noted that in order to just
Only the parts related to the present invention are shown in description, attached drawing rather than entire infrastructure.
Fig. 7 is the flow chart that source and drain ion injection method is lightly doped of memory provided in an embodiment of the present invention, this method
It is applicable to the preparation of NOR flash memory memory.Fig. 8 is the corresponding memory of step 22 in Fig. 7 provided in an embodiment of the present invention
Sectional view, Fig. 9 is the sectional view of the corresponding memory of step 23 in Fig. 7 provided in an embodiment of the present invention, and Figure 10 is this hair
The sectional view for the corresponding memory of step 24 in Fig. 7 that bright embodiment provides.Fig. 2, Fig. 7 and Fig. 8-Figure 10 are please referred to, it should
Ion injection method may include:
Step 21 forms the preparation periphery polysilicon gate of peripheral components and depositing for storage unit in 100 1 side surface of substrate
Store up control gate, wherein preparation periphery polysilicon gate limits the source and drain injection region of the storage unit with storage control gate.
Specifically, referring to FIG. 2, needing before etching and forming the storage control gate of storage unit the one of substrate 100
Side growth is used to form peripheral polysilicon gate and stores the film layer of control gate, in the peripheral polysilicon gate of preparation far from substrate 100
Side forms the first photoresist 120.When forming peripheral polysilicon gate and storage control gate, the present embodiment can be initially formed storage
Control gate re-forms peripheral polysilicon gate.It, can be according to storage unit and its source and drain in the corresponding film layer of etching storage region
The suitable mask plate of the size selection in area, the peripheral polysilicon gate of mask plate covering preparation, and limit the source and drain note of storage unit
Enter area.It is understood that preparation periphery polysilicon gate is located at the periphery of memory, storage unit can in an array manner,
It is formed in the interior zone for the memory that the peripheral polysilicon gate of preparation is surrounded.
Source and drain ion implanting is lightly doped using self-registered technology progress storage unit in step 22.
Specifically, referring to FIG. 8, if before etching forms peripheral polysilicon gate, using self-registered technology to storage
The lightly-doped source of unit leaks into row ion implanting, since the peripheral polysilicon gate of preparation and storage control gate have defined that storage is single
The source and drain injection region of member, therefore, there is no need to form special mask plate ion implanting can be completed.Therefore, preparation periphery is utilized
The source and drain injection region for the storage unit that polysilicon gate and storage control gate limit, can save the technique to form mask plate, save
The preparation process flow of memory is saved.By ion implanting, first is formed in the lightly-doped source drain region of storage unit and is gently mixed
Miscellaneous source-drain structure 401.
Step 23 performs etching the peripheral polysilicon gate of preparation, and it is more to form periphery in the setting control unit area of peripheral components
Crystal silicon grid.
In general, the photoengraving pattern that different etching technics needs is not also identical, therefore, to the peripheral polysilicon of preparation
Grid perform etching, before the setting control unit area of peripheral components forms peripheral polysilicon gate, it is also necessary to remove the first photoresist
120, and new photoresist is formed, development is exposed to new photoresist, is removed in corresponding preparation peripheral polysilicon gate region
Photoresist in addition to setting control unit area further etches away the peripheral polysilicon gate of the preparation exposed, in peripheral components
Setting control unit area form peripheral polysilicon gate.
Step 24 carries out peripheral components and is lightly doped source and drain ion implanting.
Fig. 9 and Figure 10 are please referred to, after forming peripheral polysilicon gate, it is also necessary to carry out the lightly-doped source to peripheral components
Ion implanting is leaked, and forms the second lightly-doped source drain structure 402 in peripheral device region.Specifically, on the basis of step 23,
Coating photoresist again is exposed development to photoresist, limits the source and drain injection region (as shown in Figure 9) of peripheral components, so
Peripheral components are carried out afterwards source and drain ion implanting is lightly doped, forms the second lightly-doped source drain structure 402.In the present embodiment, due to
The ionic species or ion concentration adulterated in first lightly-doped source drain structure 401 and the first lightly-doped source drain structure 402 is different,
It carries out that ion implanting is individually lightly doped therefore, it is necessary to the source and drain injection region respectively to storage unit and peripheral components.
The embodiment of the present invention is limited after forming storage control gate using the peripheral polysilicon gate of preparation and storage control gate
The source and drain injection region of storage unit is lightly doped source and drain ion implanting using self-aligned technology progress storage unit, infuses in ion
Before entering, without the need for the mask plate of protection peripheral components, the preparation process flow of memory is simplified, the system of memory is shortened
In the standby period, improve the preparation efficiency of memory.
Optionally, referring to FIG. 2, preparation periphery polysilicon gate may include the gate insulating layer 310 that stacks gradually and outer
Grid layer 320 is enclosed, storage control gate includes the tunnel oxide 211 stacked gradually, floating gate layer 212, interlayer insulating film 213 and control
Grid layer 214 processed；Gate insulating layer 320 and tunnel oxide 211 can be prepared in different process, peripheral gates layer 320 and control
Grid layer 214 processed can be prepared in same technique.Optionally, when etching forms storage control gate, in peripheral 320 He of grid layer
Side of the control grid layer 214 far from substrate 100 can also include the first photoresist 120.It should be noted that the present invention is limited
Fixed memory includes but is not limited to structure shown in Fig. 2, Fig. 2 only the parts related to the present invention are shown structure, Er Feicun
The entire infrastructure of reservoir.
Optionally, the preparation periphery polysilicon gate of peripheral components and depositing for storage unit are formed in 100 1 side surface of substrate
Storage control gate includes: to form the peripheral polysilicon gate of preparation and storage control in 100 1 side surface of substrate using photoetching, etching technics
Grid.Specifically, during forming storage control gate, the first photoresist 120 is for covering and protecting the peripheral polysilicon of preparation
Grid, so that preparation periphery polysilicon gate is not etched.It is understood that common lithographic method includes wet etching and dry method
Etching etc., in all etching technics of the present embodiment, is not specifically limited lithographic method.
Figure 11 is the another sectional view of the corresponding reservoir of step 22 in Fig. 7 provided in an embodiment of the present invention.Optionally, it asks
With reference to Fig. 8 and Figure 11, it may include: outer with preparation for using self-registered technology to carry out the source and drain ion implanting that is lightly doped of storage unit
The control grid layer 214 for enclosing polysilicon gate 320 and storage unit is exposure mask, carries out ion implanting to the substrate 100 exposed；Or
Person, using the remaining photoresist after using the first photoetching, etching technics to form storage control gate as exposure mask, to the substrate exposed
100 carry out ion implanting.
It should be noted that the difference of Fig. 8 and Figure 11 is, source and drain ion implanting is lightly doped in progress storage unit
When, Fig. 8 remains the first photoresist 120, and Figure 11 then eliminates the first photoresist 120.Due to peripheral gates layer 320 and control
Grid layer 214 can limit the source and drain injection region of storage unit, therefore, regardless of whether retain the first photoresist 120,
Source and drain ion implanting is lightly doped with complete storage unit.
Referring to FIG. 9, optionally, being performed etching to the peripheral polysilicon gate of preparation, in the setting control unit area of peripheral components
Forming peripheral polysilicon gate includes: to form the peripheral gates 321 of peripheral components in setting control unit area using photoetching process；Together
When, the gate insulating layer 310 after etching forms insulating layer 311.
Optionally, use photoetching process can be with after the peripheral gates 321 that setting control unit area forms peripheral components
It include: that the first annealing is carried out to memory.Meanwhile first annealing additionally aid in the first lightly-doped source drain structure
The diffusion of Doped ions in 401.Annealing can eliminate stress in semiconductor, keep semiconductor structure more stable, can also be with
The diffusion rate of Doped ions in accelerated semiconductor, keeps the distribution of doped chemical more uniform.Commonly thermal annealing mode includes
Common thermal annealing and rapid thermal annealing, optionally, the first annealing can be rapid thermal annealing.Compared to common thermal annealing, fastly
Speed heat annealing can complete annealing within the extremely short time, and when requiring not very high to annealing temperature, sample surfaces need not
It is protected with deielectric-coating, simple process.
Fig. 9 and Figure 10 are please referred to, optionally, the source and drain ion implanting that is lightly doped for carrying out peripheral components may include: to be formed
Second photoresist 121, wherein the second photoresist 121 covers storage unit, and the second photoresist 121 limits peripheral components
Source and drain injection region；It is exposure mask with the second photoresist 121, ion implanting at least once is carried out to the substrate exposed.Optionally, outside
Being lightly doped after ion implanting can make annealing treatment first for peripheral device carry out.
It should be noted that the second photoresist 121 is formed in after the etching for completing the peripheral polysilicon gate of preparation, the second light
Photoresist 121 covers storage unit, can be used for protecting storage control gate；Meanwhile second photoresist 121 also cover peripheral polysilicon
Grid.Limit the source and drain injection region of peripheral components according to the edge of memory and the second photoresist 121, and to the source-drain area into
Row ion implanting.Since the source and drain injection region of peripheral components may need to carry out multiple various concentration, different types of ion note
Enter, therefore, the present embodiment is not particularly limited the number of the ion implanting of peripheral components.Optionally, complete be lightly doped from
After son injection, it is also necessary to remove the second photoresist 121.
Optionally, after each ion implanting further include: carry out the second annealing to the memory.Optionally,
Second annealing is also possible to rapid thermal annealing.Meanwhile second annealing can accelerate the first lightly-doped source drain structure 401
It is spread with the ion of the second lightly-doped source drain structure 402, keeps the distribution of Doped ions more uniform.
It should be noted that requiring to remove the photoresist on memory before each annealing；Annealing with
Afterwards, photoetching process is continued to execute if necessary, can carry out the smearing and patterned process of photoresist again.
Conventionally, as the first lightly-doped source drain structure 401 is formed at the first annealing and the second annealing
After reason, in order to spread the foreign ion in the first lightly-doped source drain structure 401 sufficiently, it is also necessary to form the first lightly-doped source
After drain structure 401, special thermal anneal process is carried out to memory again, therefore, the process flow of memory is cumbersome, cost of manufacture
It is higher.And primary annealing, the storage unit drain terminal impurity point of formation only are carried out to the first lightly-doped source drain structure 401
Cloth and concentration gradient are not ideal enough, so as to cause programing effect and the decline of storage unit electric leakage control.
However in the present embodiment, the first lightly-doped source drain structure 401 be formed in the second lightly-doped source drain structure 402 it
Before, the first annealing and second makes annealing treatment the diffusion that can accelerate foreign ion in the first lightly-doped source drain structure 401.
That is, in the case where not made annealing treatment to the lightly-doped source drain region of storage unit specially, the first annealing and
Second annealing can lightly-doped source drain region to storage unit carry out annealing at least twice.In fact, depositing
In reservoir preparation process, it usually needs to the source and drain injection region of peripheral components carry out that ion implanting repeatedly is lightly doped, gently mix every time
After heteroion injection, require to make annealing treatment memory.Compared with prior art, the present embodiment can to memory into
Row repeatedly after annealing, can be such that the Doped ions in the lightly-doped source drain region of storage unit sufficiently spread, have memory
Good programing effect and storage unit electric leakage control.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention
It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also
It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (8)
1. a kind of ion injection method of memory characterized by comprising
In the storage control gate of preparation peripheral polysilicon gate and storage unit that one side of substrate surface forms peripheral components, wherein
The peripheral polysilicon gate of preparation and the storage control gate limit the source and drain injection region of the storage unit；
Source and drain ion implanting is lightly doped using what self-registered technology carried out the storage unit；
The peripheral polysilicon gate of the preparation is performed etching, forms peripheral polysilicon in the setting control unit area of the peripheral components
Grid；
Carry out the peripheral components is lightly doped source and drain ion implanting.
2. the ion injection method of memory according to claim 1, which is characterized in that the peripheral polysilicon gate of preparation
Including the gate insulating layer and peripheral gates layer stacked gradually, the storage control gate include the tunnel oxide stacked gradually,
Floating gate layer, interlayer insulating film and control grid layer；
The gate insulating layer and the tunnel oxide are prepared in different process, the peripheral gates layer and the control gate
Layer is prepared in same technique.
3. the ion injection method of memory according to claim 2, which is characterized in that formed on one side of substrate surface outer
The peripheral polysilicon gate of the preparation of peripheral device and the storage control gate of storage unit include:
The peripheral polysilicon gate of preparation and the storage control gate are formed on one side of substrate surface using photoetching, etching technics.
4. the ion injection method of memory according to claim 3, which is characterized in that carry out institute using self-registered technology
The source and drain ion implanting that is lightly doped for stating storage unit includes:
Using the peripheral polysilicon gate of preparation and the control grid layer of the storage unit as exposure mask, to the substrate exposed into
Row ion implanting；Alternatively,
Using the remaining photoresist after using the first photoetching, etching technics to form the storage control gate as exposure mask, to what is exposed
The substrate carries out ion implanting.
5. the ion injection method of memory according to claim 2, which is characterized in that the peripheral polysilicon of the preparation
Grid perform etching, and form peripheral polysilicon gate in the setting control unit area of the peripheral components and include:
The peripheral gates of the peripheral components are formed in the setting control unit area using photoetching, etching technics.
6. the ion injection method of memory according to claim 5, which is characterized in that using photoetching, etching technics
After the setting control unit area forms the peripheral gates of the peripheral components further include:
First annealing is carried out to the memory.
7. the ion injection method of memory according to claim 6, which is characterized in that carry out the light of the peripheral components
Doped source and drain ion implanting includes:
Form the second photoresist, wherein storage unit described in second photoresist overlay, and second photoresist limits
The source and drain injection region of the peripheral components；
Using second photoresist as exposure mask, ion implanting at least once is carried out to the substrate exposed.
8. the ion injection method of memory according to claim 7, which is characterized in that after each ion implanting also
Include:
Second annealing is carried out to the memory.
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Application publication date: 20191029 |