CN116206958A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
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- CN116206958A CN116206958A CN202310167243.3A CN202310167243A CN116206958A CN 116206958 A CN116206958 A CN 116206958A CN 202310167243 A CN202310167243 A CN 202310167243A CN 116206958 A CN116206958 A CN 116206958A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/228—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a liquid phase, e.g. alloy diffusion processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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Abstract
The invention discloses a preparation method of a semiconductor device. The preparation method of the semiconductor device comprises the following steps: providing a substrate; forming a field oxide layer on the front surface of the substrate; carrying out pre-diffusion treatment and junction pushing on the back surface of the substrate by a first preset material; etching the back surface of the substrate to the direction of the inside of the substrate to form a plurality of holes and grooves which are arranged in an array manner; wherein the depth of the hole groove is smaller than the junction pushing depth; filling the holes and grooves with a second preset material to obtain a substrate structure with the holes and grooves on the back surface to replace the epitaxial wafer. The technical scheme of the embodiment of the invention reduces the process complexity and the preparation cost, and has lower requirements on the process precision.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device manufacturing method.
Background
At present, when an excessive voltage spike occurs to the collector of the bipolar device, a resistor with a certain resistance value is connected in series to solve the problem, but the frequency response of the bipolar device is slower, and the generated power consumption is larger.
In the prior art, the problems of slower response and larger power consumption of a bipolar device are solved by preparing an epitaxial layer with high resistivity on a substrate with low resistivity, so that parasitic capacitance of an N-type heavily doped region depletion layer of a source electrode and a drain electrode can be reduced on a MOS (metal oxide semiconductor) transistor or an IGBT (insulated gate bipolar transistor), immunity of the device to stray charge noise in the substrate is improved, and response speed is improved. However, the cost and the complexity of the process required by the method for preparing the epitaxial wafer by adopting the epitaxial process in the prior art are high, and the precision requirement on each flow in the process is also high.
Disclosure of Invention
The invention provides a preparation method of a semiconductor device, which is used for reducing the process complexity and the requirements on the process precision and reducing the preparation cost.
According to an aspect of the present invention, there is provided a semiconductor device manufacturing method including:
providing a substrate;
forming a field oxide layer on the front surface of the substrate;
carrying out pre-diffusion treatment and junction pushing on the back surface of the substrate by a first preset material;
etching a plurality of hole grooves which are arranged in an array manner in the direction of the back surface of the substrate facing the inside of the substrate; the depth of the hole groove is smaller than the junction pushing depth;
and filling all the hole grooves with a second preset material to obtain a substrate structure with the back filled with the hole grooves so as to replace the epitaxial wafer.
Optionally, the forming a field oxide layer on the front surface of the substrate includes:
preparing the field oxide layer on the front surface and the back surface of the substrate by utilizing an oxyhydrogen synthesis mode;
and removing the field oxide layer on the back surface of the substrate.
Optionally, the removing the field oxide layer on the back surface of the substrate includes:
coating a layer of photoresist on the surface of the field oxide layer on the front surface of the substrate to form a protective layer;
and completely etching the field oxide layer on the back surface of the substrate by adopting hydrofluoric acid.
Optionally, the thickness of the field oxide layer on the front surface of the substrate is 10000-13000 angstroms.
Optionally, the performing pre-diffusion treatment and junction pushing of the first preset material on the back surface of the substrate includes:
and carrying out pre-diffusion treatment and junction pushing of the first preset material by adopting a diffusion furnace with a silicon carbide furnace tube.
Optionally, when the diffusion furnace with the silicon carbide furnace tube is used for performing the pre-diffusion treatment and junction pushing of the first preset material, the method further comprises:
and forming a passivation layer on the back surface of the substrate.
Optionally, etching the substrate back surface in a direction facing the substrate interior to form a plurality of hole slots arranged in an array, including:
and etching the back surface of the substrate by using femtosecond laser at the passivation layer to sequentially obtain a plurality of hole grooves.
Optionally, the etching speed of the femtosecond laser is 3000-3500 mm/s, and the etching interval is 0.01-0.03 mm.
Optionally, etching the substrate back surface in a direction facing the substrate interior to form a plurality of hole slots arranged in an array, including:
coating photoresist on the surface of the passivation layer to form a photoresist layer;
exposing a part of the substrate area corresponding to the passivation layer by adopting exposure, development and dry etching modes on the photoresist layer;
and etching the exposed substrate areas by using a deep groove etching machine to obtain the hole grooves.
Optionally, the longitudinal section of the hole groove is in a right trapezoid shape, and the right trapezoid angle is 80-88 degrees;
the junction pushing depth is 180+/-5 mu m, the depth of each hole groove is 165+/-5 mu m, and the distance between every two adjacent hole grooves is 20-25 mu m.
Optionally, the filling each hole groove with the second preset material includes:
and evaporating the second preset material by adopting a low-pressure chemical vapor deposition method, and depositing the second preset material into the hole groove.
Optionally, the first preset material includes: phosphorus oxychloride; the second preset material comprises: phosphorus doped polysilicon.
Optionally, the obtaining the substrate structure with the back surface filled with the hole groove includes:
and removing the passivation layer on the back surface of the substrate by adopting a chemical mechanical polishing process to obtain the substrate structure.
The embodiment of the invention provides a technical scheme for filling corresponding materials to replace epitaxial wafers by forming deep grooves on the back surface. And forming a field oxide layer on the front surface of the substrate, and performing pre-diffusion treatment and junction pushing of a first preset material on the back surface of the substrate to form a heavily doped region with a certain carrier concentration gradient. Etching a plurality of hole grooves from the back surface of the substrate to the inside of the substrate, and filling the hole grooves with a second preset material to form a substrate structure with a certain carrier concentration gradient from the front surface of the substrate to the back surface of the substrate. Compared with the epitaxial wafer prepared by adopting an epitaxial process, the preparation method provided by the embodiment of the invention does not need to consider parameter setting of various influencing factors of epitaxial layer growth, has lower process complexity, has lower requirements on process precision relative to parameter control, and reduces preparation cost.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 2 is a schematic view of structures in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 3 is a schematic flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 4 is a schematic view of structures in a method for manufacturing a semiconductor device according to still another embodiment of the present invention;
fig. 5 is a schematic diagram showing a specific structure of step S140 in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 6 is a schematic flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 7 is a schematic view of structures in a method for manufacturing a semiconductor device according to still another embodiment of the present invention;
fig. 8 is a schematic view of structures in a method for manufacturing a semiconductor device according to still another embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The embodiment of the invention provides a preparation method of a semiconductor device. Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and fig. 2 is schematic structural diagrams of the method for manufacturing a semiconductor device according to an embodiment of the present invention. Referring to fig. 1 and 2, the method for manufacturing the semiconductor device specifically includes the following steps:
s110, providing a substrate 10.
And S120, forming a field oxide layer 20 on the front surface of the substrate 10.
Illustratively, a field oxide layer is prepared on the front side of the cleaned substrate, and is used for protecting and passivating the surface of the semiconductor substrate, and insulating the electrode leads of the device from the conductive substrate to prevent the device from leaking electricity. Illustratively, for a silicon substrate, the field oxide layer formed on the substrate surface is a silicon dioxide layer of a certain thickness.
S130, performing pre-diffusion treatment and junction pushing on the back surface of the substrate 10 by using a first preset material.
Illustratively, the back surface of the substrate is subjected to a pre-diffusion treatment of a first predetermined material, i.e., the first predetermined material is deposited on the back surface of the substrate for controlling the concentration of the first predetermined material on the surface of the substrate. After the pre-diffusion treatment, carrying out high-temperature junction pushing on the deposited first preset material on the back surface of the substrate to a certain depth to form a certain junction depth, thereby forming a heavily doped region with a certain carrier concentration gradient on the back surface of the substrate. Illustratively, fig. 2 shows a case where an N-type heavily doped region is formed, the first preset material is phosphorus oxychloride, and the substrate is a silicon wafer. Phosphorus oxychloride is used as a phosphorus source, and the back of the silicon wafer is subjected to phosphorus pre-diffusion treatment and junction pushing so that an N-type heavily doped region with a certain depth and a certain carrier concentration gradient is formed on the back of the silicon wafer.
S140, etching the back surface of the substrate 10 towards the inner direction of the substrate 10 to form a plurality of hole slots 30 which are arranged in an array manner; wherein the depth of the hole slot 30 is smaller than the push junction depth.
Illustratively, a plurality of holes are formed from the back surface of the substrate toward the inside of the substrate, and a material film layer with a certain carrier concentration gradient can be formed in the holes, so that the substrate forms a certain carrier concentration gradient from the front surface to the back surface. The etched hole groove is arranged in the heavily doped region of the substrate, so that a carrier concentration gradient is formed between the position of the hole groove and the front surface of the substrate. Therefore, kong Caoshen degrees should be less than the push junction depth of the phosphorus source. Illustratively, the trench depth and the push junction depth may be specifically set according to the actual requirements of device fabrication, and are not limited herein.
And S150, filling the hole grooves 30 with a second preset material to obtain a substrate structure with the back filled with the hole grooves, so as to replace the epitaxial wafer.
Illustratively, a second predetermined material is filled into each of the etched via holes to fill the via holes such that the substrate has a desired carrier concentration gradient from front to back. Through the operation of each step, a substrate structure with a plurality of holes and grooves formed in the back and filled with a second preset material is formed, and the substrate structure has a certain carrier concentration gradient, so that an epitaxial wafer can be prepared on the surface of the substrate instead of an epitaxial process, and the process difficulty and the preparation cost are reduced. The second preset material filled in each hole groove is phosphorus doped polysilicon.
The embodiment provides a technical scheme that deep grooves are formed in the back surface to fill corresponding materials to replace epitaxial wafers. And forming a field oxide layer on the front surface of the substrate, and performing pre-diffusion treatment and junction pushing of a first preset material on the back surface of the substrate to form a heavily doped region with a certain carrier concentration gradient. Etching a plurality of hole grooves from the back surface of the substrate to the inside of the substrate, and filling the hole grooves with a second preset material to form a substrate structure with a certain carrier concentration gradient from the front surface of the substrate to the back surface of the substrate. Compared with the epitaxial wafer prepared by adopting an epitaxial process, the preparation method provided by the embodiment does not need to consider parameter setting of various influencing factors of epitaxial layer growth, has lower process complexity, has lower requirements on process precision relative to parameter control, and reduces preparation cost.
Optionally, based on the above embodiment, step S130 in the semiconductor device manufacturing method specifically includes:
and carrying out pre-diffusion treatment and junction pushing of the first preset material by adopting a diffusion furnace with a silicon carbide furnace tube.
Specifically, when pre-diffusion treatment and junction pushing of corresponding materials are carried out on the back surface of the substrate, the substrate is placed in a diffusion furnace, a certain amount of gas is filled in the diffusion furnace tube, the substrate is in a specific gas atmosphere, and the pre-diffusion treatment is carried out under the high-temperature condition.
Illustratively, the diffusion furnace used in performing the pre-diffusion treatment and the junction pushing may be a diffusion furnace having a silicon carbide furnace tube. The silicon carbide furnace tube has high purity and less impurities, does not pollute the substrate in the pre-diffusion treatment and junction pushing processes, is not easy to deform and crack, and has good quality. If the diffusion furnace with the silicon carbide furnace tube is adopted, the atmosphere of the specific condition in the furnace tube is kept better, so that the junction pushing time of the substrate in the furnace tube can be shortened, and the situation that the substrate is in high-temperature atmosphere for a long time is avoided. If a diffusion furnace of furnace tubes of other materials is used, for example: and the quartz furnace tube and the like, because the quality of the furnace tube made of other materials is poorer than that of the silicon carbide furnace tube, the specific temperature and the gas atmosphere in the furnace tube are kept poorer, the substrate can be polluted, the pre-diffusion treatment and the junction pushing effect of the substrate are poorer, and the junction pushing time lasts longer. The substrate is in high temperature atmosphere for a long time to push the junction, so that defects are easily generated in the substrate, and the quality of the substrate is reduced. The semiconductor device is prepared by using the substrate with poor quality, and the parameters of the semiconductor device can be obviously influenced, so that the performance of the semiconductor device is reduced.
Optionally, fig. 3 is a schematic flow chart of another semiconductor device manufacturing method according to an embodiment of the present invention, and fig. 4 is schematic structural diagrams of another semiconductor device manufacturing method according to an embodiment of the present invention. On the basis of the above embodiments, the following embodiments describe a method for forming a field oxide layer on the front surface of a substrate in detail. Referring to fig. 3 and 4, the method for manufacturing the semiconductor device includes:
s210, providing a substrate 10.
S220, preparing a field oxide layer 20 on the front surface and the back surface of the substrate 10 by utilizing an oxyhydrogen synthesis mode.
Illustratively, the substrate is placed in a furnace tube that is filled with hydrogen and oxygen gas that grows a film of material. Preparing a field oxide layer on the surface of the cleaned substrate by adopting an oxyhydrogen synthesis mode in a hydrogen and oxygen atmosphere. In the process of preparing the field oxide layer, the front surface and the back surface of the substrate can be simultaneously grown with the field oxide layer with a certain thickness. Illustratively, the field oxide layer on the front side of the substrate has a thickness of 10000-13000 angstroms. Preferably, the thickness of the field oxide layer prepared on the front surface of the substrate can be 10000 angstrom, so that the effect of protecting the surface of the semiconductor substrate and preventing the electric leakage of the semiconductor device can be achieved, certain materials can be saved, and the preparation cost is reduced.
S230, removing the field oxide layer 20 on the back surface of the substrate 10.
Specifically, after the substrate with the field oxide layers on the front surface and the back surface is obtained, the field oxide layers on the back surface of the substrate are removed completely because the back surface of the substrate is not required to be protected by the field oxide layers and the subsequent operation is required to be carried out on the back surface of the substrate.
S240, performing pre-diffusion treatment and junction pushing on the back surface of the substrate 10 by using a first preset material.
S250, etching the back surface of the substrate 10 towards the inner direction of the substrate 10 to form a plurality of hole slots 30 which are arranged in an array manner; wherein the depth of the hole slot 30 is smaller than the push junction depth.
And S260, filling the hole grooves 30 with a second preset material to obtain a substrate structure with the back filled with the hole grooves, so as to replace the epitaxial wafer.
Optionally, on the basis of the foregoing embodiments, step S230 specifically includes:
s2301, a photoresist layer is coated on the surface of the field oxide layer 20 on the front surface of the substrate 10 to form a protection layer.
Specifically, a field oxide layer on the front surface of the substrate needs to be reserved to protect the front surface of the substrate and prevent electric leakage of devices, so that a layer of photoresist is coated on the surface of the field oxide layer on the front surface of the substrate to form a protective layer, so that the field oxide layer on the front surface of the substrate is protected from being polluted and damaged in the subsequent process flow.
S2302, the field oxide layer 20 on the back surface of the substrate 10 is completely etched by hydrofluoric acid.
Specifically, the back surface of the substrate is soaked in hydrofluoric acid with a certain concentration, and the field oxide layer on the back surface of the substrate is corroded, so that the field oxide layer formed on the back surface is completely removed. The front surface of the substrate is provided with a protective layer, so that the front surface field oxide layer can be reserved and cannot be corroded by hydrofluoric acid. After soaking for a period of time, the substrate is fished out. And washing the substrate for multiple times by adopting deionized water at normal temperature, cleaning hydrofluoric acid remained on the surface of the substrate, and spin-drying or blow-drying the deionized water remained on the surface of the substrate by using a nitrogen gun for later operation.
The technical scheme of the embodiment further limits the method for forming the field oxide layer on the front surface of the substrate, and the back surface field oxide layer is removed after preparing the field oxide layer on the front surface and the back surface of the substrate by utilizing an oxyhydrogen synthesis mode. Compared with a method for coating a photoresist layer on the back surface of a substrate and preparing a field oxide layer on the front surface of the substrate in an oxyhydrogen synthesis mode, the method provided by the embodiment can ensure that the preparation environment of the field oxide layer is higher in cleanliness and does not generate other pollutants. Therefore, the method of the embodiment can make the prepared field oxide layer have higher purity and cleaner surface.
Optionally, on the basis of the foregoing embodiments, with continued reference to the schematic structural diagram corresponding to step S240 in fig. 4, when performing the pre-diffusion treatment and junction pushing of the first preset material on the back surface of the substrate, the method further includes:
a passivation layer 40 is formed on the back side of the substrate 10.
Specifically, when the substrate is subjected to pre-diffusion treatment and junction pushing in a diffusion furnace, the substrate is in a certain gas atmosphere. Illustratively, in this embodiment, the silicon carbide furnace tube of the diffusion furnace is filled with hydrogen and oxygen prior to performing the pre-diffusion treatment and the junction pushing. And placing the substrate in an oxyhydrogen atmosphere, performing pre-diffusion treatment and junction pushing under the high-temperature condition, and simultaneously forming a passivation layer with a certain thickness on the back surface of the substrate. The substrate used in this embodiment is a silicon wafer, and the passivation layer formed on the back surface of the substrate is a silicon dioxide layer while performing the pre-diffusion treatment and junction pushing.
There are various methods for etching the back surface of the substrate to form a plurality of holes and grooves, and the methods can include laser etching and photoetching. The following embodiments will explain the above two etching methods, respectively.
The present embodiment specifically describes a method of forming a hole groove by laser etching. Optionally, with continued reference to fig. 4, etching a plurality of hole grooves arranged in an array on the back surface of the substrate toward the direction inside the substrate may specifically include:
the back surface of the substrate 10 is etched by a femtosecond laser at the passivation layer 40 to sequentially obtain a plurality of hole grooves 30.
Specifically, the present embodiment describes a method of forming a via hole by laser etching. Etching is performed by using a laser with high energy, for example: in this embodiment, a femtosecond laser is selected. Femtosecond laser is a technical means that human can obtain the shortest pulse under laboratory conditions, and huge power generated by the femtosecond laser in the moment is larger than the total power generated in the whole world. Because the peak power of the femtosecond laser is ultra-high, after focusing, the light intensity of the femtosecond laser far exceeds the coulomb field from internal interaction, so the femtosecond laser can easily break electrons away from the constraint of atoms to form plasma.
The principle of applying femtosecond laser etching is as follows: the surface of the material is irradiated by a high-energy femtosecond laser beam, so that the material of the irradiated part is vaporized, and the cutting or stripping of the material is realized. When the femtosecond laser is used for etching the back surface of the substrate through the passivation layer, the femtosecond laser can enable the etching edge to be smooth, and the substrate is prevented from being damaged.
Illustratively, the etching speed of the femtosecond laser is 3000-3500 mm/s, the etching interval is 0.01-0.03 mm, and the etching speed and the etching interval can be automatically adjusted by a user according to actual process requirements, so that the method is not limited. The etching distance is the distance between the laser emitted by two adjacent laser pulses and irradiated on the surface of the passivation layer, and the etching speed is the etching length of the laser in unit time. Preferably, the laser etching speed is 3000mm/s, and the laser etching interval is 0.015mm. If the laser etching interval is too small, the etching process has higher precision, but the etching efficiency is lower; if the laser etching interval is larger, the etching efficiency can be improved, the etching accuracy can be reduced, and the etching edge is rough. Therefore, the laser etching speed and the etching interval can be set to proper parameter values according to the requirements of the actual process.
For example, the power of the femtosecond laser at the time of performing laser etching may be set to 6.1 to 6.2W. Preferably, the power of the femtosecond laser is 6.18W, so that a better etching effect can be achieved. If the laser power is too small, the etching depth of the hole groove may be insufficient; if the laser power is too high, the laser etching area at the edge of the hole slot may be increased, resulting in lower etching accuracy.
According to the technical scheme, the method for etching the hole groove on the back surface of the substrate by using the femtosecond laser can obtain the hole groove with smooth edges, and the substrate is not damaged in the etching process.
The present embodiment specifically describes a method of forming a hole groove by photolithography etching. Optionally, fig. 5 is a schematic diagram of a specific structure of step S140 in a method for manufacturing a semiconductor device according to an embodiment of the present invention. On the basis of the above embodiments, referring to fig. 5, a plurality of hole slots arranged in an array are etched on the back surface of the substrate toward the inner direction of the substrate, which specifically includes:
and S141, coating photoresist on the surface of the passivation layer 40 to form a photoresist layer 41.
Specifically, a layer of photoresist is coated on the surface of a passivation layer formed on the back surface of the substrate, so that a mask layer is formed.
S142, exposing, developing and dry etching the photoresist layer 41 to expose a portion of the passivation layer 40 corresponding to the substrate 10.
Specifically, each etching region for etching the passivation layer is exposed by exposing and developing each specific region of the photoresist layer. And etching the passivation layer by using a dry etching method in the corresponding etching area to expose the substrate area under the passivation layer, so as to be used as a position mark for etching a hole slot on the back surface of the substrate.
And S143, etching the exposed areas of each substrate 10 by using a deep groove etching machine to obtain the hole grooves 30.
Specifically, a deep groove etching machine is used for sequentially etching at each position mark determined through a photoetching process, and a hole groove with a certain depth is obtained. And after etching is finished, removing the photoresist on the back surface of the substrate to obtain the substrate with a plurality of holes with a certain depth, wherein the holes are arranged in an array manner on the back surface of the substrate.
According to the technical scheme, the conventional photoetching method is adopted to carry out exposure etching on the passivation layer on the back surface of the substrate, the position of the etched hole slot is determined, and then the deep slot etching machine is used for etching, so that the precision of hole slot etching can be improved.
Optionally, on the basis of the above embodiments, with continued reference to the schematic structural diagram corresponding to step S140 in fig. 2, the longitudinal section of the hole slot 30 is in a regular trapezoid shape, and the angle of the regular trapezoid is 80-88 °; the junction pushing depth is 180+/-5 mu m, the depth of the hole grooves 30 is 165+/-5 mu m, and the distance between two adjacent hole grooves 30 is 20-25 mu m.
Illustratively, the hole slot is etched by a laser etching process or a photoetching process, the sizes of the hole bottom and the hole opening are not the same, and the longitudinal section of the hole slot is in a right trapezoid shape, namely the size of the hole bottom is larger than that of the hole opening. For example, the positive trapezoid angle of the longitudinal cross-sectional shape of the cell is 80 to 88 degrees, and it is convenient for the cell to be filled with a material in this angle range.
Illustratively, the depth of the hole trench may be 165+ -5 μm, and the junction depth formed when the back surface of the substrate is subjected to the pre-diffusion treatment and junction pushing is 180+ -5 μm. It can be seen that the depth of the hole trench needs to be smaller than the junction depth of the push junction to form a satisfactory carrier concentration gradient at the back side of the substrate. The depth of the hole and the junction depth formed by the push junction can be determined by a user according to the thickness of the substrate and the preparation requirement of an actual device, and the method is not limited herein.
Illustratively, among the plurality of hole grooves formed on the back surface of the substrate and arranged in an array, the pitch between adjacent two hole grooves is 20 to 25 μm, and the specific pitch is not limited herein. If the hole-slot spacing is too small, the silicon layer at the interval between the two holes-slots is too thin, so that the silicon layer is easy to break in the subsequent filling process. If the hole-slot spacing is too large, the number of holes-slots formed in a substrate with a certain area is reduced, which may result in that the prepared substrate structure cannot reach the carrier concentration gradient meeting the requirement.
The following examples illustrate methods of filling the cell with material. Alternatively, in an alternative embodiment, fig. 6 is a schematic flow chart of another semiconductor device manufacturing method according to an embodiment of the present invention, and fig. 7 is schematic structural diagrams of another semiconductor device manufacturing method according to an embodiment of the present invention. On the basis of the above embodiments, referring to fig. 6 and 7, the semiconductor device manufacturing method includes:
s710, providing a substrate 10.
S720, forming a field oxide layer 20 on the front surface of the substrate 10.
S730, performing pre-diffusion treatment and junction pushing of the first preset material on the back surface of the substrate 10.
S740, etching the back surface of the substrate 10 towards the inner direction of the substrate 10 to form a plurality of hole slots 30 which are arranged in an array; wherein the depth of the hole slot 30 is smaller than the push junction depth.
S750, evaporating the second preset material by adopting a low-pressure chemical vapor deposition method, and depositing the second preset material into the hole groove 30.
Illustratively, the second predetermined material is evaporated into a gas by low pressure chemical vapor deposition, and the gas is deposited into the inside of each hole groove to form a second predetermined material film layer so as to fill each hole groove. And obtaining the second preset material film layer with higher purity by using a low-pressure chemical vapor deposition method. Illustratively, the second predetermined material comprises: phosphorus doped polysilicon. The phosphorus doped polysilicon is filled in the hole groove on the back of the substrate, and a substrate structure with a certain carrier concentration gradient can be formed, so that the substrate with the carrier concentration gradient can be obtained by replacing an epitaxial process.
S760, removing the passivation layer on the back surface of the substrate by adopting a chemical mechanical polishing process to obtain the substrate structure.
In particular, the chemical mechanical polishing process (Chemical Mechanical Polishing, CMP) is a technique that achieves a material surface that is both planar and free of scratches and contamination by impurities. And polishing the back surface of the substrate by using a chemical mechanical polishing process to form a flat and smooth back surface of the substrate. And in the polishing process, the passivation layer on the back surface of the substrate is completely removed to expose the back surface of the substrate, and the surface of the second preset material filled in each hole groove is flush with the back surface of the substrate, so that the substrate structure capable of replacing the epitaxial wafer is obtained.
In another alternative embodiment, fig. 8 is a schematic structural diagram of another semiconductor device manufacturing method according to an embodiment of the present invention. On the basis of the above embodiments, the semiconductor device manufacturing method includes six steps S810 to S860. The steps other than step S850 are the same as those of steps S710 to S760.
Step S850 of the present embodiment is different from step S750 of the foregoing embodiment in that, in step S850, referring to fig. 8, the second preset material is evaporated by low pressure chemical vapor deposition and deposited inside the hole groove until the surface of the second preset material film is flush with the back surface of the substrate. Because the passivation layer on the back of the substrate needs to be completely removed in step S860, the second preset material part on the same layer as the passivation layer is also removed, so that the part on the same layer as the passivation layer can be omitted when the second preset material is deposited, thereby saving certain materials and reducing the cost.
In the embodiment, the second preset material is evaporated by adopting a low-pressure chemical vapor deposition method and deposited to each hole groove, and the hole grooves are filled up to obtain the second preset material film layer with higher purity. And removing the redundant passivation layer on the back of the substrate through a chemical mechanical polishing process to obtain a substrate structure with deep grooves on the back for filling with preset materials, wherein the substrate structure has a certain carrier concentration gradient from the front to the back of the substrate so as to replace an epitaxial wafer.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (13)
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a field oxide layer on the front surface of the substrate;
carrying out pre-diffusion treatment and junction pushing on the back surface of the substrate by a first preset material;
etching a plurality of hole grooves which are arranged in an array manner in the direction of the back surface of the substrate facing the inside of the substrate; the depth of the hole groove is smaller than the junction pushing depth;
and filling all the hole grooves with a second preset material to obtain a substrate structure with the back filled with the hole grooves so as to replace the epitaxial wafer.
2. The method of manufacturing a semiconductor device according to claim 1, wherein forming a field oxide layer on the front surface of the substrate comprises:
preparing the field oxide layer on the front surface and the back surface of the substrate by utilizing an oxyhydrogen synthesis mode;
and removing the field oxide layer on the back surface of the substrate.
3. The method of manufacturing a semiconductor device according to claim 2, wherein said removing the field oxide layer on the back surface of the substrate comprises:
coating a layer of photoresist on the surface of the field oxide layer on the front surface of the substrate to form a protective layer;
and completely etching the field oxide layer on the back surface of the substrate by adopting hydrofluoric acid.
4. The method of manufacturing a semiconductor device according to claim 1, wherein a thickness of the field oxide layer on the front surface of the substrate is 10000 to 13000 angstroms.
5. The method for manufacturing a semiconductor device according to claim 1, wherein the performing pre-diffusion treatment and junction pushing of the first preset material on the back surface of the substrate comprises:
and carrying out pre-diffusion treatment and junction pushing of the first preset material by adopting a diffusion furnace with a silicon carbide furnace tube.
6. The method according to claim 5, wherein when the preliminary diffusion treatment and junction pushing of the first predetermined material are performed by using the diffusion furnace having the silicon carbide furnace tube, further comprising:
and forming a passivation layer on the back surface of the substrate.
7. The method for manufacturing a semiconductor device according to claim 6, wherein etching the substrate back surface in a direction facing the substrate interior to form a plurality of hole grooves arranged in an array, comprises:
and etching the back surface of the substrate by using femtosecond laser at the passivation layer to sequentially obtain a plurality of hole grooves.
8. The method of manufacturing a semiconductor device according to claim 7, wherein the etching speed of the femtosecond laser is 3000 to 3500mm/s and the etching pitch is 0.01 to 0.03mm.
9. The method for manufacturing a semiconductor device according to claim 6, wherein etching the substrate back surface in a direction facing the substrate interior to form a plurality of hole grooves arranged in an array, comprises:
coating photoresist on the surface of the passivation layer to form a photoresist layer;
exposing a part of the substrate area corresponding to the passivation layer by adopting exposure, development and dry etching modes on the photoresist layer;
and etching the exposed substrate areas by using a deep groove etching machine to obtain the hole grooves.
10. The method for manufacturing a semiconductor device according to claim 7 or 9, wherein the longitudinal cross-sectional shape of the hole groove is a positive trapezoid, and the positive trapezoid angle is 80 to 88 °;
the junction pushing depth is 180+/-5 mu m, the depth of each hole groove is 165+/-5 mu m, and the distance between every two adjacent hole grooves is 20-25 mu m.
11. The method of manufacturing a semiconductor device according to claim 1, wherein filling each of the hole grooves with the second predetermined material comprises:
and evaporating the second preset material by adopting a low-pressure chemical vapor deposition method, and depositing the second preset material into the hole groove.
12. The method of manufacturing a semiconductor device according to claim 1, wherein the first predetermined material comprises: phosphorus oxychloride; the second preset material comprises: phosphorus doped polysilicon.
13. The method of manufacturing a semiconductor device according to claim 7 or 9, wherein the obtaining a substrate structure having a filled hole trench on a back surface comprises:
and removing the passivation layer on the back surface of the substrate by adopting a chemical mechanical polishing process to obtain the substrate structure.
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