CN105097505B - The method of the polysilicon emitter manufacture of transistor - Google Patents
The method of the polysilicon emitter manufacture of transistor Download PDFInfo
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Abstract
The present invention relates to the method that a kind of polysilicon emitter of transistor is manufactured.Including：Including N-type collecting zone, p-type base, the first oxide layer, the substrate surface progress photoetching of the second oxide layer, etching, forming emitter window, expose and emitter window width identical p-type base region；Deposited in the first oxide layer, the surface of the second oxide layer and emitter window undoped with polysilicon so that undoped with polysilicon emitter window region is completely covered；Deposit undoped with polysilicon after substrate surface carry out photoetching, etching, remove emitter window region exterior domain undoped with polysilicon；Using ion implantation technology in emitter window undoped with polysilicon inject doped chemical；First is carried out to the substrate after injection doped chemical to be heat-treated, so that the doped chemical in the polysilicon in emitter window is diffused among the top layer in the p-type base region exposed, forms N-type diffusion region.
Description
Technical field
The present invention relates to the polysilicon emitter manufacture in semiconductor device processing technology field, more particularly to a kind of transistor
Method.
Background technology
Bipolar transistor is made up of launch site, base, collecting zone., can be bipolar transistor according to its conduction type
Pipe is divided into NPN transistor and PNP transistor, and the wherein launch site of NPN transistor and collecting zone is N-type semiconductor, and base is p-type
Semiconductor, according to the type of its launch site, can be categorized as transistor monocrystalline emitter transistor and polysilicon emitter
Transistor, the former launch site is the monocrystalline silicon of n-type doping, and the launch site of the latter is the polysilicon of n-type doping, wherein polysilicon
Emitter transistor is mainly used in high frequency field, and its cross-sectional view is as shown in Figure 1.
Polysilicon emitter transistor shown in Fig. 1 includes N-type collecting zone 11, p-type base 12, and by N-type diffusion region
13 and the launch site that collectively forms of N-type polycrystalline silicon, wherein, N-type polycrystalline silicon is located at silica window（Referred to as " launch site window
Mouth 14 "）Among and its bottom directly contacted with the surface of p-type base 12.In practiced processes, N-type diffusion region 13 is many by N-type
Doped chemical in crystal silicon（Phosphorus, arsenic or antimony）Thermal expansion is dissipated to formation among the top layer of p-type base 12 under certain temperature environment
's.The region that thick oxide layer 15 shown in Fig. 1 is covered is place, and the region that thin oxide layer 16 is covered is active area.
Semiconductor fabrication process is the series of process step implemented on a semiconductor wafer, and semiconductor crystal wafer is disc
Semiconductor monocrystal, including silicon, germanium wafer etc..The method of the existing polysilicon emitter for making polysilicon emitter transistor
Including：
Including the surface progress light of N-type collecting zone 11, p-type base 12, thick oxide layer 15, the substrate of thin oxide layer 16
Carve, etching technics formation emitter window 14, expose the p-type base 12 in the region of emitter window 14, then deposit undoped with
Polysilicon, is then doped using ion implantation technology to polysilicon, is formed N-type polycrystalline silicon, is then heat-treated so that
The doped chemical in polysilicon in emitter window 14 is diffused among the top layer of p-type base 12, forms N-type diffusion region 13,
Then the polysilicon that photoetching, etching technics remove the exterior domain in the emitter window region is carried out, polysilicon emitter is formed
（Do not marked in Fig. 1）.To ensure that polysilicon emitter still can be complete in the case where a small amount of deviation of the alignment occurs in photoetching process
Cover the region of emitter window 14, the width of polysilicon emitter（Distance between left side wall 17 and right-side wall 18）Generally both greater than
The width of emitter window 14.
Because polysilicon is made up of numerous little crystal grains, deposit undoped with the technological temperature of polysilicon be generally 600-
650 degrees Celsius, than the temperature of above-mentioned heat treatment（Generally higher than 900 degrees Celsius）It is much lower, therefore in process of thermal treatment process
In, the crystal grain in polysilicon can become greatly, the surface of polycrystalline silicon membrane can recrystallize, these can all cause polysilicon to transmitting
Area's window 14 produces stress, causes semiconductor crystal wafer to deform upon, so that the alignment precision of above-mentioned polysilicon layer photoetching is not high,
In order to ensure that launch site window still can be completely covered in polysilicon emitter in the case where larger deviation of the alignment occurs in photoetching process
14 regions of mouth, it is necessary to which the width for designing polysilicon emitter is more much larger than the width of emitter window 14, and this results in chip face
Product becomes big, and cost increases.
The content of the invention
The method that the present invention provides a kind of polysilicon emitter manufacture of transistor, avoids what heat treatment was produced to realize
Stress causes the problem of polysilicon layer lithography alignment accuracy is not high, so as to reduce chip area, save process costs.
The method that the present invention provides a kind of polysilicon emitter manufacture of transistor, including：
Including N-type collecting zone, p-type base, the first oxide layer, the substrate surface progress photoetching of the second oxide layer, quarter
Erosion, forms emitter window, exposes and emitter window width identical p-type base region；
Deposited in the first oxide layer, the surface of the second oxide layer and emitter window undoped with polysilicon so that not
Emitter window region is completely covered in the polysilicon of doping；
Deposit undoped with polysilicon after substrate surface carry out photoetching, etching, remove outside emitter window region
Region undoped with polysilicon, reservation undoped with polysilicon width be more than or equal to emitter window width；
Using ion implantation technology in emitter window undoped with polysilicon inject doped chemical；
First is carried out to the substrate after injection doped chemical to be heat-treated, so that the doping in the polysilicon in emitter window
Among elements diffusion to the top layer in the p-type base region exposed, N-type diffusion region is formed.
The present invention transistor polysilicon emitter manufacture method, by include N-type collecting zone, p-type base,
First oxide layer, the substrate surface of the second oxide layer are carried out behind photoetching, etching, the p-type base for exposing emitter window region, are formed sediment
Product undoped with polysilicon so that undoped with polysilicon be completely covered emitter window region, then by deposit undoped with
Polysilicon after substrate surface carry out photoetching, etching, remove emitter window region exterior domain undoped with polysilicon,
Then into emitter window undoped with polysilicon inject doped chemical, and carry out first be heat-treated so that launch site window
The doped chemical in polysilicon in mouthful is diffused among the top layer in the p-type base region exposed, and is formed N-type diffusion region, is obtained
The polysilicon emitter of transistor.By above-mentioned after polycrystalline silicon deposit, photoetching, etching are first carried out, first is then just carried out
Heat treatment, the technology that efficiently avoid causes the alignment precision of polysilicon layer photoetching not high because of the stress that heat treatment is produced is asked
Topic, so as to realize reduction chip area, save process costs.
Brief description of the drawings
Fig. 1 is the cross-sectional view of polysilicon emitter transistor；
The flow chart of the embodiment one for the method that Fig. 2 manufactures for the polysilicon emitter of transistor of the present invention；
Fig. 3 for the embodiment of the present invention one emitter window formed after cross-sectional view；
Fig. 4 for the embodiment of the present invention one deposit undoped with polysilicon after cross-sectional view；
Fig. 5 be the photoetching of the embodiment of the present invention one, etching undoped with polysilicon after cross-sectional view；
Fig. 6 is the cross-sectional view after the injection doped chemical of the embodiment of the present invention one；
Fig. 7 is the cross-sectional view after the first heat treatment of the embodiment of the present invention one；
Fig. 8 is the cross-sectional view after execution step 104 after the step 102 of the embodiment of the present invention one；
The flow chart of the embodiment two for the method that Fig. 9 manufactures for the polysilicon emitter of transistor of the present invention.
Embodiment
The flow chart of the embodiment one for the method that Fig. 2 manufactures for the polysilicon emitter of transistor of the present invention, such as Fig. 2 institutes
Show, the method for the present embodiment includes：
Step 101, include N-type collecting zone 11, p-type base 12, the first oxide layer 15, the second oxide layer 16 substrate
Surface carry out photoetching, etching, formed emitter window 14, expose with the region of 14 width identical p-type base of emitter window 12,
Concrete structure formed referring to Fig. 3 emitter window after cross-sectional view.
Semiconductor fabrication process is the series of process step implemented on a semiconductor wafer, and semiconductor crystal wafer is disc
Semiconductor monocrystal, including silicon, germanium wafer etc..
N-type collecting zone 11 is produced on single crystal wafer first, then dioxy is made on the existing top layer of N-type collecting zone 11
SiClx oxide layer, obtains the first oxide layer 15, defines place；Again by doping process, not by the region of the first oxide layer 15
Produce p-type base 12 in the top layer of N-type collecting zone 11 of the active area of covering；Forming N-type collecting zone 11, p-type base 12 again
The second oxide layer 16 is grown with the top layer of the first oxide layer 15, wherein, the oxide layer 15 of the second oxide layer 16 to the first is thin, and first
5000 to 20000 angstroms of oxidated layer thickness scope, commonly referred to as thick oxide layer；Second 200 to 4000 angstroms of oxidated layer thickness scope, leads to
Frequently referred to thin oxide layer；It is preferred that：Second 1000 angstroms of oxidated layer thickness, the first 10000 angstroms of oxidated layer thickness.
Include N-type collecting zone 11, p-type base 12, the first oxide layer 15, the substrate of the second oxide layer 16 so as to be formed.
Then, include N-type collecting zone 11, p-type base 12, the first oxide layer 15, the second oxide layer 16 substrate table
Face carries out photoetching and etching technics, and wherein photoetching and etching technics includes：Crystal column surface cleaning, drying, linging, spin coating photoresist,
It is soft dry, alignment exposure, it is rear dry, development, it is hard dry, etching, the process such as detection, photoetching can be exposed using contact exposure, proximity
The method such as light or projection exposure；Etching can use dry etching or wet etching.Wafer table after photoetching and etching
Layer forms emitter window 14, and exposes the region of part p-type base 12 with the same width of emitter window 14.
Step 102, deposit and do not mix in first oxide layer 15, the surface of the second oxide layer 16 and the emitter window 14
Miscellaneous polysilicon 19 so that undoped with polysilicon 19 region of emitter window 14 is completely covered, concrete structure forms sediment referring to Fig. 4
Product undoped with polysilicon after cross-sectional view.
Step 103, the deposit undoped with polysilicon 19 after substrate surface carry out photoetching, etching, remove the transmitting
The exterior domain in the region of area's window 14 undoped with polysilicon 19, reservation undoped with polysilicon 19 width be more than or equal to hair
Penetrate the width of area's window 14, concrete structure referring to Fig. 5 photoetching, etching undoped with polysilicon after cross-sectional view.
Photoetching herein, etching technics are also referred to as polysilicon layer photoetching, etching, and this technique is to remove launch site window
The polysilicon in the region outside 14 regions of mouth, so as to form polysilicon emitter.It is a small amount of right to ensure to occur in a lithographic process
In the case of quasi- deviation, the region of emitter window 14, the width of polysilicon emitter still can be completely covered in polysilicon emitter
Degree（Distance between left side wall 17 and right-side wall 18）Generally it is both greater than the width of emitter window 14.It is photoetching work in the present embodiment
The deviation surplus that the alignment procedures of skill are reserved is：Retain undoped with polysilicon 19 width exceed the edge of emitter window 14
0.1 to 0.5 micron so that polysilicon layer photoetching, etching after emitter window 14 in still retain many of intact covering
Crystal silicon.
Step 104, using ion implantation technology in the emitter window undoped with polysilicon inject doped chemical
20, the cross-sectional view that concrete structure is injected after doped chemical referring to Fig. 6.
Polysilicon is doped using ion implantation technology, doped chemical 20 is phosphorus, arsenic or antimony, i.e., to step 103
The substrate of middle formation carries out ion implanting, and in the region covered with polysilicon, doped chemical 20 is injected among polysilicon,
The region not covered by polysilicon, doped chemical is injected among oxide layer, because oxide layer is simply made among transistor
For insulating barrier, the function that doped chemical 20 does not influence it as insulating barrier is filled with.
Step 105, to injection doped chemical 20 after substrate carry out first be heat-treated so that in the emitter window 14
Doped chemical 20 in polysilicon is diffused among the top layer in the region of p-type base 12 exposed, and forms N-type diffusion region 13, tool
Body structure is referring to the cross-sectional view after the heat treatments of Fig. 7 first.
First is carried out to the substrate after injection doped chemical 20 to be heat-treated so that doped chemical 20 is in sufficiently high temperature
Under, with electroactive, so as to diffuse among the top layer in the region of p-type base 12 exposed, form N-type diffusion region 13.In order to
Shorten heat treatment time, that is, accelerate the speed of heat treatment heating-cooling, so that less technique heat budget is obtained, the present embodiment
First heat treatment can use rapid thermal treatment（Rapid Thermal Process, referred to as：RTP）, the temperature of the first heat treatment
For 900 to 1150 degrees Celsius, the time is 10 to 200 seconds.Wherein, it is preferred that the temperature that can set the first heat treatment is 1000
Degree Celsius, the time is 30 seconds；Or temperature is 1020 degrees Celsius, the time is 20-40 seconds；Or temperature is 1050 degrees Celsius, when
Between be 20 seconds, to obtain optimal doped chemical diffusion effect.
It should be noted that the order of step 103 and step 104 can be exchanged, if the ion implantation technology of step 104
Before photoetching, etching technics in step 103, then in ion implanting, by the substrate surface that is formed after step 102
All covered by polysilicon, therefore doped chemical is to be injected among polysilicon, will not be injected among oxide layer, therefore,
The polysilicon emitter structure obtained after the displacement of above-mentioned two sequence of steps is the same.The note of step 104 is performed after step 102
Enter the cross-sectional view after doped chemical technique referring to Fig. 8；After step 104 after the photoetching of execution step 103, etching technics
Cross-sectional view it is identical with Fig. 6.
The present embodiment by include N-type collecting zone, p-type base, the first oxide layer, the second oxide layer substrate surface
Carry out photoetching, etching, behind the p-type base for exposing emitter window region, deposit undoped with polysilicon so that undoped with it is many
Crystal silicon is completely covered emitter window region, then by deposit undoped with polysilicon after substrate surface carry out photoetching, carve
Erosion, remove emitter window region exterior domain undoped with polysilicon, then into emitter window undoped with it is many
Crystal silicon injects doped chemical, and progress first is heat-treated, so that the doped chemical in the polysilicon in emitter window is diffused to
Among the top layer in the p-type base region exposed, N-type diffusion region is formed, the polysilicon emitter of transistor is obtained.By it is above-mentioned
After polycrystalline silicon deposit, photoetching, etching are first carried out, first is then just carried out and is heat-treated, effectively avoid because heat treatment is produced
Stress cause the not high technical problem of the alignment precision of polysilicon layer photoetching so that realize reduction chip area, save technique
Cost.
The flow chart of the embodiment two for the method that Fig. 9 manufactures for the polysilicon emitter of transistor of the present invention, such as Fig. 9 institutes
Show, the method for the present embodiment includes：
Step 201, include N-type collecting zone 11, p-type base 12, the first oxide layer 15, the second oxide layer 16 substrate
Surface carries out photoetching, etching, forms emitter window 14, exposes and the area of 14 width identical p-type base of the emitter window 12
Domain, concrete structure formed referring to Fig. 3 emitter window after cross-sectional view.
The step implements process referring to the step 101 in embodiment one, and here is omitted.
Step 202, second is carried out to exposing the substrate after the region of p-type base 12 be heat-treated, to repair the area of p-type base 12
The damage in domain.
Form the etching technics of emitter window 14 so that the top layer production in the p-type base 12 in the region of emitter window 14
Raw damage, when carrying out the first heat treatment, the doped chemical in polysilicon（Phosphorus, arsenic or antimony）Along the thermal diffusion speed of damage field
Degree is very fast, and the depth ratio of the N-type diffusion region 13 of formation is larger, causes the working frequency of transistor smaller, in order to ensure in practice
Transistor has sufficiently high working frequency, it is desirable to which it is shallow that the depth of the N-type diffusion region 13 among the top layer of p-type base 12 is tried one's best, institute
Formed with the present embodiment in photoetching, etching after emitter window 14, the is carried out to exposing the substrate after the region of p-type base 12
Two heat treatments so that be damaged in etching technics and chaotic lattice is recombinated, reach and repair because etching technics is in p-type base
The effect for the damage that the top layer of area 12 is formed, so as to avoid the doped chemical in existing method in polysilicon in the P that there is damage
Thermal diffusion is very fast among the top layer of type base, and the depth ratio of the N-type diffusion region of formation is larger, cause the working frequency of transistor compared with
Small the problem of.
Second heat treatment of the present embodiment can use rapid thermal treatment, the temperature of the second rapid thermal treatment for 950 to
1150 degrees Celsius, the time is 10 to 200 seconds.It is preferred that, the temperature that can set the second heat treatment is 1050 degrees Celsius, and the time is
60 seconds；Or temperature is 1100 degrees Celsius, the time is 30 seconds；Or temperature is 1150 degrees Celsius, the time is 50 seconds.To obtain most
The effect of good reparation damage.In addition, the second heat treatment can also be using boiler tube heat treatment, temperature is 800 to 1150 degrees Celsius,
Time is 10 to 300 minutes.It is preferred that, the temperature that can set the second heat treatment is 980 degrees Celsius, and the time is 30 minutes；Or
Person's temperature is 1050 degrees Celsius, and the time is 50 minutes；Or temperature is 1100 degrees Celsius, the time is 90 minutes, optimal to obtain
Reparation damage effect.
Step 203, deposit and do not mix in first oxide layer 15, the surface of the second oxide layer 16 and the emitter window 14
Miscellaneous polysilicon 19 so that undoped with polysilicon 19 region of emitter window 14 is completely covered, concrete structure is deposited referring to Fig. 4
Undoped with polysilicon after cross-sectional view.
Step 204, the deposit undoped with polysilicon 19 after substrate surface carry out photoetching, etching, remove launch site
The exterior domain in the region of window 14 undoped with polysilicon 19, reservation undoped with polysilicon 19 width be more than or equal to transmitting
The width of area's window 14, concrete structure referring to Fig. 5 photoetching, etching undoped with polysilicon after cross-sectional view.
The step implements process referring to the step 103 in embodiment one, and here is omitted.
Step 205, using ion implantation technology in the emitter window 14 undoped with polysilicon 19 inject and adulterate
Element 20, the cross-sectional view that concrete structure is injected after doped chemical referring to Fig. 6.
The step implements process referring to the step 104 in embodiment one, and here is omitted.
Step 206, to injection doped chemical 20 after substrate carry out first be heat-treated so that in the emitter window 14
Doped chemical 20 in polysilicon is diffused among the top layer in the region of p-type base 12 exposed, and forms N-type diffusion region 13, tool
Body structure is referring to the cross-sectional view after the heat treatments of Fig. 7 first.
The step implements process referring to the step 105 in embodiment one, and here is omitted.
It should be noted that the order of step 204 and step 205 can be exchanged, reason and the step 103 in embodiment one
The reasons why being replaced with step 104 is identical, will not be repeated here.
The present embodiment by include N-type collecting zone, p-type base, the first oxide layer, the second oxide layer substrate surface
Photoetching, etching are carried out, behind the p-type base for exposing emitter window region, the is carried out to exposing the substrate after p-type base region
Two heat treatments, so as to repair the damage in p-type base region, it is ensured that transistor has sufficiently high working frequency；Then by forming sediment
Product undoped with polysilicon so that undoped with polysilicon be completely covered emitter window region, then by deposit undoped with
Polysilicon after substrate surface carry out photoetching, etching, remove emitter window region exterior domain undoped with polysilicon,
Then into emitter window undoped with polysilicon inject doped chemical, and carry out first be heat-treated so that launch site window
The doped chemical in polysilicon in mouthful is diffused among the top layer in the p-type base region exposed, and is formed N-type diffusion region, is obtained
The polysilicon emitter of transistor.By above-mentioned after polycrystalline silicon deposit, photoetching, etching are first carried out, first is then just carried out
Heat treatment, the technology that efficiently avoid causes the alignment precision of polysilicon layer photoetching not high because of the stress that heat treatment is produced is asked
Topic, so as to realize reduction chip area, save process costs.
Further, also include after step 206：The 3rd is carried out to the substrate after formation N-type diffusion region to be heat-treated, to release
Put the stress in wafer.
During the first process of thermal treatment, the crystal grain in polysilicon can become greatly, the surface of polycrystalline silicon membrane can occur
Recrystallization, these can all cause polysilicon to produce stress to emitter window, because the first process of thermal treatment time is shorter, make
It is difficult uniformly to discharge in a short time to obtain stress, therefore causes semiconductor crystal wafer to deform upon, so that subsequent layers photoetching
Alignment precision is not high, in order to discharge the stress in wafer, and carrying out the 3rd to the substrate after formation N-type diffusion region is heat-treated, and
The temperature of 3rd heat treatment is far smaller than the temperature of the first heat treatment.The temperature of 3rd heat treatment is 350 to 700 degrees Celsius, when
Between be 30 to 300 minutes.It is preferred that, the temperature that can set the 3rd heat treatment is 475 degrees Celsius, and the time is 60 minutes；Or
Temperature is 550 degrees Celsius, and the time is 30-90 minutes；Or temperature is 650 degrees Celsius, the time is 30-90 minutes, to obtain most
The effect of good release stress.
Can slowly it be discharged due to the stress that the first heat treatment is produced, so as to improve polysilicon emitter by the 3rd heat treatment
The alignment precision of each photoetching after technique, reduces technology difficulty.
One of ordinary skill in the art will appreciate that：Realizing all or part of step of above-mentioned each method embodiment can lead to
The related hardware of programmed instruction is crossed to complete.Foregoing program can be stored in a computer read/write memory medium.The journey
Sequence upon execution, performs the step of including above-mentioned each method embodiment；And foregoing storage medium includes：ROM, RAM, magnetic disc or
Person's CD etc. is various can be with the medium of store program codes.
Finally it should be noted that：Various embodiments above is merely illustrative of the technical solution of the present invention, rather than its limitations；To the greatest extent
The present invention is described in detail with reference to foregoing embodiments for pipe, it will be understood by those within the art that：Its according to
The technical scheme described in foregoing embodiments can so be modified, or which part or all technical characteristic are entered
Row equivalent substitution；And these modifications or replacement, the essence of appropriate technical solution is departed from various embodiments of the present invention technology
The scope of scheme.
Claims (9)
1. a kind of method of the polysilicon emitter manufacture of transistor, it is characterised in that including：
Including N-type collecting zone, p-type base, the first oxide layer, the substrate surface progress photoetching of the second oxide layer, etching, shape
Into emitter window, expose and emitter window width identical p-type base region；
Deposited in first oxide layer, the surface of the second oxide layer and the emitter window undoped with polysilicon, with
Make it is described undoped with polysilicon the emitter window region is completely covered；
The deposit undoped with polysilicon after substrate surface carry out photoetching, etching, remove the emitter window region
Exterior domain undoped with polysilicon, reservation undoped with polysilicon width be more than or equal to emitter window width；
Using ion implantation technology in the emitter window undoped with polysilicon inject doped chemical；
First is carried out to the substrate after injection doped chemical to be heat-treated, so that the doping in the polysilicon in the emitter window
Among elements diffusion to the top layer in the p-type base region exposed, N-type diffusion region is formed；
It is described deposited in first oxide layer, the surface of the second oxide layer and the emitter window undoped with polysilicon
Before, in addition to：
Second is carried out to exposing the substrate after p-type base region to be heat-treated, to repair the damage in p-type base region.
2. according to the method described in claim 1, it is characterised in that second heat treatment is rapid thermal treatment, and temperature is 950
To 1150 degrees Celsius, the time is 10 to 200 seconds.
3. according to the method described in claim 1, it is characterised in that second heat treatment is boiler tube heat treatment, and temperature is 800
To 1150 degrees Celsius, the time is 10 to 300 minutes.
4. according to the method described in claim 1, it is characterised in that after the formation N-type diffusion region, in addition to：
The 3rd is carried out to the substrate after formation N-type diffusion region to be heat-treated, to discharge the stress in wafer.
5. method according to claim 4, it is characterised in that the temperature of the 3rd heat treatment is Celsius for 350 to 700
Degree, the time is 30 to 300 minutes.
6. method according to claim 4, it is characterised in that the temperature of the 3rd heat treatment is less than at the described first heat
The temperature of reason.
7. the method according to any one of claim 1-6, it is characterised in that first heat treatment is at fast speed heat
Reason.
8. method according to claim 7, it is characterised in that the temperature of first heat treatment is Celsius for 900 to 1150
Degree, the time is 10 to 200 seconds.
9. the method according to any one of claim 1-6, it is characterised in that the reservation undoped with polysilicon
Width exceeds 0.1 to 0.5 micron of emitter window edge.
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| CN102683401A (en) * | 2012-05-22 | 2012-09-19 | 清华大学 | Self-alignment lifting outer base region germanium silicon heterojunction bipolar transistor and preparation method thereof |
| CN103258732A (en) * | 2013-05-07 | 2013-08-21 | 上海华力微电子有限公司 | Method for preventing surfaces of silicon substrate from being damaged |
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