CN105093812A - Array substrate mother plate and manufacturing method therefor, and mask plate - Google Patents
Array substrate mother plate and manufacturing method therefor, and mask plate Download PDFInfo
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- CN105093812A CN105093812A CN201510491131.9A CN201510491131A CN105093812A CN 105093812 A CN105093812 A CN 105093812A CN 201510491131 A CN201510491131 A CN 201510491131A CN 105093812 A CN105093812 A CN 105093812A
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- exposure region
- base palte
- array base
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Abstract
The invention provides an array substrate mother plate and a manufacturing method therefor, and a mask plate. The mask plate is provided with at least one first exposure region; each first exposure region corresponds to one array substrate on the array substrate mother plate; the mask plate is further provided with a second exposure region; and the second exposure region is used for forming identification codes of the array substrates on the array substrate mother plate. The mask plate provided by the invention, by adding the second exposure region for manufacturing the identification codes on the mask plate, enables the identification code manufacturing process on the array substrate mother plate and the production process of the array substrates to be performed at the same time, so that the manufacturing time of the array substrate mother plate is greatly reduced and the production efficiency is improved.
Description
Technical field
The present invention relates to display field, particularly relate to a kind of array base palte motherboard and preparation method thereof, mask plate.
Background technology
TFT-LCD (Thin Film Transistor-LCD), as a kind of panel display apparatus, because it has the features such as little, low in energy consumption, the radiationless and cost of manufacture of volume is relatively low, and is applied in the middle of high-performance display field more and more.
TFT-LCD is primarily of array base palte, liquid crystal layer between color membrane substrates and two substrates is formed, wherein, array base palte is as the important component part of TFT-LCD, its performance quality directly can have influence on the display effect of TFT-LCD, at present, in the process of design TFT-LCD various product, the each array base palte on array substrate motherboard is needed to carry out stamp mark, Product Status is reviewed so that follow-up, the stamp technique of existing product line is carried out after the TFT graphic making on array base palte motherboard completes, particularly, first array base palte motherboard is needed to be transported on stamp equipment, then successively Laser Jet is carried out to each array base palte on it, but, when the array base palte quantity on array base palte motherboard is more, according to above-mentioned stamp technique, then will inevitably cause the increase of production time, thus reduction production efficiency.
Summary of the invention
(1) technical matters that will solve
The technical problem to be solved in the present invention is: how to solve in existing array base palte mastering process because stamp technique causes the problem that production efficiency is not high.
(2) technical scheme
For solving the problems of the technologies described above, technical scheme of the present invention provides a kind of mask plate, be provided with at least one first exposure region, first exposure region described in each corresponds to an array base palte on array base palte motherboard, described mask plate is also provided with the second exposure region, and described second exposure region for forming the identification code of described array base palte on described array base palte motherboard.
Preferably, described mask plate to be provided with in matrix multiple described first exposure region of arrangement, the first exposure region described in each is equipped with and self the second exposure region one to one.
Preferably, the second exposure region described in each is provided with multiple photic zone in point-like, and described multiple photic zone in point-like is matrix arrangement.
Preferably, the second exposure region described in each is arranged on the peripheral position of the first corresponding exposure region.
Preferably, described first exposure region is for the figure of the figure or source-drain electrode that make the grid of described array base palte.
For solving the problems of the technologies described above, present invention also offers a kind of method for making of array base palte motherboard, comprising:
Underlay substrate forms opaque film and photoresist layer successively;
Mask plate is adopted to expose described photoresist layer, described mask plate is provided with the first exposure region and the second exposure region, wherein, first exposure region described in each corresponds to an array base palte on array base palte motherboard, and described second exposure region for forming the identification code of described array base palte on described array base palte motherboard;
Carry out developing and etching technics, thus on described underlay substrate corresponding described first exposure region position on form a kind of structure graph in described array base palte, the position of corresponding described second exposure region of described underlay substrate is formed the identification code of described array base palte.
Preferably, described mask plate is provided with multiple described first exposure region of the arrangement in matrix, first exposure region described in each is equipped with and self the second exposure region one to one, each second exposure region is provided with the photic zone of multiple point-like, and the photic zone of described multiple point-like is all arranged in array, describedly exposure carried out to described photoresist layer comprises:
For the photoresist region that each the second exposure region is corresponding, the photoresist exposure corresponding to the photic zone of a part of quantity in described second exposure region, and photoresist corresponding to the photic zone of remainder in described second exposure region does not expose.
Preferably, exposure device is adopted to expose described photoresist layer, described exposure device comprises and exposes probe one to one with the second exposure region on described mask plate, each exposure probe comprises and photic zone pointolite one to one in the second corresponding exposure region, when described exposure probe is positioned at above the second exposure region of its correspondence, by controlling the wherein unlatching of each pointolite or closedown thus making the photic zone of a part of quantity in the second corresponding exposure region expose photoresist, and the photic zone of remainder does not expose photoresist.
Preferably, the second exposure region described in each is arranged on the peripheral position of the first corresponding exposure region.
Preferably, described structure graph is the figure of grid or the figure of source-drain electrode.
For solving the problems of the technologies described above, present invention also offers a kind of array base palte motherboard, adopting the method for making of above-mentioned array base palte motherboard to be formed.
(3) beneficial effect
Mask plate provided by the invention, by setting up the second exposure region for making identification code thereon, the technique that array base palte motherboard makes identification code can be carried out with the manufacture craft of array base palte simultaneously, thus the Production Time of array base palte motherboard can be greatly reduced, enhance productivity.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of a kind of mask plate that embodiment of the present invention provides;
Fig. 2 is the schematic diagram of second exposure region on the mask plate in Fig. 1;
Fig. 3 is a kind of schematic diagram making identification code that embodiment of the present invention provides;
Fig. 4 adopts the schematic diagram of mask board to explosure provided by the invention;
The schematic diagram of the array base palte motherboard that Fig. 5 adopts mask plate provided by the invention to obtain;
The enlarged diagram of an identification code on array base palte motherboard in Fig. 6 Fig. 5.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples for illustration of the present invention, but are not used for limiting the scope of the invention.
Embodiment of the present invention provides a kind of mask plate, be provided with at least one first exposure region, first exposure region described in each corresponds to an array base palte on array base palte motherboard, described mask plate is also provided with the second exposure region, and described second exposure region for forming the identification code of described array base palte on described array base palte motherboard.
The mask plate that embodiment of the present invention provides, by setting up the second exposure region for making identification code thereon, the technique that array base palte motherboard makes identification code can be carried out with the manufacture craft of array base palte simultaneously, thus the Production Time of array base palte motherboard can be greatly reduced, enhance productivity.
See Fig. 1, Fig. 1 is the schematic diagram of a kind of mask plate that embodiment of the present invention provides, this mask plate 100 is provided with multiple described first exposure region 110 of the arrangement in matrix, each first exposure region 110 is for the formation of a kind of structure graph of an array base palte on array base palte motherboard, and described in each, the peripheral position of the first exposure region 110 is also provided with and self the second exposure region 120 one to one;
Wherein, the first exposure region on mask plate may be used for making opaque structure graph in array base palte, such as, this structure graph can be the figure of grid or the figure of source-drain electrode that are formed by copper product, also can be other nontransparent rete figures, by setting up the second exposure region on mask plate, when adopting this mask plate to make array base palte motherboard, position corresponding with the first exposure region on underlay substrate can not only be formed the structure graph of each array base palte, the identification code of each array base palte can also be made on the position that the second exposure region is corresponding simultaneously,
Particularly, can by arranging photic zone in each second exposure region on mask plate, by this photic zone, the opaque film of underlay substrate corresponding position can be retained after the structure graph of above-mentioned array base palte completes simultaneously, thus form the pattern with photic zone same shape, therefore, can by arranging the photic zone of preset shape on mask plate in the second exposure region, thus the pattern that can form correspondingly-shaped is as identification code;
Preferably, in order to difform identification code can be formed, as shown in Figure 2, second exposure region 120 described in each is provided with light tight district 121 and multiple photic zone 122 in point-like, and described multiple photic zones 122 in point-like arrangement in matrix, in the process making identification code, for the described photoresist region that each second exposure region is corresponding, the photoresist exposure corresponding to the photic zone of a part of quantity in described second exposure region, and photoresist corresponding to the photic zone of remainder in described second exposure region does not expose, therefore, the photic zone of a part of quantity can be selected to expose, and the photic zone of remainder does not expose, by selecting the photic zone of exposure to form required shape, thus the identification code of correspondingly-shaped can be made, such as, the stamp of a character can be realized by second exposure region.
Embodiment of the present invention additionally provides a kind of method for making of array base palte motherboard, and the method comprises:
S1: form opaque film and photoresist layer successively on underlay substrate; Wherein, this opaque film is for the formation of structure graph opaque in array base palte, and such as, this structure graph can be the figure of grid or the figure of source-drain electrode that are formed by copper product;
S2: adopt mask plate to expose described photoresist layer, described mask plate is provided with the first exposure region and the second exposure region, wherein, first exposure region described in each corresponds to an array base palte on array base palte motherboard, and described second exposure region for forming the identification code of described array base palte on described array base palte motherboard;
S3: carry out developing and etching technics, thus on described underlay substrate corresponding described first exposure region position on form a kind of structure graph in described array base palte, the position of corresponding described second exposure region of described underlay substrate is formed the identification code of described array base palte.
Preferably, the method for making of array base palte motherboard of the present invention can adopt the mask plate in above-mentioned Fig. 1, namely mask plate is provided with multiple described first exposure region of the arrangement in matrix, the peripheral position of the first exposure region described in each is equipped with and self the second exposure region one to one, each second exposure region is provided with the photic zone of multiple point-like, and the photic zone of described multiple point-like is all arranged in array, wherein, describedly exposure carried out to described photoresist layer comprise:
For the photoresist region that each the second exposure region is corresponding, the photoresist exposure corresponding to the photic zone of a part of quantity in described second exposure region, and photoresist corresponding to the photic zone of remainder in described second exposure region does not expose.
Particularly, see Fig. 3, first on underlay substrate 200, opaque film 210 and photoresist layer 220 is formed successively, and adopt above-mentioned mask plate 100 and exposure device 300 pairs of photoresist layers 220 to expose, wherein, described exposure device 300 comprises and exposes probe 310 one to one with the second exposure region 120 on described mask plate 100, each exposure probe 310 comprises and photic zone pointolite one to one in the second corresponding exposure region, when described exposure probe is positioned at above the second exposure region of its correspondence, by controlling the wherein unlatching of each pointolite or closedown thus making the photic zone of a part of quantity in the second corresponding exposure region expose photoresist, and the photic zone of remainder does not expose photoresist,
Particularly, in above-mentioned exposure device 300, corresponding second exposure region of each probe, for the formation of the identification code of an array base palte on array base palte motherboard, the position of each probe can be arranged according to different design sizes and coordinate position, light source imports in this exposure device by optical fiber 320, by controlling the switch of each pointolite thus controlling the exposure of corresponding photic zone, arrive after directly over the second exposure region corresponding on mask plate at each probe, corresponding array point can be carried out according to program design directly over it to irradiate, thus Correct exposure is carried out to corresponding position, form corresponding exposing patterns,
Wherein, when adopting above-mentioned mask plate to expose above-mentioned photoresist layer 220, can expose the first exposure region on mask plate and the second exposure region simultaneously, such as, can be as shown in Figure 4, exposure scanister 400 is adopted to expose the first exposure region, exposure device 300 is adopted to expose the second exposure region, both can be synchronized with the movement, also can move respectively under different control, such as, exposure device 300 synchronously can move above at exposure scanister 400, can arrive directly over the second exposure region of mask plate prior to exposure scanister 400 like this, the switch of each pointolite is controlled according to program design, thus required exposing patterns can be formed, to obtain the identification code of correspondingly-shaped,
By the way, thus on photoresist layer 220, form corresponding exposure station to form different characters, and make exposure scanister 400 synchronous operation, to complete the exposure technology of the first exposure region, then carry out developing procedure, again opaque film 210 to be etched and by remaining photoresist lift off, thus a kind of structure graph 211 formed on the position of corresponding described first exposure region of underlay substrate 210 as shown in Figure 5 in array base palte, the position of corresponding second exposure region of underlay substrate is formed the identification code 212 of array base palte, particularly, see Fig. 6, Fig. 6 is the enlarged diagram of an identification code 212 in Fig. 5,
Adopt the mask plate in the present invention, just can be realized TFT graph exposure and the product identification code exposure of array base palte by single stepping, and then structure graph and the identification code of array base palte can be obtained simultaneously, compared to existing technology, the production time can be greatly reduced, improve production efficiency.
In addition, embodiment of the present invention additionally provides a kind of array base palte motherboard, and it adopts the method for making of above-mentioned array base palte motherboard to be formed.
Above embodiment is only for illustration of the present invention; and be not limitation of the present invention; the those of ordinary skill of relevant technical field; without departing from the spirit and scope of the present invention; can also make a variety of changes and modification; therefore all equivalent technical schemes also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (11)
1. a mask plate, be provided with at least one first exposure region, first exposure region described in each corresponds to an array base palte on array base palte motherboard, it is characterized in that, described mask plate is also provided with the second exposure region, and described second exposure region for forming the identification code of described array base palte on described array base palte motherboard.
2. mask plate according to claim 1, is characterized in that, described mask plate to be provided with in matrix multiple described first exposure region of arrangement, and the first exposure region described in each is equipped with and self the second exposure region one to one.
3. mask plate according to claim 2, is characterized in that, the second exposure region described in each is provided with multiple photic zone in point-like, and described multiple photic zone in point-like is matrix arrangement.
4. mask plate according to claim 2, is characterized in that, the second exposure region described in each is arranged on the peripheral position of the first corresponding exposure region.
5. according to the arbitrary described mask plate of Claims 1 to 4, it is characterized in that, described first exposure region is for the figure of the figure or source-drain electrode that make the grid of described array base palte.
6. a method for making for array base palte motherboard, is characterized in that, comprising:
Underlay substrate forms opaque film and photoresist layer successively;
Mask plate is adopted to expose described photoresist layer, described mask plate is provided with the first exposure region and the second exposure region, wherein, first exposure region described in each corresponds to an array base palte on array base palte motherboard, and described second exposure region for forming the identification code of described array base palte on described array base palte motherboard;
Carry out developing and etching technics, thus on described underlay substrate corresponding described first exposure region position on form a kind of structure graph in described array base palte, the position of corresponding described second exposure region of described underlay substrate is formed the identification code of described array base palte.
7. the method for making of array base palte motherboard according to claim 6, it is characterized in that, described mask plate is provided with multiple described first exposure region of the arrangement in matrix, first exposure region described in each is equipped with and self the second exposure region one to one, each second exposure region is provided with the photic zone of multiple point-like, and the photic zone of described multiple point-like is all arranged in array, describedly exposure carried out to described photoresist layer comprises:
For the photoresist region that each the second exposure region is corresponding, the photoresist exposure corresponding to the photic zone of a part of quantity in described second exposure region, and photoresist corresponding to the photic zone of remainder in described second exposure region does not expose.
8. the method for making of array base palte motherboard according to claim 7, it is characterized in that, exposure device is adopted to expose described photoresist layer, described exposure device comprises and exposes probe one to one with the second exposure region on described mask plate, each exposure probe comprises and photic zone pointolite one to one in the second corresponding exposure region, when described exposure probe is positioned at above the second exposure region of its correspondence, by controlling the wherein unlatching of each pointolite or closedown thus making the photic zone of a part of quantity in the second corresponding exposure region expose photoresist, and the photic zone of remainder does not expose photoresist.
9. the method for making of array base palte motherboard according to claim 7, is characterized in that, the second exposure region described in each is arranged on the peripheral position of the first corresponding exposure region.
10. the method for making of array base palte motherboard according to claim 7, is characterized in that, described structure graph is the figure of grid or the figure of source-drain electrode.
11. 1 kinds of array base palte motherboards, is characterized in that, adopt as arbitrary in claim 6 ~ 10 as described in array base palte motherboard method for making formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510491131.9A CN105093812A (en) | 2015-08-11 | 2015-08-11 | Array substrate mother plate and manufacturing method therefor, and mask plate |
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| CN201510491131.9A CN105093812A (en) | 2015-08-11 | 2015-08-11 | Array substrate mother plate and manufacturing method therefor, and mask plate |
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Cited By (8)
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| CN106019814A (en) * | 2016-05-30 | 2016-10-12 | 京东方科技集团股份有限公司 | Mask plate and preparation method for film layer |
| CN106707682A (en) * | 2017-01-05 | 2017-05-24 | 京东方科技集团股份有限公司 | Mask plate, exposure device and method for carrying out exposure by exposure device |
| CN106773520A (en) * | 2016-12-30 | 2017-05-31 | 武汉华星光电技术有限公司 | A kind of mask plate, controller and the method for entering Mobile state stamp using mask plate |
| CN107045258A (en) * | 2017-03-01 | 2017-08-15 | 深圳市科利德光电材料股份有限公司 | A kind of light shield and the method encoded using the light shield in product surface making date |
| CN109116593A (en) * | 2018-08-02 | 2019-01-01 | 深圳市华星光电半导体显示技术有限公司 | motherboard exposure method |
| CN109856843A (en) * | 2019-04-16 | 2019-06-07 | 京东方科技集团股份有限公司 | Display panel motherboard, display panel and its detection method |
| CN110842375A (en) * | 2019-11-15 | 2020-02-28 | Tcl华星光电技术有限公司 | Code printing device, manufacturing method and display device |
| WO2020124860A1 (en) * | 2018-12-21 | 2020-06-25 | 武汉华星光电技术有限公司 | Coding method, coding device and coding system |
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