CN105070661B - A kind of preparation method and structure of power unit structure - Google Patents
A kind of preparation method and structure of power unit structure Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 60
- 229920005591 polysilicon Polymers 0.000 claims abstract description 59
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 43
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 40
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 40
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 40
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 40
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 40
- 238000002347 injection Methods 0.000 claims abstract description 26
- 239000007924 injection Substances 0.000 claims abstract description 26
- 238000000137 annealing Methods 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 18
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 17
- 239000011574 phosphorus Substances 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 16
- 238000000206 photolithography Methods 0.000 claims abstract description 12
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 11
- 239000001301 oxygen Substances 0.000 claims abstract description 11
- 230000008021 deposition Effects 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- 230000004913 activation Effects 0.000 claims abstract description 7
- 239000010409 thin film Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 150000002500 ions Chemical group 0.000 claims 1
- -1 phosphonium ion Chemical class 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 13
- 230000002035 prolonged effect Effects 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 18
- 230000005684 electric field Effects 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 14
- 238000000034 method Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000005611 electricity Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
The embodiment of the invention discloses a kind of preparation methods of power unit structure to carry out high annealing, activation injection ion, highly doped n-type drift region is from device surface to buried oxide layer upper surface by carrying out phosphorus injection on thin film SOI disk；Silicon etching is carried out, until buried oxide layer, forms SiO2Dielectric layer window carries out SiO2Deposition carries out SiO2Etching carries out polysilicon deposition until buried oxide layer surface, forms polysilicon window；Phosphorus injection is carried out by the photolithography plate of specific customization, then carries out prolonged high annealing；It forms drain electrode, source electrode, grid and grid oxygen and polysilicon gate, polysilicon gate is connected with the grid in drift region；Deposit field oxygen SiO2And metal, and metal is performed etching, source, leakage, grid metal are formed, so as to effectively improve device electric breakdown strength, reduces device on-resistance.
Description
Technical field
The present embodiments relate to the technical field of semiconductor devices more particularly to a kind of preparation sides of power unit structure
Method and structure.
Background technique
Power integrated circuit is sometimes referred to as high voltage integrated circuit, is the important branch of modern electronics, can be various power
Transformation and energy processing unit provide high speed, high integration, the new-type circuit of low-power consumption and Flouride-resistani acid phesphatase, are widely used in electric power control
The current consumptions fields and national defence, space flight etc. such as system, automotive electronics, display device driving, communication and illumination processed are all more important
Field.Its application range expands rapidly, and to the high tension apparatus of its core, higher requirements are also raised.
For power device MOSFET, first, under the premise of guaranteeing breakdown voltage, it is necessary to reduction device as much as possible
Conducting resistance improve device performance.But institute is formed there are a kind of approximate quadratic relationship between breakdown voltage and conducting resistance
" the silicon limit " of meaning.Second, it is necessary to it is integrated convenient for high-low pressure, in smart-power IC, in addition to Power processing circuit, further include
Control circuit, logic circuit protect circuit, the low-voltage circuits such as interface circuit, therefore power device cannot influence low-voltage circuit
Operation, must have a good isolation between the two, SOI technology due to its Fully dielectric isolation, the advantage that speed is fast, low in energy consumption,
The most market share is occupied in the application of middle low power rapidly.When device pressure resistance is in middle a small range, indulge
Influence to pressure resistance is relatively small, and lateral pressure resistance determines the breakdown voltage of device.The electricity of traditional lateral LDMOS device structure
Peak value be generally focused on the source electrode and drain electrode both ends of device, the entire U-shaped distribution of drift region electric field, and surface field compared with
It is high.Traditional lateral RESURF SOI technology, such as field plate techniques, thin silicon membrane technology etc. improve drift to a certain extent
Electric field in the middle part of area, but device performance improves limited, and makes device surface electric field higher, increase in device use process can
By property problem.
Summary of the invention
The purpose of the embodiment of the present invention is to propose the preparation method and structure of a kind of power unit structure, it is intended to how to have
Electric field and the problem of improve internal electric field in the middle part of the raising drift region of effect.
For this purpose, the embodiment of the present invention uses following technical scheme:
A kind of preparation method of power unit structure, the preparation method include:
Phosphorus injection is carried out on thin film SOI disk, carries out high annealing, activation injection ion carries out silicon etching, until
Buried oxide layer forms SiO2Dielectric layer window carries out SiO2Deposition carries out SiO2Etching, until buried oxide layer surface, forms polycrystalline
Silicon window carries out polysilicon deposition；
Phosphorus injection is carried out by the photolithography plate of specific customization, then carries out prolonged high annealing；
It forms drain electrode, source electrode, grid and grid oxygen and polysilicon gate, polysilicon gate is connected with the grid in drift region；
Deposit field oxygen SiO2And metal, and metal is performed etching, form source, leakage, grid metal.
Preferably, the high annealing, activation injection ion annealing temperature be 800~900 DEG C, annealing time be 2~
5min forms highly doped n-type drift region.
Preferably, the SiO of the formation2The two edges of dielectric layer window apart from highly doped n-type drift region two edges 0.5~
1μm。
Preferably, polysilicon window two edges are apart from 0.5~1 μm of media slot two edges.
Preferably, the photolithography plate by specific customization carries out the annealing that phosphorus injection carries out prolonged high annealing again
Temperature is 900~1200 DEG C, and the time is 400~800min, so that the doping concentration of polysilicon is linearly increasing from source to leaking.
Preferably, the doping concentration inside the polysilicon gradually increases from one end close to source electrode to close to one end of drain electrode
Add, approximately linear distribution, and in SiO2Slot two sides form the n-layer of high-dopant concentration, and highly doped n-type drift region is from device
Surface to buried oxide layer upper surface.
A kind of power unit structure, the power unit structure include:
P type substrate, buried oxide layer, source electrode, grid, N-shaped deviate area, linear doping polysilicon layer, highly doped n-type floor, SiO2
And drain electrode；
For the P type substrate in the bottom of the power device, the buried oxide layer is described on the P type substrate, described
Doping concentration inside linear doping polysilicon is gradually increased from one end close to the source electrode to one end close to the drain electrode,
Linear distribution, and in SiO2The n-layer of slot two sides formation high-dopant concentration.
Preferably, the SiO of the formation2The two edges of dielectric layer window apart from highly doped n-type drift region two edges 0.5~
1μm；Polysilicon window two edges are apart from 0.5~1 μm of media slot two edges.
The embodiment of the present invention provides a kind of preparation method of power unit structure, by carrying out phosphorus on thin film SOI disk
Injection carries out high annealing, and activation injection ion carries out silicon etching, until buried oxide layer, forms SiO2Dielectric layer window, into
Row SiO2Deposition carries out SiO2Etching carries out polysilicon deposition until buried oxide layer surface, forms polysilicon window；Pass through spy
The photolithography plate very customized carries out phosphorus injection, then carries out prolonged high annealing；Formed drain electrode, source electrode, grid and grid oxygen and
Grid in polysilicon gate, polysilicon gate and drift region are connected；Deposit field oxygen SiO2And metal, and metal is performed etching, it is formed
Source, leakage, grid metal reduce device on-resistance so as to effectively improve device electric breakdown strength.
Detailed description of the invention
Fig. 1 is the flow diagram of the preparation method of power unit structure of the embodiment of the present invention；
Fig. 2 is a kind of structural schematic diagram of photolithography plate provided in an embodiment of the present invention；
Fig. 3 is a kind of schematic diagram of phosphorus injection provided in an embodiment of the present invention；
Fig. 4 is a kind of schematic diagram for forming highly doped n-type offset area provided in an embodiment of the present invention；
Fig. 5 is a kind of formation SiO provided in an embodiment of the present invention2The schematic diagram of dielectric layer window；
Fig. 6 is a kind of SiO provided in an embodiment of the present invention2The schematic diagram of deposition；
Fig. 7 is a kind of schematic diagram for forming polysilicon window provided in an embodiment of the present invention；
Fig. 8 is a kind of polysilicon deposition provided in an embodiment of the present invention and the schematic diagram for carrying out phosphorus injection；
Fig. 9 is a kind of schematic diagram for forming source electrode, drain electrode, grid provided in an embodiment of the present invention；
Figure 10 is a kind of schematic diagram for forming metal electrode provided in an embodiment of the present invention；
10 be drain electrode, and 11 be SiO2, 12 attach most importance to doped n-type layer, and 13 be linear doping polysilicon layer, and 14 deviate area for N-shaped,
15 be grid, and 16 be source electrode, and 17 be buried oxide layer, and 18 be P type substrate.
Specific embodiment
The embodiment of the present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this
Locate described specific embodiment and is used only for explaining the embodiment of the present invention, rather than the restriction to the embodiment of the present invention.In addition also
It should be noted that only parts related to embodiments of the present invention are shown rather than entire infrastructure for ease of description, in attached drawing.
Embodiment one
It is the flow diagram of the preparation method of power unit structure of the embodiment of the present invention with reference to Fig. 1, Fig. 1.
In example 1, the preparation method of the power unit structure includes:
Step 101, phosphorus injection is carried out on thin film SOI disk, carries out high annealing, and activation injection ion carries out silicon quarter
Erosion, until buried oxide layer, forms SiO2Dielectric layer window carries out SiO2Deposition carries out SiO2Etching, until buried oxide layer surface,
Polysilicon window is formed, polysilicon deposition is carried out；
Step 102, phosphorus injection is carried out by the photolithography plate of specific customization, then carries out prolonged high annealing；
Specifically, photolithography plate is refering to what is shown in Fig. 2, Fig. 2 is a kind of structural representation of photolithography plate provided in an embodiment of the present invention
Figure.
Step 103, drain electrode, source electrode, grid and grid oxygen and polysilicon gate, the grid phase in polysilicon gate and drift region are formed
Even；
Step 104, field oxygen SiO is deposited2And metal, and metal is performed etching, form source, leakage, grid metal.
Specifically, specific step is as follows for process flow:
(1) phosphorus injection is carried out on thin film SOI disk；(Fig. 3, Fig. 3 are a kind of phosphorus injections provided in an embodiment of the present invention
Schematic diagram)
(2) high annealing is carried out, activation injection ion forms highly doped n-type drift region, and annealing temperature is 800~900
DEG C, annealing time is 2~5min；(Fig. 4, Fig. 4 are that a kind of highly doped n-type that formed provided in an embodiment of the present invention deviates showing for area
It is intended to)
(3) silicon etching is carried out, until buried oxide layer, forms SiO2Dielectric layer window, window two edges are apart from highly doped n-type
0.5~1 μm of drift region two edges；(Fig. 5, Fig. 5 are a kind of formation SiO provided in an embodiment of the present invention2The signal of dielectric layer window
Figure)
(4) SiO is carried out2Deposition；(Fig. 6, Fig. 6 are a kind of SiO provided in an embodiment of the present invention2The schematic diagram of deposition)
(5) SiO is carried out2Etching, until buried oxide layer surface, forms polysilicon window, window two edges are apart from media slot
0.5~1 μm of two edges；(Fig. 7, Fig. 7 are a kind of schematic diagrames for forming polysilicon window provided in an embodiment of the present invention)
(6) polysilicon deposition is carried out；(schematic diagram that Fig. 8, Fig. 8 are a kind of polysilicon deposition provided in an embodiment of the present invention)
(7) phosphorus injection (photolithography plate is shown in figure (2)) is carried out by the photolithography plate of specific customization, then carries out prolonged high temperature
Annealing, make the doping concentration of polysilicon from source to leak it is linearly increasing, annealing temperature be 900~1200 DEG C, the time be 400~
800min；(schematic diagram that Fig. 9, Fig. 9 are a kind of phosphorus injection provided in an embodiment of the present invention)
(8) drain electrode, source electrode, grid and grid oxygen are formed and polysilicon gate, polysilicon gate is connected with the grid in drift region, had
Body technology is identical as traditional handicraft；(schematic diagram that Figure 10 is a kind of power unit structure provided in an embodiment of the present invention)
Specifically, traditional SOI LDMOS device structure middle low power should occasion under, it is most of all to pass through
It elongates drift region length or reduces drift doping concentration to meet the needs of breakdown voltage, and both modes can all cause
Device on-resistance increases, and limits further increasing for device performance, also becomes SOI power device and move towards large-scale application
Bottleneck.The invention proposes a kind of longitudinal direction RESURF structure of SOI power device, such as Figure 10, traditional lateral RESURF technologies
It is all located at device surface, and longitudinal direction RESURF technology is in inside device drift region, in the structure, is in SiO2Polycrystalline in slot
Prolonged high annealing is carried out again after the photolithography plate injection that silicon layer passes through specific customization, can make the doping inside polysilicon
Concentration is gradually increased from one end close to source electrode to close to one end of drain electrode, approximately linear distribution, while in SiO2Slot two sides
The n-layer of high-dopant concentration is formed, other structures are then identical as traditional SOI LDMOS structure.Since polysilicon doping concentration is close
Like linear distribution and depth directes reach buried oxide layer, therefore, forms longitudinal RESURF technology, the polysilicon layer of linear doping can be adjusted
Drift region electric field processed, so that drift region field distribution is more uniform, it can be in SiO after highly doped n-layer is completely depleted2It stays on surface
Lower a large amount of immovable positive charge improves the charge density on dielectric layer both sides in conjunction with the electronics that polysilicon layer introduces, according to
The electric field of Gauss theorem, dielectric layer can greatly increase, while also result in effectively increasing for drift region electric field, improve device
Breakdown voltage.In break-over of device, the polysilicon layer for connecting grid can attract electronics aggregation on dielectric layer both sides, form an electricity
Sub- accumulation layer flows through drift region for electric current and provides the current channel of a low-resistance, causes device on-resistance to greatly reduce, in addition
The presence of polysilicon layer also contributes to drift region and exhausts, so that under the conditions of same breakdown voltage, the doping concentration of device drift region
It is greatly improved, improves SOI power device performance.
In the present invention, longitudinal RESURF technology is introduced to traditional semiconductor power device LDMOS structure, improves and hits
Wear the tradeoff between voltage and conducting resistance.The doping concentration of polysilicon in deep trouth is gradually increased from source to leakage,
The distribution of drift region electric fields uniform can be modulated, secondly, a large amount of immovable positive charge is left after the fully- depleted of drift region, so that being situated between
The charge density of matter layer surface greatly increases, and effectively raises electric field in the middle part of drift region, different from traditional RESURF technology,
On the one hand the high electric field on surface can be introduced drift region bottom by longitudinal RESURF technology, avoid the occurrence of surface field concentration, separately
On the one hand the doping concentration of drift region bottom can be made to be greatly improved, improves the breakdown voltage of device.In break-over of device
When, the polysilicon layer for connecting grid can make close to SiO2There is charge accumulated in layer surface, formed the low impedance path of electric current with
And increased drift doping concentration can effectively reduce the conducting resistance of device, device performance be improved, especially in
The occasion of low-power applications.
Embodiment two
It is the schematic diagram of power unit structure of the embodiment of the present invention with reference to Figure 10, Figure 10.
In example 2, the power unit structure includes:
P type substrate, buried oxide layer, source electrode, grid, N-shaped deviate area, linear doping polysilicon layer, highly doped n-type floor, SiO2
And drain electrode；
For the P type substrate in the bottom of the power device, the buried oxide layer is described on the P type substrate, described
Doping concentration inside linear doping polysilicon is gradually increased from one end close to the source electrode to one end close to the drain electrode,
Linear distribution, and in SiO2The n-layer of slot two sides formation high-dopant concentration.
Invention describes a kind of high-performance semiconductor power unit structures and preparation method thereof of longitudinal direction RESURF technology.
The breakdown voltage of lateral power LDMOS structure is codetermined by laterally pressure-resistant and longitudinal pressure resistance, and in a certain range,
The laterally pressure-resistant and drift doping concentration directly proportional with drift region length of device is inversely proportional, and the conducting resistance of device is then just
It is good on the contrary, therefore, mutually restricted between the breakdown voltage and conducting resistance of lateral power, there are a contradictory relation,
In the present invention, longitudinal RESURF technology is introduced to traditional semiconductor power device LDMOS structure, improve breakdown voltage and is led
The tradeoff being powered between hindering.The doping concentration of polysilicon in deep trouth is gradually increased from source to leakage, can modulate drift
The distribution of area's electric fields uniform is moved, secondly, a large amount of immovable positive charge is left after the fully- depleted of drift region, so that dielectric layer surface
Charge density greatly increases, and electric field in the middle part of drift region is effectively raised, different from traditional RESURF technology, longitudinal RESURF
On the one hand the high electric field on surface can be introduced drift region bottom by technology, avoid the occurrence of surface field concentration, on the other hand can be with
So that the doping concentration of drift region bottom is greatly improved, the breakdown voltage of device is improved.In break-over of device, grid is connected
Polysilicon layer can make close to SiO2There is charge accumulated in layer surface, formed electric current low impedance path and increased drift
Area's doping concentration can effectively reduce the conducting resistance of device, device performance be improved, especially in middle low power application
Occasion.
Describe the technical principle of the embodiment of the present invention in conjunction with specific embodiments above.These descriptions are intended merely to explain this
The principle of inventive embodiments, and it cannot be construed to the limitation to protection scope of the embodiment of the present invention in any way.Based on herein
Explanation, those skilled in the art, which does not need to pay for creative labor, can associate the other specific of the embodiment of the present invention
Embodiment, these modes are fallen within the protection scope of the embodiment of the present invention.
Claims (7)
1. a kind of preparation method of power unit structure, which is characterized in that the preparation method includes:
Phosphorus injection is carried out on thin film SOI disk；
The first the high temperature anneal is carried out, activation injection ion forms highly doped n-type drift region, the highly doped n-type drift region
From device surface to buried oxide layer upper surface；
Silicon etching is carried out in highly doped n-type drift region, until buried oxide layer, forms SiO2Media slot, the highly doped n-type drift
The reservation part in area forms highly doped n-type floor；
Carry out SiO2Deposition, in SiO2SiO is formed in media slot2Dielectric layer；
Carry out SiO2Etching, until buried oxide layer surface, forms polysilicon slot；
Polysilicon deposition is carried out, forms polysilicon layer in polysilicon slot；
Phosphorus injection is carried out by default photolithography plate, then carries out the second the high temperature anneal, annealing time is 400 ~ 800min, is formed
Linear doping polysilicon layer, the doping concentration inside the linear doping polysilicon layer is from one end close to source electrode to close to drain electrode
One end gradually increase, it is linear to be distributed；
Form drain region, source region and grid oxygen and polysilicon gate, the line in polysilicon gate and highly doped n-type drift region
Property doped polysilicon layer be connected；
Deposit field oxygen SiO2And metal, and metal is performed etching, form source metal, drain metal and gate metal.
2. preparation method according to claim 1, which is characterized in that the annealing temperature of first the high temperature anneal is
800 ~ 900 DEG C, annealing time is 2 ~ 5min.
3. preparation method according to claim 1, which is characterized in that the SiO2Two opposite first edges of media slot point
Not apart from 0.5 ~ 1 μm of corresponding two edges in the highly doped n-type drift region；The first edge and the side from source electrode to drain electrode
To parallel.
4. preparation method according to claim 1, which is characterized in that the opposite two second edges difference of the polysilicon slot
Apart from the SiO20.5 ~ 1 μm of the corresponding two edges of media slot；The second edge is parallel with the direction from source electrode to drain electrode.
5. preparation method according to claim 1, which is characterized in that the annealing temperature of second the high temperature anneal is
900~1200℃。
6. a kind of power unit structure, which is characterized in that the power unit structure includes:
P type substrate, buried oxide layer, source electrode, grid, N-shaped drift region, linear doping polysilicon layer, highly doped n-type layer, SiO2Dielectric layer
And drain electrode；
The P type substrate is in the bottom of the power device, and the buried oxide layer is on the P type substrate, the N-shaped drift region
On the buried oxide layer；
The highly doped n-type layer to be formed by carrying out phosphonium ion injection and annealing in N-shaped drift region, and the highly doped n-type layer is from n
Type drift region surface to buried oxide layer upper surface；
The SiO2Dielectric layer is formed in the SiO in highly doped n-type layer2In media slot, the SiO2Media slot is from the heavy doping
N-layer surface to buried oxide layer upper surface；
The linear doping polysilicon layer is formed in the SiO2In polysilicon slot in dielectric layer, the polysilicon slot is from described
SiO2Dielectric layer surface is to buried oxide layer upper surface；
Doping concentration inside the linear doping polysilicon layer is from one end close to the source electrode to close to the one of the drain electrode
End gradually increases, linear distribution.
7. power unit structure according to claim 6, which is characterized in that the SiO2Two first opposite sides of media slot
Edge is respectively apart from 0.5 ~ 1 μm of corresponding two edges of the highly doped n-type layer；The first edge and the side from source electrode to drain electrode
To parallel；Two opposite second edges of the polysilicon slot are respectively apart from the SiO2Corresponding 0.5 ~ 1 μ of two edges of media slot
m；The second edge is parallel with the direction from source electrode to drain electrode.
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| CN1988176A (en) * | 2006-08-14 | 2007-06-27 | 东南大学 | High voltage N-shape metal oxide semiconductor tube and its preparing method |
| CN103021864A (en) * | 2012-12-11 | 2013-04-03 | 中国科学院上海微系统与信息技术研究所 | Silicon On Insulator (SOI) Reduced Surface Field (RESURF) superjunction device structure and production method thereof |
| CN103545372A (en) * | 2012-07-11 | 2014-01-29 | 台湾积体电路制造股份有限公司 | FinFET with trench field plate |
| CN205211709U (en) * | 2015-08-19 | 2016-05-04 | 工业和信息化部电子第五研究所华东分所 | Structure of power device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1988176A (en) * | 2006-08-14 | 2007-06-27 | 东南大学 | High voltage N-shape metal oxide semiconductor tube and its preparing method |
| CN103545372A (en) * | 2012-07-11 | 2014-01-29 | 台湾积体电路制造股份有限公司 | FinFET with trench field plate |
| CN103021864A (en) * | 2012-12-11 | 2013-04-03 | 中国科学院上海微系统与信息技术研究所 | Silicon On Insulator (SOI) Reduced Surface Field (RESURF) superjunction device structure and production method thereof |
| CN205211709U (en) * | 2015-08-19 | 2016-05-04 | 工业和信息化部电子第五研究所华东分所 | Structure of power device |
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