CN105047146B - Display device - Google Patents
Display device Download PDFInfo
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- CN105047146B CN105047146B CN201410811281.9A CN201410811281A CN105047146B CN 105047146 B CN105047146 B CN 105047146B CN 201410811281 A CN201410811281 A CN 201410811281A CN 105047146 B CN105047146 B CN 105047146B
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- sic
- source drive
- time schedule
- schedule controller
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G5/006—Details of the interface to the display terminal
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2370/00—Aspects of data communication
- G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2370/00—Aspects of data communication
- G09G2370/10—Use of a protocol of communication by packets in interfaces along the display data pipeline
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2370/00—Aspects of data communication
- G09G2370/14—Use of low voltage differential signaling [LVDS] for display data communication
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
A kind of display device, including：First and second data drivers, it is configured to check the availability of communications with time schedule controller when receiving supply voltage；Synchronization unit, it is configured to export DPM signals when the first and second data drivers can be used in being communicated with time schedule controller；And power module, the DPM signals of synchronization unit output are configured to, high-potential voltage is provided to the first and second data drivers.
Description
This application claims the priority for enjoying the korean patent application 10-2014-0051877 submitted on April 29th, 2014,
Wherein as reference, the application is introduced in a manner of to illustrate comprehensively herein, for use in any purpose.
Technical field
The present invention relates to it is a kind of can prevent because source drive IC breaks down and cause that source drive IC burns it is aobvious
Show equipment.
Background technology
Display device includes being used for multiple source electrode driven integrated circuits that data voltage is provided to the data wire of display panel
(hereinafter referred to as " IC "), for providing the multiple of grid impulse (or scanning impulse) to the gate line of display panel in order
Raster data model IC and the time schedule controller for controlling driving IC.
Time schedule controller is by the interface of such as miniature low-voltage differential signal (LVDS) interface etc, to source drive IC
Digital of digital video data, the clock for sampling digital of digital video data, the control letter of operation for controlling source drive IC are provided
Number etc..The digital of digital video data that time schedule controller inputs is converted into analog data voltage by source drive IC, and is provided
To data wire.
When connecting time schedule controller and source drive in a manner of multiple-limb (multi-drop) miniature LVDS interface
During IC, many bar circuits, including R data transmission line, G data transmission line, B are needed between time schedule controller and source drive IC
Data line, the control line in the time sequential routine for controlling source drive IC and dipole inversion, clock transfer line etc..As
Example, in RGB data transmission, RGB digital of digital video data and clock are by miniature LVDS interface with the side of Difference signal pair
Formula is transmitted.Therefore, when simultaneous transmission odd data and even data, needed between time schedule controller and source drive IC to
Lack 14 circuits to transmit RGB data.If the length of RGB data is 10 bits, 18 circuits are needed.Therefore, it is necessary to
It is installed on the source electrode printed circuit board (PCB) between time schedule controller and source drive IC and forms numerous circuits, this makes it difficult to subtract
The width of small source PCB.
The applicant proposes a kind of connection time schedule controller and source electrode in a point-to-point fashion in following patent application
IC is driven to minimize the number of, lines between time schedule controller and source drive IC and to make stable signal transmission
New signal host-host protocol (hereinafter referred to as " built-in panel interface (EPI) agreement ")：Korean patent application 10-2008-
0127458 (submission on December 15th, 2008), U.S. Patent application 12/543,996 (August was submitted on the 19th in 2009), South Korea is special
Profit application 10-2008-0127456 (submission on December 15th, 2008), (August 19 in 2009 of U.S. Patent application 12/461,652
Day submits), korean patent application 10-2008-0132466 (submission on December 23rd, 2008), and U.S. Patent application 12/
547,341 (August was submitted on the 7th in 2009).
EPI agreements meet following interface specification (1)-(3).
(1) transmitting terminal of time schedule controller in a point-to-point fashion, via each data wire to being connected to source drive IC's
Receiving terminal, without sharing these circuits.
(2) any individually clock line pair is not connected between time schedule controller and source drive IC.Time schedule controller passes through
By data wire pair, to source drive IC transmission each with the video data and control data of clock signal.
(3) the built-in clock recovery circuitry for being used for clock and data recovery (CDR) in each source drive IC.
Time schedule controller transmits clock training pattern signal or preamble signal to source drive IC, so as to locked clock restoring circuit
The phase and frequency of output.When via data wire to output clock training pattern signal and clock signal, in source drive IC
Built-in clock recovery circuitry produces internal clocking.
When having locked the phase and frequency of each internal clocking, source drive IC is fed back to for indicating stable export
The locking signal LOCK with high logic level, using the input as time schedule controller.The locking signal be by with sequential
The locking feedback signal line that controller and last source drive IC are connected, time schedule controller is fed back to as input
's.
In EPI agreements, as described above, before the control data of transmission input picture and video data, SECO
Clock training pattern signal is sent to source drive IC by device.Source drive IC clock recovery circuitry is schemed based on the clock training
Case signal, output internal clocking perform clock training operation so as to recovered clock.When stably having locked each internal clocking
Phase and frequency when, each source drive IC clock recovery circuitry and time schedule controller establish data link.With sequential
After controller establishes data link, source drive IC sends locking signal to next source drive IC.In response to from most
The locking signal that the latter source drive IC is received, time schedule controller start to transmit control data and video counts to source drive IC
According to.
In this process, locking signal may be sent to next because of source drive IC exceptions or failure
Source drive IC.In this case, locking signal will not reach time schedule controller, moreover, time schedule controller can not be to source
Pole driving IC provide data voltage.
Recently, the method for while to data wire both ends supplying data voltage has been used, to compensate to large area face
Plate provides the data voltage drop occurred during data voltage due to the distance between source drive IC and data wire.In other words,
First source drive IC is connected with one end of data wire, and the second source drive IC is connected with the other end of data wire.Thus,
First and second source drive IC provide data voltage to each data line.In EPI agreements, if the first and second source electrodes
Some in driving IC fail to establish data link with time schedule controller, then they will be unable to provide data electricity to data wire
Pressure.And on the other hand, the source drive IC of normal work can provide data voltage from the other end of data wire.Thus, data are worked as
Line from the source drive IC of the normal work being connected with one end receive data voltage when, in the source drive IC meetings that the other end is formed
Burnt by sink current (sink current).
The content of the invention
The illustrative embodiments of the present invention provide a kind of display device, including：First data driver and the second data are driven
Dynamic device, it is configured to check the availability of communications with time schedule controller when receiving supply voltage；Synchronization unit, it is configured in institute
State the first data driver and export DPM signals when the second data driver can be used in being communicated with time schedule controller；With
And power module, the DPM signals of the synchronization unit output are configured to, are counted to first data driver and second
High-potential voltage is provided according to driver.
Brief description of the drawings
Comprising accompanying drawing provide for the present invention further understanding, these accompanying drawings are introduced into and constitute this explanation
A part for book, it illustrates embodiments of the invention, and for illustrating principle of the invention together with specification.In accompanying drawing
In：
Fig. 1 is the view for showing the display device according to the present invention；
Fig. 2 is the view for the ce circuit for showing time schedule controller and source drive IC；
Fig. 3 is the view for showing the synchronization unit according to the present invention；
Fig. 4 is the oscillogram for showing the EPI agreements for the signal transmission between time schedule controller and source drive IC；
Fig. 5 is the view for the length for showing a packet according to EPI agreements；
Fig. 6 is shown in the oscillogram of the EPI signals transmitted in horizontal blanking period；
Source drive IC internal circuit configuration is shown in Fig. 7；And
Fig. 8 is to show the timing diagram for being used to drive the method for liquid crystal display according to the present invention.
Embodiment
Now will be referring in detail to embodiments of the invention exemplified in accompanying drawing.In the accompanying drawings will as much as possible all the time
Same or analogous part is quoted using identical reference numeral.It should be noted that if it is determined that known technology is possible to
Embodiments of the invention can be misled, then the detailed description on known technology will be omitted.
The display device of the present invention can be used as flat-panel monitor to implement, such as liquid crystal display (LCD), FED
Device (FED), Plasmia indicating panel (PDP), or organic light emitting diode display (OLED).It should be noted that rear
In continuous illustrative embodiments, although describing liquid crystal display as example, the display device of the present invention simultaneously not only limits
In the example.
With reference to figure 1, included according to the liquid crystal display of illustrative embodiments of the present invention：Liquid crystal display panel 10, sequential control
Device 20 processed, the first data driver 31 and the second data driver 32, and raster data model IC 40.
Liquid crystal display panel 10 includes the liquid crystal layer formed between the substrates.Liquid crystal display panel 10 includes passing through data wire
DL and gate lines G the L liquid crystal cells for intersecting and setting in the matrix form.
Pel array is formed on the tft array substrate of liquid crystal display panel 10, the pel array includes data wire DL, grid
Polar curve GL, TFT and storage.Liquid crystal cells be by the pixel electrode of data voltage is applied with via TFT, with applying
The electric field driven between the public electrode of common electric voltage is added.TFT gate electrode is connected with gate lines G L, TFT drain electrode electricity
Pole is connected with data wire DL.TFT source electrode is connected with the pixel electrode of liquid crystal cells.TFT is in response to via gate lines G L
The grid impulse of offer and turn on, so as to from pixel electrode from data wire DL to liquid crystal cells provide data voltage.In liquid crystal
Show and black matrix, colour filter, public electrode etc. are formed on the filter substrate of panel 10.In the TFT battle arrays of liquid crystal display panel 10
Adhere to polarizer on row substrate and filter substrate respectively, and form the pre-dumping for setting liquid crystal respectively on these substrates
The oriented layer at angle.It can be formed between the tft array substrate and color filter array substrate of liquid crystal display panel 10 for keeping
The wadding of liquid crystal cells Clc cell gap.
Liquid crystal display panel 10 can both be implemented with vertical electric field type of drive, for example, twisted-nematic (TN) pattern and hang down
Straight orientation (VA) pattern, can also be implemented with horizontal component of electric field type of drive, such as coplanar conversion (IPS) pattern and fringing field are cut
Change (FFS) pattern.The liquid crystal display of the present invention can be implemented using any form, show among these including transmission liquid crystal
Show device, semi permeable type liquid crystal display and reflective liquid-crystal display.Transmissive type liquid crystal display and semi-transmission-type liquid crystal
Show that device needs back light unit.Back light unit can be direct-type backlight unit or edge-type backlight unit.
Time schedule controller 20 is by such as low-voltage differential signal (LVDS) interface and minimizes differential signal transmission
(TMDS) interface such as interface, external timing signal, such as vertical/horizontal synchronizing signal are received from external host system (not shown)
Vsync/Hsync, data enable signal DE and master clock signal CLK.Time schedule controller 20 is via data wire pair, serial connection
To source drive IC SIC#1-SIC#8.Time schedule controller 20 is operated to meet foregoing EPI agreements, and input is schemed
The digital of digital video data of picture is sent to source drive IC SIC#1-SIC#8, and to source drive IC SIC#1-SIC#8 and grid
Driving IC40 time sequential routine is controlled.Time schedule controller 20 is by the clock training pattern signal of input picture, control signal
And digital of digital video data is converted into Difference signal pair, and the signal transmission standard according to defined in EPI agreements, by the difference
Sub-signal to via data wire to being serially transmitted to source drive IC SIC#1-SIC#8.
After the locking signal LOCK with high logic level is received from last source drive IC SIC#4, when
Sequence controller 20 serially transfers the control data and video counts for being each built-in with EPI clocks to source drive IC SIC#1-SIC#8
According to.The control data includes source electrode control data, and the source electrode control data is used to control from source drive IC SIC#1-
The output timing of data voltage and the polarity of the data voltage of SIC#8 outputs.The control data can include being used for
The grid control data in control gate driving IC 40 time sequential routine.
Time schedule controller 20 receives the first locking of the 4th source drive IC SIC#4 from the first data driver 31
Signal, and the first locking signal LOCK_UP is sent to synchronization unit 50.Come in addition, time schedule controller 20 also receives
From the 8th source drive IC SIC#8 of the second data driver 32 the second locking signal, and by second locking signal
LOCK_DN is sent to synchronization unit 50.Meanwhile time schedule controller 20 also transmits DPM signals to synchronization unit 50.
First data driver 31 and the second data driver 32 receive the video data from time schedule controller 20, and
The high potential reference voltage VDD and middle potential reference voltage HVDD supplied by using power module 60, by the video data
It is converted into analog data voltage.
Once receiving D/C power voltage VCC, the first data driver 31 and the second data driver 32 are checked for producing
Whether the CDR functions of raw internal clock signal are stablized.
In order to check the stability of CDR functions, the D/C power voltage VCC with high logic level is inputted into the first source first
Pole driving IC SIC#1 locking signal input, the first source drive IC SIC#1 are the of the first data driver 31
One source drive IC.Once receiving D/C power voltage VCC, the first source drive IC SIC#1 carry in response to time schedule controller 20
The clock training pattern signal of confession, produces the output of clock recovery circuitry.When the phase and frequency for having locked the output and
When thus stabilizing CDR functions, the first source drive IC SIC#1 have high logic to the second source drive IC SIC#2 transmission
The locking signal of level.Once receiving the locking signal from the first source drive IC SIC#1, then work as clock recovery signal
CDR function-stables when, the second source drive IC SIC#2 are in response to clock training pattern signal and to the 3rd source drive IC
SIC#3 transmits locking signal.By this way, as the first to the 4th source drive IC included in the first data driver 31
When SIC#1-SIC#4 CDR functions are all stable, the 4th source drive IC SIC#4 as last source drive IC just lead to
Locking feedback signal line is crossed, to first locking signal LOCK_UP of the transmission of time schedule controller 20 with high logic level.
The locking signal that D/C power voltage VCC with high logic level is input into the 5th source drive IC SIC#5 is defeated
Enter end, wherein the 5th source drive IC SIC#5 are the first source drive IC of the second data driver 32.Once receive
Believe to D/C power voltage VCC, the 5th source drive IC SIC#5 in response to the clock training pattern provided from time schedule controller 20
Number, produce clock recovery circuitry output.When the phase and frequency for having locked the output and when thus stabilizing CDR functions,
5th source drive IC SIC#5 have the locking signal of high logic level to the 6th source drive IC SIC#6 transmission.With this
Mode, when the 5th to the 8th source drive IC SIC#5-SIC#8 included in the second data driver 32 CDR functions are all steady
Regularly, the 8th source drive IC SIC#8 as last source drive IC will pass through locking feedback signal line, to sequential
Second locking signal LOCK_DN of the transmission of controller 20 with high logic level.
Can be by COG (chip on glass) techniques or TAB (tape-automated bonding) technique, by the He of the first data driver 31
The source drive IC SIC#1-SIC#8 included in second data driver 32 are connected to the data wire of liquid crystal display panel 10.Source
Pole drives IC SIC#1-SIC#8 via data wire to receiving the clock training pattern signal for being each built-in with EPI clocks, control
Data and video data.Source drive IC SIC#1-SIC#8 ce circuit provides EPI clocks to its clock recovery circuitry, with
Just (RGB bits x 2) internal clocking of video data is produced.By using phased lock loop (hereinafter referred to as
" PLL ") or delay locked loop (hereinafter referred to as " DLL "), the clock recovery circuitry output internal clocking and mask letter
Number, and produce locking signal LOCK.Source drive IC SIC#1-SIC#8 sample input figure according to its internal clocking sequential
The video data bit of picture, then by the RGB bits switch through over-sampling into parallel data.
Source drive IC SIC#1-SIC#8 are in a manner of code maps, to being carried out via data wire to the control data of input
Decoding, and recover source electrode control data and grid control data.In response to the source electrode control data after recovery, source drive IC
The video data of input picture is converted into positive/negative analog video data voltage by SIC#1-SIC#8, and provides it to liquid crystal
The data wire DL of display panel 10.Grid control data can be sent at least one grid by source drive IC SIC#1-SIC#8
Pole drives IC 40.
Fig. 2 is the view for the ce circuit for showing time schedule controller 20 and source drive IC SIC.Source electrode shown in Fig. 2 drives
Dynamic IC SIC are any one in source drive IC SIC#1-SIC#4, and its internal circuit is ce circuit.
With reference to figure 2, time schedule controller 20 is by LVDS interface or TMDS interfaces, from the number of host computer system reception input picture
Word video data RGB.Time schedule controller 20 is according to the external timing signal inputted from host computer system, by using internal sequential control
Signal generating circuit processed produces the control data including source electrode control data and grid control data.The basis of time schedule controller 20
Source drive IC and raster data model IC sequential, to by LVDS interface or TMDS interfaces and the clock that is inputted from host computer system and
Data RGB sequential is realigned.In addition, for EPI transmission for, time schedule controller 20 each data-signal it
Between onboard clock, and the clock is converted into Difference signal pair, and it is sent by sending buffer 24.The difference
Signal is to being to transmission via data wire.
Source drive IC SIC order caching device 25 receives the difference transmitted from time schedule controller 20 via data wire pair
Signal pair.Source drive IC SIC clock recovery circuitry 26 recovers internal clocking, and source according to the EPI clocks received
Pole driving IC SIC sample circuit 27 according to internal clocking and respectively sampling bits from control data and digital of digital video data.
Raster data model IC 40 by TAP techniques, can be connected to the gate line of the tft array substrate of liquid crystal panel, or
Person directly can also form raster data model by GIP (grid on plate) technique on the tft array substrate of liquid crystal display panel 10
IC 40.In response to the grid control for directly receiving from time schedule controller 20 or being received via source drive IC SIC#1-SIC#4
Data processed, raster data model IC 40 provide the grid arteries and veins with positive/negative analog video data voltage synchronous to gate lines G L in order
Punching.
Synchronization unit 50 receives the first locking signal LOCK_UP and the second locking signal LOCK_DN from time schedule controller 20
And DRM signals.All there is high logic level if all of input signal, then synchronization unit 50 by DPM signal outputs extremely
Power module 60.For this purpose, as shown in figure 3, synchronization unit 50 can be accorded with using logic and operation.
In response to DPM signals, power module 60 produces high potential reference voltage VDD and middle potential reference voltage HVDD, and
And the HDD and VHDD are supplied to source drive IC SIC#1-SIC#8.
Fig. 4 is to show the EPI agreements for the signal transmission between the time schedule controller shown in Fig. 2 and source drive IC
Oscillogram.
With reference to figure 4, time schedule controller 20 in the first stage (stage-I) to the first data driver 31 first to the 4th
Clock training pattern signal (or preamble signal) of the source drive IC SIC#1-SIC#4 transmission with constant frequency.It is once logical
Cross locking feedback signal line and receive the first locking signal LOCK_UP with high logic level, then time schedule controller 20 continues
To the second stage (stage-II) of signal transmission.Time schedule controller 20 is in the source electrode of second stage (stage-II) to first to the 4th
Drive IC SIC#1-SIC#4 transmission control datas.If the first locking signal LOCK_UP keeps being in high logic level, when
Sequence controller 20 proceeds to the phase III (stage-III) of signal transmission, defeated to be transmitted to source drive IC SIC#1-SIC#4
Enter the video data (RGB data) of image.Similarly, time schedule controller 20 in the first stage (stage-I) to the second data-driven
Clock training pattern signal of the 5th to the 8th source drive IC SIC#5-SIC#8 transmission with constant frequency of device 32.Once
Receive the second locking signal LOCK_DN with high logic level by locking feedback signal line, then time schedule controller 20 after
Continue the second stage (stage-II) of signal transmission.Time schedule controller 20 is in second stage (stage-II) to the 5th to the 8th source
Pole driving IC SIC#5-SIC#8 transmission control datas.If the second locking signal LOCK_DN keeps being in high logic level,
Time schedule controller 20 proceeds to the phase III (stage-III) of signal transmission, to be transmitted to source drive IC SIC#5-SIC#8
The video data (RGB data) of input picture.
In Fig. 4, " Tlock " is represented from starting the to first to the 4th source drive IC SIC#1-SIC#4 or the 5th to the
Eight source drive IC SIC#5-SIC#8 input clock training pattern signals, until having locked the first to the 4th source drive IC
The output of SIC#1-SIC#4 or the 5th to the 8th source drive IC SIC#5-SIC#8 clock recovery circuitry and by locking signal
It is inverted to the time spent by high logic level H.Time Tlock length is at least a horizontal cycle.One horizontal cycle
It is the time write data on a horizontal line of liquid crystal display panel 10 required for the liquid crystal cells arranged.
Fig. 5 is the view for the length for showing a packet according to EPI agreements.
With reference to figure 5, the data that the first to the 8th source drive IC SIC#1-SIC#8 are sent to according to EPI agreements are divided
Group includes multiple data bits and the Clocking bits distributed before and after data bit.The data bit is control number
According to or input picture digital of digital video data bit.The time that one bit needs to expend UI (unit gap) transmits,
This depends on the resolution ratio or number of data bits of liquid crystal display panel 10.
Clocking bits be assigned to data bit between one of two adjacent packets and another packet data bit it
Between 4 UI, its logical value can be " 0011 (or L L H H) ".If number of data bits is 10, then a packet can
With RGB data bit and 4 UI Clocking bits including 30 UI.If number of data bits is 8, then a packet
24 UI RGB data bit and 4 UI Clocking bits can be included.If number of data bits is 6, then one point
Group can include 18 UI RGB data bit and 4 UI Clocking bits.
In EPI agreements, as shown in fig. 6, first stage (stage-I) signal, second stage (stage-II) signal and
Phase III (stage-III) signal is that source drive IC SIC#1-SIC#8 are sent in each horizontal blanking period.
In Fig. 6, " DE " is the data enable signal that time schedule controller 20 is sent to from host computer system, and its pulse width is a horizontal week
Phase.
Source drive IC SIC#1-SIC#8 internal circuit configuration is shown in Fig. 7.
With reference to figure 7, each in the first to the 4th source drive IC SIC#1-SIC#4 carries to k data lines D1-Dk
For positive/negative data voltage (wherein k is positive integer).In 5th to the 8th source drive IC SIC#5-SIC#8 each from
First to the 4th source drive IC SIC#1-SIC#4 provide the direction in opposite direction of data voltage to k data lines D1-Dk
Data voltage is provided.
Each in first to the 8th source drive IC SIC#1-SIC#8 includes data sampler and deserializer
71, digital analog converter (hereinafter referred to as " DAC ") 72 and output circuit 73.
Data sampler and deserializer 71 carry out frequency multiplication to the EPI clocks CLK received from time schedule controller 20 or prolonged
Late, will pass through clock recovery circuitry to recover internal clocking, and according to the internal clocking, from via data wire to serial defeated
Sampling bits in the RGB digital of digital video data of the input picture entered.Then, data sampler and deserializer 71 latch sampling
Obtained data bit, then it is converted into parallel data by simultaneously exporting these bits.
Data sampler and deserializer 71 include the ce circuit shown in Fig. 3.Data sampler and deserializer 71
Recover the control data via data wire to reception in a manner of code maps, to produce source electrode control data.If described
Control data has encoded grid control data wherein, then data sampler and deserializer 71 are from via number
According to line to recovering the grid control data in the control data of input, and it is sent to raster data model IC 40.Source electrode control
Data processed can include source electrode output enable signal SOE, polarity control signal POL etc..Polarity control signal POL represents to provide
Polarity to data wire D1-Dk positive/negative analog data voltage.Source electrode exports enable signal SOE to source drive IC SIC#1-
SIC#8 data output sequential and electric charge is shared sequential and is controlled.If display device is not liquid crystal display, then can be with
Omit polarity control signal POL.Grid control data starts pulse, grid output enable signal etc. including grid.
The video data that data sampler and deserializer 72 input is converted into positive gamma compensated voltage by DAC 72
GMAH and negative gamma compensated voltage GMAL, to produce positive/negative analog video data voltage.Then, DAC 72 is in response to polarity control
Signal POL processed and reversal data voltage polarity.
Output circuit 73 exports enable signal SOE high logic simulation cycle in source electrode, shared by electric charge and slow via output
Storage, the average or common electric voltage Vcom of positive negative data voltage are provided to data wire D1-Dk.The time is shared in electric charge, from source electrode
The positive negative data voltage output channel to be sent to that driver SIC#1-SIC#8 is provided is short-circuited, so as to data wire D1-Dk
The average of positive negative data voltage is provided.
Fig. 8 is to show the timing diagram for being used to drive the method for liquid crystal display according to the present invention.
With reference to figure 8, according to the method for driving liquid crystal display according to the present invention, the first data driver 31 is examined
Availability of communications is looked into, and exports the first locking signal LOCK_UP.The step that first data driver 31 performs is to be based on
EPI agreements, to the available of the data transfer between the source drive IC SIC#1-SIC#4 of time schedule controller the 20 and first to the 4th
The processing that property is checked.
For this purpose, the first source drive IC produces the output of clock recovery circuitry in response to supply voltage VCC, and
When CDR function-stables, the first locking signal LOCK_UP is transmitted to the second source drive IC SIC#2.Come from once receiving
First source drive IC SIC#1 the first locking signal LOCK_UP, the second source drive IC SIC#2 produces clock recovery electricity
The output on road, and when CDR function-stables, the first locking signal LOCK_UP is transmitted to the 3rd source drive IC SIC#3.Class
As, when CDR function-stables, the 3rd source drive IC SIC#3 believe to the locking of the 4th source drive IC SIC#4 transmission first
Number LOCK_UP.When CDR function-stables, the 4th source drive IC SIC#4 transmit the first locking signal to time schedule controller 20
LOCK_UP (S801 and S803).
Similarly, the second data driver 32 checks availability of communications, and exports the second locking signal LOCK_DN.Change
Yan Zhi, once receiving supply voltage VCC, the 5th to the 8th source electrode driver SIC#5-SIC# of the second data driver 32 is pressed
The stability of its CDR function of sequential search.On the second data driver 32 operation more details and be directed to the first data
Content described by the operation of driver 31 is identical.When the 5th to the 8th source drive IC SIC#5-SIC#8 CDR work(
When can be stable, the 8th source drive IC SIC#8 to time schedule controller 20 transmit the second locking signal LOCK_DN (S805 and
S807)。
Time schedule controller 20 exports DPM signals, and the lockings of the first locking signal LOCK_UP and second to synchronization unit 50
Signal LOCK_DN.
Synchronization unit 50 receives the first locking signal LOCK_UP and the second locking signal LOCK_DN.It is if all above-mentioned defeated
Entering signal all has high logic level, then synchronization unit 50 exports DPM signals (S809) to power module 60.
In response to the DPM signals inputted from synchronization unit 50, power module 60 produces high potential reference voltage VDD and middle electricity
Position reference voltage HVDD.Then, high potential reference voltage VDD and middle potential reference voltage HVDD are supplied to source by power module 60
Pole driving IC SIC#1-SIC#8 (S811).
After high potential reference voltage VDD is received, the first to the 8th source drive IC SIC#1-SIC#8 produce gal
Horse reference voltage GMA.Then, the first to the 8th source drive IC SIC#1-SIC#8 are by gamma reference voltage GMA and middle current potential
Reference voltage HVDD is supplied to data wire DL.
From the above, it can be seen that only when both the first data driver 31 and the second data driver 32 export height
During logical locking signal, DPM signals can just be exported according to the synchronization unit 50 of the liquid crystal display of the present invention.That is,
When that can carry out data transmission between the first data driver 31 and the second data driver 32 and time schedule controller 20,
Synchronization unit 50 exports DPM signals according to EPI agreements.Correspondingly, if the first data driver 31 and the second data driver
Any one in 32 is not used to the communication based on EPI agreements, then synchronization unit 50 does not export DPM signals.Thus, power supply mould
Block 60 does not receive DPM signals, and does not produce high potential reference voltage VDD and middle potential reference voltage HVDD, therefore, first
The data driver 32 of data driver 31 and second does not receive high potential reference voltage VDD and middle potential reference voltage HVDD.
Correspondingly, the first data driver 31 and the second data driver 32 not to data wire DL provide high potential reference voltage VDD and
Middle potential reference voltage HVDD.
That is, if any one in the first data driver 31 and the second data driver 32 is not used to lead to
Letter, then according to the liquid crystal display of the present invention the first data driver 31 and the second data driver 32 will be prevented to provide
Data voltage and middle potential reference voltage HVDD.Even if electric current flow to data wire DL via a source drive IC, can also hinder
Only other source drives IC pours into electric current via data wire, thus prevents source drive IC from being burnt because of sink current.
In addition, in the liquid crystal display according to the present invention, supply voltage VCC is provided to source drive IC SIC#
1-SIC#8, and hereafter high potential reference voltage VDD can be supplied to by these IC by power module.Further, since source electrode
Driving IC SIC#1-SIC#8 can produce gamma electric voltage GMA using high potential reference voltage VDD, therefore can be correctly real
The current power supply process in operation source electrode driver SIC#1-SIC#8.
As described above, power module be arranged to become available in each data driver being connected with both ends and when
Sequence controller is just operated after being communicated.Therefore, also will not be due to even if operational error occurs for any data driver
Voltage is merely provided one end of data wire and causes other data drivers to be burned out.
Although embodiment here is to reference to numerous illustrative embodiments to describe, however, it is to be appreciated that ability
Field technique personnel can be designed that other modifications and the embodiment within numerous concepts for falling into the disclosure.Especially, exist
Within the scope of the disclosure, accompanying drawing and accessory claim, part and/or arrangement in the assembled arrangement of this theme are
Various changes and modifications can be carried out.In addition to change and modification in terms of part and/or arrangement, the purposes of replacement
Equally it is obvious to those skilled in the art.
Claims (2)
1. a kind of display device, including：
First data driver and the second data driver, it is configured to check when receiving supply voltage and time schedule controller
Availability of communications；
Synchronization unit, it is configured to can be used in entering with time schedule controller in first data driver and the second data driver
DPM signals are exported during row communication；And
Power module, the DPM signals that the power module exports in response to the synchronization unit, to first data driver
High-potential voltage is provided with the second data driver,
Wherein described first data driver with the time schedule controller when can enter row data communication to the sequential control
Device processed transmits the first locking signal, and second data driver can enter row data communication with the time schedule controller
When to the time schedule controller transmit the second locking signal,
Wherein described synchronization unit receives the DPM signals and first locking signal and second from the time schedule controller
Locking signal, and if first locking signal and the second locking signal all have high logic level, to the power supply mould
Block exports the DPM signals.
2. display device as claimed in claim 1, wherein first data driver and the second data driver simultaneously to
At least one data wire provides data voltage.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2014-0051877 | 2014-04-29 | ||
| KR1020140051877A KR102248139B1 (en) | 2014-04-29 | 2014-04-29 | Display Device |
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| CN105047146A CN105047146A (en) | 2015-11-11 |
| CN105047146B true CN105047146B (en) | 2018-01-26 |
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| US (1) | US9449577B2 (en) |
| KR (1) | KR102248139B1 (en) |
| CN (1) | CN105047146B (en) |
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| KR102304807B1 (en) * | 2014-08-18 | 2021-09-23 | 엘지디스플레이 주식회사 | Liquid crystal display device |
| US9865205B2 (en) * | 2015-01-19 | 2018-01-09 | Himax Technologies Limited | Method for transmitting data from timing controller to source driver and associated timing controller and display system |
| KR102321216B1 (en) * | 2015-05-29 | 2021-11-04 | 삼성디스플레이 주식회사 | Display Device |
| CN105161059B (en) * | 2015-06-30 | 2018-09-07 | 京东方科技集团股份有限公司 | Display drive method, display panel and preparation method thereof, display device |
| CN105185325A (en) * | 2015-08-12 | 2015-12-23 | 深圳市华星光电技术有限公司 | Liquid crystal display driving system and driving method |
| KR102458645B1 (en) * | 2015-12-28 | 2022-10-25 | 엘지디스플레이 주식회사 | Display device and driving method thereof |
| KR102563779B1 (en) * | 2016-06-30 | 2023-08-04 | 엘지디스플레이 주식회사 | Organic light emitting diode display device |
| KR102552006B1 (en) * | 2016-11-22 | 2023-07-05 | 주식회사 엘엑스세미콘 | Data driving device and display device including the same |
| KR102418971B1 (en) * | 2017-11-15 | 2022-07-11 | 삼성디스플레이 주식회사 | Display device and driving method thereof |
| TWI683293B (en) * | 2018-10-09 | 2020-01-21 | 友達光電股份有限公司 | Display device and link training method of display device |
| KR102526949B1 (en) * | 2018-11-14 | 2023-04-28 | 엘지디스플레이 주식회사 | Foldable display and Driving Method of the same |
| KR102728645B1 (en) * | 2019-08-29 | 2024-11-13 | 삼성디스플레이 주식회사 | Display device and driving method thereof |
| CN113035104A (en) | 2019-12-24 | 2021-06-25 | 硅工厂股份有限公司 | Display driving apparatus and display apparatus including the same |
| KR20210112074A (en) * | 2020-03-04 | 2021-09-14 | 주식회사 실리콘웍스 | Data driving device operating on low power mode, data processing device and display device including the same |
| CN111681584A (en) * | 2020-06-04 | 2020-09-18 | Tcl华星光电技术有限公司 | Display device and electronic apparatus |
| TWI751737B (en) * | 2020-10-15 | 2022-01-01 | 元太科技工業股份有限公司 | Display apparatus |
| CN114373415A (en) * | 2020-10-15 | 2022-04-19 | 元太科技工业股份有限公司 | Display device |
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| CN116168651A (en) * | 2021-11-25 | 2023-05-26 | 瑞昱半导体股份有限公司 | Backlight control device |
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| KR102248139B1 (en) | 2021-05-04 |
| KR20150125145A (en) | 2015-11-09 |
| US9449577B2 (en) | 2016-09-20 |
| US20150310824A1 (en) | 2015-10-29 |
| CN105047146A (en) | 2015-11-11 |
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