KR20090060080A - Liquid crystal display device and method for driving the same - Google Patents

Abstract

A liquid crystal display device and a method for driving the same are provided to minimize electromagnetic interference generated from transmit lines by restoring pixel data into data before modulation. A timing controller(12) receives pixel data from the outside and determines whether pixel data is modulated or not according to the logic state of bits comprising pixel data. The timing controller produces flag data indicating whether the pixel data is modulated or not and it outputs the flag data and the pixel data. A data driver(8) receives the pixel data and flag data from the timing controller through a plurality of differential signal transmission lines. The data driver determines whether the pixel data is restored or not according to a bit logic condition.

Description

Driving circuit of liquid crystal display and driving method thereof {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit of a liquid crystal display device and a driving method thereof, and more particularly to a driving circuit of a liquid crystal display device and a driving method thereof which can minimize electronic interference.

The liquid crystal display device includes a timing controller for aligning pixel data from the outside and outputting them in accordance with timing, and a data driver for converting the pixel data from the timing controller into an analog pixel voltage and supplying the same to the liquid crystal panel.

Transmission lines for supplying pixel data from the timing controller to the data driver are connected between the timing controller and the data driver, wherein the pixel data from the timing controller is converted from white data to black data (or black data to white data). In this case, a large amount of electromagnetic interference (EMI) is generated from the transmission lines.

The present invention has been made to solve the above problems, and provides a driving circuit of the liquid crystal display device and a driving method thereof which can minimize the electromagnetic interference by reducing the transition of the data using the flag data. There is a purpose.

In order to achieve the above object, the driving circuit of the liquid crystal display according to the present invention receives the pixel data from the outside and determines whether the pixel data is modulated according to a logic state of bits forming the pixel data. A timing controller which generates flag data indicating information on whether the pixel data is modulated and outputs the flag data and the pixel data; And a data driver receiving pixel data and flag data from the timing controller through a plurality of differential signal transmission lines and determining whether to restore the pixel data according to a logic state of a bit constituting the flag data. It features.

In addition, the driving circuit of the liquid crystal display according to the present invention for achieving the above object, by receiving the pixel data from the outside to determine whether or not to modulate the pixel data in accordance with the logical state of the bits forming the pixel data Generating flag data indicating information on whether the pixel data has been modulated; Step B for transmitting the pixel data and the flag data which have passed the step A through a plurality of data transmission lines; And a step C of determining whether to restore the pixel data according to a logic state of a bit constituting the flag data by receiving the pixel data and the flag data which have passed the step B.

The liquid crystal display device and the driving method thereof according to the present invention have the following effects.

According to the present invention, the pixel data is modulated according to a logic state of bits constituting the pixel data, and information indicating that the pixel data is modulated is indicated by using flag data, and then before the pixel data is modulated by using the flag data. By restoring the shape, electromagnetic interference generated from transmission lines through which the pixel data is transmitted can be minimized.

1 is a view showing a liquid crystal display device according to an embodiment of the present invention.

In the liquid crystal display according to the exemplary embodiment of the present invention, as shown in FIG. 1, gate lines GL and data lines DL intersecting with each other, and each of the gate lines GL and each data line. A display panel 2 including a thin film transistor TFT formed at an intersection portion between the DLs, a data driver 8 for inputting data into data lines DL of the display panel 2, and the display. A backlight unit 4 including a gate driver 10 for inputting scan pulses to the gate lines GL of the panel 2, a plurality of light sources for irradiating light to the display panel 2, and Timing for controlling the lamp driver 6 for driving the light sources of the backlight unit 4, the data driver 8, the gate driver 10, and the lamp driver 6 of the display panel 2. Supply power required for the controller 12 and the liquid crystal display panel and backlight unit 4. Which includes a power generation unit (14).

The thin film transistor TFT formed at the intersection of the data lines DL and the gate lines GL of the display panel 2 may receive data on the data lines DL in response to a scanning pulse from the gate driver 10. Is input to the liquid crystal cell. The source electrode of the thin film transistor TFT is connected to the data line DL, and the drain electrode is connected to the pixel electrode of the liquid crystal cell. The gate electrode of the thin film transistor TFT is connected to the gate line GL. The display panel 2 includes a color filter array substrate and a TFT array substrate bonded to each other with a liquid crystal layer interposed therebetween. The color filter and the common electrode are formed on the color filter array substrate. In the color filter, red, green, and blue color filter layers are disposed to transmit light of a specific wavelength band, thereby enabling color display. A black matrix is formed between color filters of adjacent colors.

Each liquid crystal cell includes a liquid crystal capacitor Clc for holding data for one frame period and a storage capacitor for stably maintaining the data for one frame period.

The timing controller 12 rearranges the pixel data input from the digital video card for each of the red pixel data R, the green pixel data G, and the blue pixel data B. FIG. The pixel data R, G, and B rearranged by the timing controller 12 are input to the data driver 8.

In addition, the timing controller 12 generates the data control signal DCS and the gate control signal GCS by using the horizontal synchronization signal H, the vertical synchronization signal V, and the clock signal CLK. The data driver 8 is supplied to the data driver 8 and the gate driver 10. The data control signal DCS includes a dot clock, a source shift clock, a source enable signal, a polarity inversion signal, and the like. The gate control signal GCS is input to the gate driver 10 including a gate start pulse, a gate shift clock, a gate output enable, and the like.

After the data driver 8 samples the pixel data according to the data control signal DCS from the timing controller 12, the data driver 8 divides the sampled data into one line for each horizontal period (1H, 2H, ...). Latch and supply the latched data to the data lines DL. That is, the data driver 8 converts the pixel data R, G, and B from the timing controller 12 into an analog pixel signal using the gamma voltages GMA1 to 6 input from the power generator 14. To supply to the data lines DL.

The gate driver 10 includes a shift register that sequentially generates scan pulses in response to a gate start pulse among the gate control signals GCS from the timing controller 12, and a voltage level suitable for driving the voltage of the scan pulses to drive the liquid crystal cell. And a level shifter for shifting to. The gate driver 10 sequentially supplies a gate high voltage to the gate lines GL in response to the gate control signal GCS.

The power generator 14 supplies the common electrode voltage Vcom to the display panel 2 and the gamma voltages GMA1 to 6 to the data driver 8.

FIG. 2 is a diagram illustrating a connection relationship between the timing controller and the data driver of FIG. 2.

As shown in FIG. 2, the timing controller 12 and the data driver 8 are connected to each other by a plurality of differential signal transmission lines LVL and a clock transmission line CL.

The timing controller 12 is formed on a control printed circuit board (PCB), and driver ICs of the data driver 8 are formed on a source PCB. The control PCB and the source PCB are connected to each other by a cable. The differential signal transmission lines LVL and the clock transmission lines CL are formed in the data cable.

The cable may be a flexible flat cable (FFC) or a flexible printed circuit (FPC).

Pixel data from the timing controller 12 and flag data to be described later are supplied to the respective driver ICs D-IC of the data driver 8 through the differential signal transmission lines LVL. The clock signal from (12) is supplied to each driver IC (D-IC) via the clock transmission line CL.

The timing controller 12 receives pixel data from the system. In addition, it is determined whether the pixel data is modulated according to a logic state of bits of the pixel data, and flag data indicating information on whether the pixel data is modulated is generated. The pixel data and the flag data are output together.

Pixel data and flag data from the timing controller 12 are supplied to the driver ICs D-IC in the data driver 8 through the differential signal transmission lines LVL.

Each driver IC D-IC receives the pixel data and the flag data from the timing controller 12 through the differential signal transmission lines LVL. Then, it is determined whether to restore the pixel data according to the logic state of the bits constituting the flag data.

3 is a detailed configuration diagram of the timing controller 12 and the driver IC (D-IC) of FIG. 2.

As shown in FIG. 3, the timing controller 12 includes a data modulator 33 and an LVDS transmitter 34, and the driver IC (D-IC) includes an LVDS receiver 44 and a data recovery unit 45. ).

The data modulator 33 receives the pixel data R / G / B and the flag data F in the form of a TTL (Transistor Transistor Logic) signal from the outside. When the logic states of all the bits R0 to B9 of the pixel data R / G / B are the same, the logic states of the bits of the pixel data R / G / B are all inverted. The logic state of any one of the bits F0 and F1 constituting the flag data F is inverted.

In detail, the data modulator 33 may select the pixel data R / G / B when all of the bits R0 to B9 of the pixel data R / G / B have a first logic value. All of the bits R0 to B9 are inverted to have the second logic value, and the specific bit F0 is inverted to have the first logic value. On the other hand, the data modulator 33 has the pixel data R / G / B when any one of all the bits R0 to B9 of the pixel data R / G / B has a second logic value. It does not invert the logic of all the bits R0 to B9 and the specific bit F0. In other words, the data modulator 33 has all of the bits R0 to B9 constituting the pixel data R / G / B having a second logic value, or the bits of the bits R0 to B9. If the logic values are different from each other, the logic values of all bits R0 to B9 and the specific bits constituting the pixel data are maintained without being inverted.

The LVDS transmitter 34 receives pixel data R / G / B and flag data F from the data modulator 33 through first to fourth data transmission lines TL1 to TL4. The pixel data R / G / B and the flag data F are converted into a low voltage differential signal (LVDS) signal.

The LVDS transmitter 34 includes first to fourth transmitters Tx1 to Tx4. The first to fourth transmitters Tx1 to Tx4 convert pixel data (R / G / B) and flag data (F) in the form of a TTL signal supplied thereto into LVDS signal forms, and convert the first to fourth differential signals. The LVDS receiver 44 supplies the LVDS receiver 44 through the transmission lines LVL1 through LVL4.

Each differential signal transmission line LVL1 to LVL4 is composed of two differential lines La and Lb. Terminal resistors RT are connected to the ends of the pair of differential lines La and Lb.

The LVDS receiver 44 receives the pixel data R / G / B and the flag data F from the LVDS transmitter 34 through the first to fourth differential signal transmission lines LVL1 to LVL4. Pixel data R / G / B and flag data F are converted into the original TTL signal form.

The LVDS receiver 44 includes first to fourth receivers Rx1 to Rx4. The first to fourth receivers Rx1 to Rx4 restore the pixel data R / G / B and the flag data F in the form of LVDS signals supplied thereto to the TTL signal and reconstruct the first to fourth data. The data recovery unit 45 supplies the data recovery unit 45 through the transmission lines L1 to L4.

The data restorer 45 receives the pixel data R / G / B and the flag data F from the LVDS receiver 44 through the first to fourth data transmission lines L1 to L4. The logic state of all the bits R0 to B9 constituting the pixel data R / G / B and the flag data F according to the logic state of the specific bit F0 included in the flag data F. It is determined whether or not to reverse the logic state of the specific bit (F0) included in the).

In detail, the data recovery unit 45 may include all the bits R0 to B9 of the pixel data R / G / B when the specific bit F0 has the first logical value. In addition to inverting so as to have, the flag data F including the specific bit F0 is deleted. On the other hand, the data recovery unit 45 does not invert the logic values of all bits R0 to B9 of the pixel data R / G / B when the specific bit F0 has the second logic value. And the flag data F including the specific bit F0 is deleted.

The first logic value may mean high logic, and the second logic value may mean low logic. On the contrary, the first logic value may mean low logic, and the second logic value may mean high logic.

The driving method of the liquid crystal display according to the exemplary embodiment of the present invention configured as described above will be described in detail as follows.

FIG. 4 is a diagram illustrating pixel data output from the data modulator 33 of FIG. 3.

The number of bits of the pixel data (R / G / B) and the flag data (F) may be any number of bits. Hereinafter, for convenience of description, a specific number of bits commonly used will be described. In particular, the flag data F may consist of 1 bit.

The data modulator 33 receives 30-bit pixel data R / G / B in the form of a TTL signal from the system in parallel through 32 transmission lines.

The 30-bit pixel data R / G / B includes 10-bit red pixel data R, 10-bit green pixel data B, and 10-bit blue pixel data B.

The flag data F is data generated by the data modulator 33. When the flag data F is not in use, the flag data F represents low logic, that is, a logic value '0'. In other words, the logic values of all the bits F0 and F1 constituting this flag data F are '0'.

The data modulator 33 checks the logic state of each of the 30 bits R0 to B9 constituting the pixel data R / G / B supplied to the data modulator 33. As a result of this check, when the logic values of the 30 bits R0 to B9 are all '1', the pixel data R / G / B is determined to be white data, and the 30 bits R0 to B9 are determined as white data. ), All of the logical values are reversed to '0'. The logical value of any one of the two bits F0 and F1 constituting the flag data F (hereinafter, referred to as 'specific bit F0') is inverted to '1'.

However, the data modulator 33 determines that the pixel data R / G / B is black data when the logic values of the 30 bits R0 to B9 supplied thereto are all '0'. The logic values of the thirty bits R0 through B9 are kept at '0'.

In addition, the data modulator 33 has a logic value '0' of any one of the 30 bits R0 to B9 supplied thereto, or a logic value of the 30 bits R0 to B9 is set. If different, the pixel data R / G / B is determined as general data, and the logic values of the thirty bits R0 to B9 and the logical values of the specific bit F0 are maintained as they are.

Meanwhile, the logic value of the other bit F1 constituting the flag data F may be maintained as '0' or '1'.

The data modulator 33 uses 32 bits of data consisting of the 30 bits of pixel data R / G / B and newly generated 2 bits of flag data F to transmit four data transmission lines TL1 to TL4. It supplies to the LVDS transmitter 34 through.

In this case, as shown in FIG. 4, the upper eight bits R0 to R7 of the ten bits R0 to R9 constituting the red pixel data R are connected through the first data transmission line TL1. The upper eight bits G0 to G7 of the ten bits G0 to G9 constituting the green pixel data G are sequentially supplied to the first transmitter Tx1, and the second data transmission line TL2 is connected to the first transmitter Tx1. Are sequentially supplied to the second transmitter Tx2, and the upper eight bits G0 to G7 of the ten bits B0 to B9 constituting the blue pixel data B are connected to the third data transmission line TL3. Are sequentially supplied to the third transmitter Tx3. The lower two bits R8 and R9 of the two bits F0 and F1 constituting the flag data F, the ten bits R0 to R9 constituting the red pixel data R, Among the lower two bits G8 and G9 of the ten bits G0 to G9 constituting the green pixel data G, and among the ten bits B0 to B9 constituting the blue pixel data B. The lower two bits B8 and B9 are sequentially supplied to the fourth transmitter Tx4 through the fourth data transmission line TL4.

Although not shown, each of the transmitters Tx1 to Tx4 includes a constant current source for generating a constant current and a plurality of switching elements. Each transmitter Tx1 to Tx4 turns on / off the switching element in response to pixel data R / G / B and flag data F, which are serially supplied through corresponding data transmission lines TL1 to TL4. The constant current from the constant current source flows to the differential signal transmission lines LVL1 to LVL4 so that voltage is applied to both ends of the termination resistors RT provided at the ends of the differential signal transmission lines LVL1 to LVL4. That is, each of the transmitters Tx1 to Tx4 converts the data in the form of the TTL signal supplied thereto to the LVDS signal using the constant current source and the plurality of switching elements.

At this time, each of the receivers Rx1 to Rx4 in the LVDS transmitter 34 converts the LVDS signal form into an original TTL signal form by amplifying the voltage difference across both ends of the termination resistor RT to a logic level.

The data recovery unit 45 checks the logical value of the specific bit F0 from the 32-bit data supplied from the receivers Rx1 to Rx4, and as a result of the check, the logical value of the specific bit F0 is '1'. In this case, the logic values of the 30 bits R0 to B9 constituting the pixel data R / G / B are inverted again to restore the original pixel data R / G / B, and the specific bit ( Delete F0). That is, all bits F0 and F1 included in the flag data F are deleted.

However, when the logic value of the specific bit F0 supplied to the data recovery unit 45 is '0', the data recovery unit 45 may include 30 bits R0 to B9 constituting the pixel data R / G / B. The logic value is kept as is and the specific bit F0 is deleted. That is, all bits F0 and F1 included in the flag data F are deleted.

Therefore, the data output from the data recovery unit 45 includes only 30-bit pixel data R / G / B from which the flag data F is removed.

5 is a view for explaining the effect of the structure of the present invention.

FIG. 5A illustrates an example in which black data and white data are alternately output without using the flag data F. As shown in FIG. 5A, pixel data R / G / B It can be seen that the logical values of all the bits R0 to B9 are inverted each time) is converted from black data to white data (or when white data is converted to black data). Accordingly, the electromagnetic interference generated from the data transmission lines TL1 to TL4 and L1 to L4 and the differential signal transmission lines LVL1 to LVL4 may increase considerably.

FIG. 5B is a diagram showing an example in which black data and white data are alternately output in a state in which the flag data F is utilized, and as shown in the figure, the pixel data R / G / When B) is converted from black data to white data (or from white data to black data), the logical values of all the bits R0 to B9 except for the specific bit F0 remain. Can be. Accordingly, electromagnetic interference generated from the data transmission lines TL1 to TL4 and L1 to L4 and the differential signal transmission lines LVL1 to LVL4 may be significantly reduced.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1 is a view showing a liquid crystal display device according to an embodiment of the present invention.

2 is a diagram illustrating a connection relationship between a timing controller and a data driver of FIG. 2;

3 is a detailed configuration diagram of the timing controller and driver IC of FIG. 2.

4 is a diagram illustrating pixel data output from the data modulator of FIG. 3.

5 is a view for explaining the effect of the structure of the present invention.

Claims (9)

It is determined whether the pixel data is modulated according to a logic state of bits constituting the pixel data by receiving pixel data from an external source, generating flag data indicating information on whether the pixel data is modulated, and generating the flag data and A timing controller configured to output the pixel data; And, And a data driver receiving pixel data and flag data from the timing controller through a plurality of differential signal transmission lines and determining whether to restore the pixel data according to a logic state of a bit constituting the flag data. Driving circuit of liquid crystal display device. The method of claim 1, The timing controller, When the pixel data in the form of TTL (Transistor Transistor Logic) signal is supplied from the outside and the logic states of all the bits constituting the pixel data are the same, the logic states of the bits constituting the pixel data are inverted and the flag data is inverted. A data modulator for inverting the logic state of any one of the bits constituting the bit; And, And an LVDS transmitter for converting pixel data and flag data from the data modulator into a Low Voltage Differential Signal (LVDS) signal. The method of claim 2, The data modulator, Inverting all the bits making up the pixel data to have a second logic value when all the bits making up the pixel data have a first logic value, and inverting the specific bits to have a second logic value; And, And when any one of all bits constituting the pixel data has a second logic value, the logic value of all the bits constituting the pixel data and a specific bit are not inverted. The method of claim 2, The data driver, An LVDS receiver receiving pixel data and flag data from the LVDS transmitter through the plurality of differential signal transmission lines and converting the pixel data and flag data into an original TTL signal; And, And a data restoring unit receiving pixel data and flag data from the LVDS receiving unit and determining whether the logical states of all bits of the pixel data are inverted according to a logic state of a specific bit included in the flag data. A driving circuit of the liquid crystal display device. The method of claim 4, wherein The data recovery unit, Inverting all the bits constituting the pixel data to have a first logic value when the specific bit has a second logic value, and deleting the flag data; And, And when the specific bit has the first logic value, does not invert the logic value of all the bits constituting the pixel data and deletes the flag data. The method of claim 2, The pixel data includes red pixel data, green pixel data, and blue pixel data; A plurality of data transmission lines for transmitting the pixel data and the flag data from the data modulator to the LVDS transmitter; The data transmission lines, A first data transmission line configured to serially transmit upper m bits (n is a natural number less than n) among n bits (n is a natural number of two or more) forming the red pixel data; A second data transmission line configured to serially transmit upper m bits of the n bits constituting the green pixel data; A third data transmission line configured to serially transmit upper m bits of the n bits constituting the blue pixel data in series; And, K bits (k is nm) constituting the flag data, lower k bits of the red pixel data, lower k bits of the green pixel data, and k bits of the blue pixel data in series And a fourth data transmission line for transmitting. A step of receiving the pixel data from the outside to determine whether the pixel data is modulated according to the logic state of the bits constituting the pixel data, and generating flag data indicating information on whether the pixel data is modulated; Step B for transmitting the pixel data and the flag data which have passed the step A through a plurality of data transmission lines; And a step C of determining whether to restore the pixel data according to a logic state of a bit constituting the flag data by receiving the pixel data and the flag data which have passed the step B. 2. The method of claim 7, wherein Step A, When the pixel data in the form of TTL signal is supplied from the outside and the logic states of all the bits constituting the pixel data are the same, the logic states of the bits constituting the pixel data are inverted and among the bits constituting the flag data. Inverting the logic state of any one particular bit; And, And a step (E) of converting pixel data and flag data from the data modulator into an LVDS signal form. The method of claim 8, The step C, Receiving the pixel data and the flag data through the step B and converting the pixel data and the flag data into an original TTL signal; And, And a G step of determining whether to invert the logic state of all bits of the pixel data according to the logic state of a specific bit included in the flag data by receiving the pixel data and the flag data which have passed the F step. A method of driving a liquid crystal display device.

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