CN105027293A - 功率场效应晶体管以及对应封装、系统及制造方法 - Google Patents

功率场效应晶体管以及对应封装、系统及制造方法 Download PDF

Info

Publication number
CN105027293A
CN105027293A CN201480011132.2A CN201480011132A CN105027293A CN 105027293 A CN105027293 A CN 105027293A CN 201480011132 A CN201480011132 A CN 201480011132A CN 105027293 A CN105027293 A CN 105027293A
Authority
CN
China
Prior art keywords
fet
power fet
grid
grids
source region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201480011132.2A
Other languages
English (en)
Inventor
格雷戈里·迪克斯
特丽·L·克利夫兰
乔伊·迪佩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microchip Technology Inc
Original Assignee
Microchip Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microchip Technology Inc filed Critical Microchip Technology Inc
Publication of CN105027293A publication Critical patent/CN105027293A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7817—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/10—Modifications for increasing the maximum permissible switched voltage
    • H03K17/102—Modifications for increasing the maximum permissible switched voltage in field-effect transistor switches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

本发明涉及一种功率FET，其包括半导体芯片(500)，所述半导体芯片具有各自并联耦合的多个源极及漏极触点(506a到506c、504a到504c)以及彼此分离的多个栅极区，其中每一栅极区连接到单独接合垫(502a到502c)。通过将功率FET的栅极分段成若干独立栅极区，控制器可选择所述FET的使用程度。例如针对切换模式应用，通过基于电流负载而动态地选择所述功率FET的大小，跨越操作的整个范围的总体效率可在不具有额外装置的情况下优化。

Description

功率场效应晶体管以及对应封装、系统及制造方法
相关申请案交叉参考
本申请案主张2013年3月11日提出申请的第61/776,500号美国临时专利申请案的权益，所述美国临时专利申请案特此出于所有目的如同全面陈述于本文中一般以全文引用的方式并入。
技术领域
本发明涉及场效应晶体管，特定来说涉及一种多栅极场效应晶体管。
背景技术
在当今的世界中，用于转换电力的切换模式电力供应器为近乎普遍的。由于切换模式电力供应器通常展现高效率的事实，因此对移动或便携式电子装置来说其为有吸引力的，这是因为这些装置通常电池没电。然而，切换模式电力供应器会取决于负载条件而展现低效率。部分来说，由于功率晶体管(通常场效应晶体管)在操作中为通常固定的，因此此结果不允许最优控制。
因此，存在跨越负载条件的宽广范围提高切换模式电力供应器的效率的需要。为此，需要允许定制控制的经改进场效应晶体管。
发明内容
根据各种实施例，一种经改进场效应晶体管(FET)可通过将功率FET的栅极分段而提供，其中控制器可“决定”所述FET的使用程度，由此跨越整个范围增加效率。
根据实施例，一种功率场效应晶体管包含半导体芯片，所述半导体芯片具有各自并联耦合的多个源极及漏极触点以及彼此分离的多个栅极区，其中每一栅极连接到单独接合垫。在一些实施例中，所述栅极接合垫是配置为经选择性控制以确定所述功率FET的功能性质。在一些实施例中，所述FET包括彼此绝缘的两个栅极以及共用漏极及源极区域。在一些实施例中，所述FET包含多个(n个)栅极，其中n>2。
根据实施例，一种布置于封装内的功率场效应晶体管(FET)包含半导体芯片，所述半导体芯片具有连接到所述封装的相应引脚的多个源极及漏极触点以及经配置以并联连接以确定所述功率FET的功能性质的彼此分离的多个栅极，其中每一栅极连接到所述封装的单独引脚。
根据实施例，一种用于制造半导体芯片的方法包含：提供各自并联耦合的多个源极及漏极触点；及提供彼此分离的多个栅极区，其中每一栅极连接到单独接合垫。在一些实施例中，将所述栅极接合垫配置为经选择性控制以确定所述功率FET的功能性质。在一些实施例中，所述FET包括彼此绝缘的两个栅极以及共用漏极及源极区域。在一些实施例中，所述FET包含多个(n个)栅极，其中n>2。
根据实施例，一种系统包含：功率FET，其包括彼此绝缘的两个栅极以及共用漏极及源极区域；及控制器，其经配置以针对所述功率FET的所述两个栅极中的每一者提供单独控制信号。在一些实施例中，栅极接合垫是配置为经选择性控制以确定所述功率FET的功能性质。在一些实施例中，所述FET包括彼此绝缘的两个栅极以及共用漏极及源极区域。在一些实施例中，所述FET包含多个(n个)栅极，其中n>2。
根据实施例，一种方法包含：提供包括彼此绝缘的两个栅极以及共用漏极及源极区域的功率FET；及提供经配置以针对所述功率FET的所述两个栅极中的每一者提供单独控制信号的控制器。在一些实施例中，将栅极接合垫配置为经选择性控制以确定所述功率FET的功能性质。在一些实施例中，所述FET包括彼此绝缘的两个栅极以及共用漏极及源极区域。在一些实施例中，所述FET包含多个(n个)栅极，其中n>2。
在结合以下描述及附图考虑时，将更好地了解及理解本发明的这些及其它方面。然而，应理解，尽管指示本发明的各种实施例及其众多特定细节，但以下描述是以图解说明方式而非限制方式给出。可在不背离本发明的精神的情况下在本发明的范围内做出许多替换、修改、添加及/或重新布置，且本发明包含所有这些替换、修改、添加及/或重新布置。
附图说明
包含随附及形成本说明书的部分的图式以描绘本发明的特定方面。应注意，图式中所图解说明的特征未必按比例绘制。通过结合附图参考以下描述，可获取对本发明及其优点的较完整理解，在附图中相似参考编号指示相似特征，且其中：
图1A是现有技术功率场效应晶体管(FET)的图式。
图1B是图解说明用于功率FET的引脚/封装配置的图式。
图2是驱动器电路的实例。
图3是各种功率FET的效率对负载电流的图表。
图4是图解说明根据实施例的功率FET的图式。
图5A图解说明FET裸片的实例。
图5B图解说明图5A的FET裸片的引线框架的实例。
图6图解说明使用根据实施例的功率FET的示范性驱动电路。
图7是根据实施例的功率FET的效率对负载电流的图表。
图8是图解说明示范性晶体管单元的图式。
具体实施方式
参考在附图中图解说明且在以下描述中详述的示范性(且因此非限制性)实施例更全面地阐释本发明及其各种特征及有利细节。然而，应理解，尽管指示优选实施例，但详细描述及特定实例仅以图解说明方式而非以限制方式给出。可省略对已知编程技术、计算机软件、硬件、操作平台及协议的描述以便不会不必要地在细节上模糊本发明。所属领域的技术人员将从本发明明了在基本发明概念的精神及/或范围内的各种替换、修改、添加及/或重新布置。
根据各种实施例，可提供允许两个(2)以上栅极的引脚输出的功率FET装置。通过将功率FET的栅极分段成“n”个分段，用户及/或控制器可选择FET的使用程度。通过基于电流负载而动态地选择FET的大小，跨越操作的整个范围的总体效率可在不具有额外装置的情况下优化。因此，尽管此装置具有并联耦合的共用源极及漏极区域，但栅极为分离的且可经控制以包含相关联漏极及源极区域。举例来说，根据一些实施例，共用功率MOSFET包括通过内部金属层并联耦合的多个晶体管单元。根据各种实施例，尽管这些单元的漏极及源极区域为内部并联连接的，但仅一些单元的栅极经并联耦合以形成彼此分离的多个栅极。总之，本发明标的物不限于任何特定FET技术，但可应用于任何类型的场效应晶体管。
切换调节器中的共用结构是彼此上下地堆叠的两个功率FET。在操作中，这些上部及下部FET轮流接通。图1A展示可用作驱动器电路中的上部或下部功率FET的常规功率FET设计100。如可见，此常规晶体管100包含源极102且具有单个栅极104及相关联触点。
图1B展示典型N沟道功率MOSFET 112及其(若干)内部连接。特定来说，可如以(举例来说)110a及110b所展示来体现集成电路封装110。MOSFET 112包含源极连接114a到114b、漏极连接116a到116d及单个栅极连接118。如可了解，多个漏极及源极连接提供低电阻连接。
图2图解说明包含控制器202及晶体管204的驱动电路200，晶体管204包含上部FET 206a及下部FET 206b。控制器202分别经由连接208、210而驱动上部晶体管206a及下部晶体管206b的栅极。上部及下部FET大小基于(举例来说)切换模式功率应用的负载条件而经选择以提供良好效率。
如图3的图式中所展示，在大负载处，设计将包含大FET装置。举例来说，可选择由受让人制造的高速N沟道功率MOSFET MCP87050及MCP87018。然而，在轻负载处，较好选择将为也由受让人制造的N沟道功率MOSFET MCP87130及MCP87050。功率FET可为NMOS或PMOS装置。根据进一步实施例，这些功率MOSFET可集成到例如微控制器的混合信号装置中。
现在转到图4，展示根据实施例的功率FET 400。在所图解说明的实例中，功率FET400包含源极402以及第一栅极404a及第二栅极404b。此装置可划分成两个部分：操作总FET的一部分的栅极A 404a及操作其余部分的栅极B 404b。因此，根据各种实施例，提供共用漏极及源极区域，但栅极分成多个部分(两个或两个以上)，其中栅极连接到内部不短路的个别栅极引脚。因此，可单独控制每一栅极404a、404b。栅极404a、404b可经外部短路以提供装置的全功率。然而，可通过仅使用两个栅极中的一者而按比例减小其参数。如果实施两个以上栅极，那么可实现甚至更大的可缩放性。
多个栅极可如图5A及图5B中所展示而实施。特定来说，展示使用引线框架上倒装芯片技术的实施方案。更特定来说，以500展示实例性裸片。裸片500包含栅极接触元件502a到502c、漏极接触元件504a到504c及源极接触元件506a到506c。
在图5B中展示对应引线框架510。引线框架510包含栅极引线512a到512c。引线框架510进一步包含漏极引线指形件514及源极引线指形件516。漏极引线指形件514经布置有接触条带518以形成单个接触元件。同样地，源极引线指形件516经布置有接触条带520，从而形成单个接触元件。
根据实施例的功率晶体管可(举例来说)通过针对接触元件502a到502c、504a到504c及506a到506c提供焊料“球块”且通过适当加热将引线框架510附接到裸片500而形成。依据共同让与的美国专利申请案US-2012-0126406-A1，通常知晓用于制造此装置的适合引线框架上倒装芯片技术，所述美国专利申请案特此以引用的方式并入。
图6图解说明根据实施例的包含晶体管的驱动电路600。驱动电路600包含控制器602及晶体管604，晶体管604包含上部FET 606a及下部FET 606b。上部及下部FET大小可具有与图2的驱动电路中相同的最大负载大小，但其具有两个栅极连接以分段装置的使用程度。也就是说，如所展示，经由连接608a、608b的上部FET 606a及经由连接610a、610b的下部FET 606b。
图7展示类似于图3中所展示的图表的所得图表。借助可选择数目个栅极，可基于电流负载而控制FET的可达大小且可获得最优效率。也就是说，跨越负载条件的范围，效率可为相对稳定的。
注意，根据各种实施例的功率FET的设计并不限制于两个栅极。而是，可提供多个(n个)栅极。此可仅受限制于硅裸片上可用的实际面积。
总之，根据各种实施例，可通过栅极的灵活指派而提供针对电流负载的宽广范围的单个FET选择。因此，提供仅用单相成本而实现“多相”解决方案的益处。
最后，图8展示穿过根据实施例的功率晶体管的可能实施例的横截面。如可见，标准场效应功率晶体管可由并联耦合的多个单元形成。单元可对称地形成，如所展示。此处，在衬底810上，可形成外延层820。在外延层820内，单元可由其中嵌入有源极区域840的基极区域830形成。在两个基极区域中间，可形成漏极区域850。针对每一单元，多个栅极860可形成于外延层820的顶部上的绝缘层821内，其中栅极860至少覆盖源极区域840与外延层820之间的基极区域内的横向沟道区域。其它单元可紧挨着此单元布置。此外，可使用其它单元结构，举例来说，基极及源极区域可为对称的，使得基极区域还可用于相邻单元。额外绝缘层821可提供于结构的顶部上。
虽然已关于其特定实施例描述本发明，但这些实施例仅为说明性的而非限制本发明。包含发明摘要及发明内容中的描述的本发明的所图解说明实施例的本文中描述并非打算穷尽性或将本发明限制于本文中所揭示的精确形式(且特定来说，在发明摘要或发明内容内包含任何特定实施例、特征或功能并非打算将本发明的范围限制于此实施例、特征或功能)。而是，所述描述打算在不将本发明限制于包含发明摘要或发明内容中所描述的任何此实施例特征或功能的任何特定描述的实施例、特征或功能的情况下描述说明性实施例、特征及功能以便给所属领域的技术人员提供用以理解本发明的上下文。
尽管本文中仅出于说明性目的而描述本发明的特定实施例及实例，但如所属领域的技术人员将认识及了解到，可能在本发明的精神及范围内做出各种等效修改。如所指示，可鉴于本发明的所图解说明实施例的前述描述而对本发明做出这些修改且这些修改将包含于本发明的精神及范围内。因此，尽管本文中已参考其特定实施例来描述本发明，但前述揭示内容中打算涵盖修改宽容度、各种改变及替代，且将了解，在一些例子中，在不背离如所陈述的本发明的范围及精神的情况下，将采用本发明的实施例的一些特征而不具有其它特征的对应使用。因此，可做出许多修改以使特定情形或材料适应本发明的基本范围及精神。
贯穿本说明书，对“一个实施例”、“一实施例”或“特定实施例”或者类似术语的提及意指结合实施例所描述的特定特征、结构或特性包含于至少一个实施例中且可不必呈现于所有实施例中。因此，贯穿本说明书，在各种地方中相应出现的短语“在一个实施例中”、“在一实施例中”或“在特定实施例中”或者类似术语未必是指相同实施例。此外，任何特定实施例的特定特征、结构或特性可以任何适合方式与一或多个其它实施例组合。将理解，本文中所描述及所图解说明的实施例的其它变化及修改鉴于本文中的教示是可能的且将视为本发明的精神及范围的部分。
在本文中的描述中，提供例如组件及/或方法的实例的众多特定细节以提供对本发明的实施例的透彻理解。然而，所属领域的技术人员将认识到，可能够在不具有特定细节中的一或多者或具有其它设备、系统、组合件、方法、组件、材料、部件及/或类似物的情况下实践实施例。在其它例子中，为避免模糊本发明的实施例的方面，未具体展示或详细描述众所周知的结构、组件、系统、材料或操作。尽管本发明可通过使用特定实施例来图解说明，但此并不且不会将本发明限制于任何特定实施例且所属领域的技术人员将认识到额外实施例是可容易理解的且是本发明的一部分。
如本文中所使用，术语“包括(comprises)”、“包括(comprising)”、“包含(includes)”、“包含(including)”、“具有(has)”、“具有(having)”或其任何其它变化打算涵盖非穷尽性包含。举例来说，包括要素清单的过程、产品、物品或设备未必仅限制于彼等要素，而是可包含未明确列举或此过程、过程、物品或设备所固有的其它要素。
此外，除非另外指示，否则如本文中所使用的术语“或”通常打算意指“及/或”。举例来说，条件A或B是通过以下各项中的任一者来满足：A为真(或存在)且B为假(或不存在)、A为假(或不存在)且B为真(或存在)以及A与B两者均为真(或存在)。如本文中所使用，包含所附权利要求书，术语前面的“一(a)”或“一(an)”(及在先行词基础为“一(a)”或“一(an)”时的“所述(the)”)包含此术语的单数及复数两者，除非权利要求书内另外明确指示(即，参考“一(a)”或“一(an)”明确地指示仅为单数或仅为复数)。此外，如在本文中的描述中及贯穿所附权利要求书所使用，“在……中”的意义包含“在……中”及“在……上”，除非上下文另外明确指出。
将了解，图式/各图中所描绘的元件中的一或多者还可以较分离或集成方式实施或者在特定情形中甚至移除或使变为不可操作，如根据特定应用为有用的。另外，图式/各图中的任何信号箭头应视为仅为示范性且并非限制性，除非另外具体注明。

Claims (17)

1.一种功率场效应晶体管，其包括：
半导体芯片，其具有各自并联耦合的多个源极及漏极触点以及彼此分离的多个栅极区，其中每一栅极连接到单独接合垫。
2.根据权利要求1所述的功率FET，其中所述栅极接合垫经配置为经选择性控制以确定所述功率FET的功能性质。
3.根据权利要求2所述的功率FET，其中所述FET包括彼此绝缘的两个栅极以及共用漏极及源极区域。
4.根据权利要求1所述的功率FET，其包括多个(n个)栅极，其中n>2。
5.一种布置于封装内的功率场效应晶体管FET，其包括半导体芯片，所述半导体芯片具有连接到所述封装的相应引脚的多个源极及漏极触点以及经配置以并联连接以确定所述功率FET的功能性质的彼此分离的多个栅极，其中每一栅极连接到所述封装的单独引脚。
6.一种用于制造半导体芯片的方法，其包括：
提供各自并联耦合的多个源极及漏极触点；及
提供彼此分离的多个栅极区，其中每一栅极连接到单独接合垫。
7.根据权利要求6所述的方法，其中将所述栅极接合垫配置为经选择性控制以确定所述功率FET的功能性质。
8.根据权利要求7所述的方法，其中所述FET包括彼此绝缘的两个栅极以及共用漏极及源极区域。
9.根据权利要求6所述的功率FET，其包括多个(n个)栅极，其中n>2。
10.一种系统，其包括：
功率FET，其包括彼此绝缘的两个栅极以及共用漏极及源极区域，及
控制器，其经配置以针对所述功率FET的所述两个栅极中的每一者提供单独控制信号。
11.根据权利要求10所述的系统，其中栅极接合垫经配置为经选择性控制以确定所述功率FET的功能性质。
12.根据权利要求11所述的系统，其中所述FET包括彼此绝缘的两个栅极以及共用漏极及源极区域。
13.根据权利要求10所述的系统，其包括多个(n个)栅极，其中n>2。
14.一种方法，其包括：
提供包括彼此绝缘的两个栅极以及共用漏极及源极区域的功率FET，及
提供经配置以针对所述功率FET的所述两个栅极中的每一者提供单独控制信号的控制器。
15.根据权利要求14所述的方法，其中将栅极接合垫配置为经选择性控制以确定所述功率FET的功能性质。
16.根据权利要求15所述的方法，其中所述FET包括彼此绝缘的两个栅极以及共用漏极及源极区域。
17.根据权利要求16所述的方法，其包括多个(n个)栅极，其中n>2。
CN201480011132.2A 2013-03-11 2014-03-10 功率场效应晶体管以及对应封装、系统及制造方法 Pending CN105027293A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201361776500P 2013-03-11 2013-03-11
US61/776,500 2013-03-11
PCT/US2014/022640 WO2014164507A1 (en) 2013-03-11 2014-03-10 Power field-effect transistor and corresponding package, system and manufacturing methods

Publications (1)

Publication Number Publication Date
CN105027293A true CN105027293A (zh) 2015-11-04

Family

ID=50686102

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480011132.2A Pending CN105027293A (zh) 2013-03-11 2014-03-10 功率场效应晶体管以及对应封装、系统及制造方法

Country Status (5)

Country Link
US (1) US20140253218A1 (zh)
KR (1) KR20150127048A (zh)
CN (1) CN105027293A (zh)
TW (1) TW201448221A (zh)
WO (1) WO2014164507A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111653620A (zh) * 2019-03-04 2020-09-11 英飞凌科技美洲公司 使用不同的阈值电压分段增加正向偏置安全工作区域

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9048838B2 (en) * 2013-10-30 2015-06-02 Infineon Technologies Austria Ag Switching circuit
US9525063B2 (en) 2013-10-30 2016-12-20 Infineon Technologies Austria Ag Switching circuit
US10613134B2 (en) 2016-12-22 2020-04-07 Texas Instruments Incorporated High-side gate over-voltage stress testing
CN113921606A (zh) * 2021-10-08 2022-01-11 阳光电源股份有限公司 一种绝缘栅双极型场效应管、功率模组及功率变换器

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8104414A (nl) * 1981-09-25 1983-04-18 Philips Nv Halfgeleiderinrichting met veldeffekttransistor.
GB9201004D0 (en) * 1992-01-17 1992-03-11 Philips Electronic Associated A semiconductor device comprising an insulated gate field effect device
US5973367A (en) * 1995-10-13 1999-10-26 Siliconix Incorporated Multiple gated MOSFET for use in DC-DC converter
US6137138A (en) * 1998-03-06 2000-10-24 Spectrian Corporation MOSFET power transistor having offset gate and drain pads to reduce capacitance
US7838948B2 (en) * 2007-01-30 2010-11-23 Infineon Technologies Ag Fin interconnects for multigate FET circuit blocks
US9093433B2 (en) * 2010-11-18 2015-07-28 Microchip Technology Incorporated Using bump bonding to distribute current flow on a semiconductor power device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111653620A (zh) * 2019-03-04 2020-09-11 英飞凌科技美洲公司 使用不同的阈值电压分段增加正向偏置安全工作区域

Also Published As

Publication number Publication date
US20140253218A1 (en) 2014-09-11
KR20150127048A (ko) 2015-11-16
TW201448221A (zh) 2014-12-16
WO2014164507A1 (en) 2014-10-09

Similar Documents

Publication Publication Date Title
US8461669B2 (en) Integrated power converter package with die stacking
CN106067794B (zh) 半导体装置
JP6320875B2 (ja) 半導体装置、電力制御装置および電子システム
CN105027293A (zh) 功率场效应晶体管以及对应封装、系统及制造方法
TWI443836B (zh) 於共同基板上之功率裝置整合
TWI623083B (zh) 於共同基板上之功率裝置整合
US10249759B2 (en) Connection arrangements for integrated lateral diffusion field effect transistors
JP2002368121A (ja) 電力用半導体装置
US11335627B2 (en) Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact
CN106558605A (zh) 半导体器件及其制造方法
EP3097584A1 (en) Integrated high side gate driver structure and circuit for driving high side power transistors
JPWO2017090389A1 (ja) 半導体集積回路装置
JP2018157084A (ja) 半導体集積回路装置
CN105336788B (zh) 半导体器件
US20130228854A1 (en) Power field effect transistor
CN104969342A (zh) 半导体装置
CN101236964B (zh) 具有开关元件和两个二极管的半导体装置
JP4525629B2 (ja) レベルシフタ
US20120068329A1 (en) Semiconductor device
CN104769715B (zh) 共用衬底上的功率裝置集成
JP4154671B2 (ja) 電力用半導体モジュール
CN113497131A (zh) 功率芯片、其控制方法以及电器设备
JP2024046114A (ja) 半導体装置
CN111342638A (zh) 一种功率器件、桥臂电路、功率模块及电子设备
JP2005327752A (ja) 電子装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20151104