CN105023846A - 在金属栅极线端中具有t形的器件和制造半导体器件的方法 - Google Patents

在金属栅极线端中具有t形的器件和制造半导体器件的方法 Download PDF

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CN105023846A
CN105023846A CN201510175441.XA CN201510175441A CN105023846A CN 105023846 A CN105023846 A CN 105023846A CN 201510175441 A CN201510175441 A CN 201510175441A CN 105023846 A CN105023846 A CN 105023846A
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sti
fin
semiconductor device
metal gates
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林健智
叶建宏
沈冠杰
张嘉德
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开了在半导体器件中制造金属栅极结构的方法。该方法包括：去除伪多晶硅栅极，使用干蚀刻工艺和湿横向蚀刻工艺去除IL氧化物和STI以在半导体器件中形成T形空隙，以及在T形空隙中沉积金属栅极材料以在金属栅极线端中形成T形结构。本发明公开了由包括伪多晶硅栅极的去除的工艺制造的半导体器件。该半导体器件包括OD鳍以及在OD鳍的部分之上制造并且邻近OD鳍的侧部的金属栅极。金属栅极在金属栅极线端中具有T形结构。通过使用干蚀刻工艺和湿横向蚀刻工艺去除IL氧化物和STI以形成T形空隙来形成T形结构。本发明还涉及在金属栅极线端中具有T形的器件和制造半导体器件的方法。

Description

在金属栅极线端中具有T形的器件和制造半导体器件的方法
技术领域
本专利文件中描述的技术涉及金属氧化物半导体场效应晶体管(MOSFET)器件，更具体地，涉及具有使用替换栅极工艺形成的栅极结构的MOSFET器件以及制造这样的器件的方法。
背景技术
在过去的几十年间，诸如MOSFET的半导体器件的缩放已经使集成电路的速度、性能、密度和每单位功能的成本能够不断地改进。用于产生金属栅极的工艺的改进可以进一步缩放集成电路。
可以在块状半导体衬底(平面器件)或在绝缘体上硅(SOI)类型的结构上制造MOSFET。例如，在替换栅极工艺中，可以由多晶硅(poly)形成伪栅极结构。在开始或继续源极-漏极(S/D)处理之后，伪栅极结构被去除并且由导电的含金属栅极堆叠件替换，含金属栅极堆叠件位于块状半导体衬底或SOI结构的硅层中的S/D之间的沟道区上面。
发明内容
为了解决现有技术中存在的问题，本发明提供了一种在半导体器件中制造金属栅极结构的方法，所述方法包括：去除伪多晶硅栅极；使用干蚀刻工艺和湿横向蚀刻工艺去除层间(IL)氧化物和浅沟槽隔离(STI)以在所述半导体器件中形成T形空隙；在所述T形空隙中沉积金属栅极材料以在金属栅极线端中形成T形结构。
在上述方法中，其中，所述干蚀刻工艺和湿横向蚀刻工艺引起1nm至10nm的横向蚀刻。
在上述方法中，其中，去除所述伪多晶硅栅极产生保留在氧化扩散(OD)部分之上的IL氧化物。
在上述方法中，其中，去除所述IL氧化物和所述STI引起氧化扩散(OD)部分的顶面上的IL氧化物去除以及邻近所述OD部分的侧面的STI去除。
在上述方法中，其中，去除所述IL氧化物和所述STI引起层间介电(ILD)层的部分下方的STI去除。
在上述方法中，其中，漏致势垒降低(DIBL)性能比在所述金属栅极线端中未形成T形结构的半导体器件的DIBL性能高
在上述方法中，其中，截止源电流(Isof)性能比在所述金属栅极线端中未形成T形结构的半导体器件的Isof性能高。
根据本发明的另一实施例，提供了一种制造晶体管的方法：制造半导体结构，所述半导体结构包括具有凸起的鳍的氧化扩散(OD)区、位于所述凸起的鳍的侧边上的浅沟槽隔离(STI)、位于鳍之上的层间(IL)氧化物、横跨鳍的伪多晶硅栅极、以及位于所述伪多晶硅栅极的侧边上的层间介电(ILD)层；抛光所述ILD层和所述伪多晶硅栅极以减小它们的高度；去除所述伪多晶硅栅极；去除所述IL氧化物和部分所述STI以在所述半导体结构中形成T形空隙；以及在所述T形空隙中沉积金属栅极材料以在金属栅极线端中形成T形结构。
在上述方法中，其中，使用干蚀刻工艺和湿横向蚀刻工艺实现去除所述IL氧化物和所述STI。
在上述方法中，其中，使用干蚀刻工艺和湿横向蚀刻工艺实现去除所述IL氧化物和所述STI，其中，所述干蚀刻工艺和湿横向蚀刻工艺的性能引起1nm至10nm的横向蚀刻。
在上述方法中，其中，去除所述IL氧化物和所述STI引起OD部分的顶面上的IL氧化物去除以及邻近所述OD部分的侧面的STI去除。
在上述方法中，其中，去除所述IL氧化物和所述STI引起所述ILD层的部分下方的STI去除。
在上述方法中，其中，漏致势垒降低(DIBL)性能比在所述金属栅极线端中未形成T形结构的晶体管的DIBL性能高。
在上述方法中，其中，截止源电流(Isof)性能比在所述金属栅极线端中未形成T形结构的晶体管的Isof性能高。
根据本发明的另一实施例，提供了一种由包括伪多晶硅栅极的去除的工艺制造的半导体器件，所述半导体器件包括：氧化扩散(OD)鳍；以及金属栅极，在所述OD鳍的部分之上制造并且邻近所述OD鳍的侧部，所述金属栅极在金属栅极线端中具有T形结构；其中，通过使用干蚀刻工艺和湿横向蚀刻工艺去除层间(IL)氧化物和浅沟槽隔离(STI)以形成T形空隙来形成所述T形结构。
在上述半导体器件中，其中，所述干蚀刻工艺和湿横向蚀刻工艺引起1nm至10nm的横向蚀刻。
在上述半导体器件中，其中，所述湿横向蚀刻工艺的应用引起邻近所述OD鳍的所述侧部的STI去除。
在上述半导体器件中，其中，所述干蚀刻工艺和所述湿横向蚀刻工艺的应用引起层间介电(ILD)层的部分下方的STI去除。
在上述半导体器件中，其中，漏致势垒降低(DIBL)性能比在所述金属栅极线端中未形成T形结构的类似的晶体管的DIBL性能高。
在上述半导体器件中，其中，截止源电流(Isof)性能比在所述金属栅极线端中未形成T形结构的类似的晶体管的Isof性能高。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1是根据一些实施例的示出在金属栅极线端中具有T形结构12的示例性半导体结构10的截面图。
图2是根据一些实施例的示出用于制造在金属栅极端部中具有T形结构的半导体结构的示例性工艺的工艺流程图。
图3至图6示出了根据一些实施例的在具有金属栅极的晶体管的制造的不同阶段期间的示例性半导体的截面图，其中金属栅极在金属栅极线端中具有T形结构。
图7A和图7B是根据一些实施例的示出对于NMOS和PMOS晶体管的预测的漏致势垒降低(DIBL)相对于阈值电压(Vts)的图。
图8A和图8B是根据一些实施例的示出对于NMOS和PMOS晶体管的预测的截止源电流(Isof)相对于饱和电流(Isat)的图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作相应的解释。
可以使用工艺制造平面晶体管，该工艺包括：制造用于晶体管的氧化扩散(OD)区，制造用于晶体管的伪多晶硅栅极，制造晶体管的源极和漏极区，以及然后使用可以称为替换多晶硅栅极(RPG)工艺的工艺制造晶体管的栅极区。RPG工艺包括去除伪多晶硅栅极以及用金属栅极替换伪多晶硅栅极。在利用RPG工艺的半导体制造工艺中，可以通过将金属栅极的线端部分形成为T形结构来改进晶体管性能。这可以允许晶体管利用具有更好的栅极可控性的较大的有效OD宽度。这可以产生改进的晶体管性能。
图1示出了在金属栅极线端中具有T形结构12的示例性半导体结构10。该示例性半导体结构包括具有凸起的鳍的OD区14、位于OD区的部分之上并且围绕OD鳍的浅沟槽隔离(STI)16的材料、以及位于STI 16和OD鳍14之上的层间介电(ILD)层18。该示例性半导体结构还包括金属栅极20，金属栅极20包括金属栅极线端中的T形结构12。
图2是示出用于制造在金属栅极端部中具有T形结构的半导体结构的示例性工艺的工艺流程图。首先制造半导体结构，该半导体结构具有带有OD鳍的OD区、伪多晶硅栅极、围绕OD鳍的STI层、以及位于OD鳍和STI层之上的ILD材料层(操作102)。制造操作的最终步骤可以是使用诸如化学机械抛光(CMP)操作的ILD抛光操作(操作104)减小多晶硅栅极和ILD层的尺寸并且使多晶硅栅极和ILD层成形。
接下来，实施伪多晶硅栅极去除操作(操作106)以去除伪多晶硅栅极材料。可以通过诸如蚀刻的操作实施伪多晶硅栅极去除并且伪多晶硅栅极去除可以导致伪多晶硅栅极材料的去除但是留下位于OD鳍的顶面之上的伪层间(IL)氧化物。
在实施伪多晶硅栅极去除操作之后，进行伪IL氧化物去除操作(操作108)。该实例中的伪IL氧化物去除操作包括干和湿蚀刻操作(操作110)。可以实施干和湿蚀刻操作以去除位于OD鳍的顶面之上的伪IL氧化物，以去除通过伪多晶硅栅极空出的区域下方的STI，以及以去除位于ILD层的部分下方并且邻近OD鳍的侧面的STI(例如，用1nm至10nm的横向蚀刻)，从而在半导体结构中形成T形空隙。在一些实例中，在干蚀刻操作之后实施湿蚀刻操作。
在伪IL氧化物去除之后，可以在通过伪多晶硅栅极去除和IL氧化物去除操作空出的区域中沉积(操作112)包括高k介电材料的金属栅极材料。可以沉积并且抛光金属栅极材料以在金属栅极线端中形成T形结构。
图3至图6示出了在具有金属栅极的晶体管的制造的不同阶段期间的示例性半导体的截面图，其中金属栅极在金属栅极线端中具有T形结构。图3中示出了示例性半导体器件，该半导体器件制造为具有带有凸起的鳍204的OD区202、位于OD区202的部分之上并且围绕OD鳍204的浅沟槽隔离(STI)206的材料、以及位于STI 206和OD鳍204之上的ILD层208。示例性半导体结构还包括伪多晶硅栅极210。
图4中示出了在已经去除伪多晶硅栅极之后的示例性半导体器件。示出了位于OD鳍204的顶面之上的伪IL栅极氧化物212。
图5中示出了在已经实施干和湿蚀刻操作之后的示例性半导体器件。实施干蚀刻和湿蚀刻操作以去除伪IL栅极氧化物212，以去除通过伪多晶硅栅极空出的区域下方的STI 206(由指向下的箭头211标示)以及去除位于ILD层208下方并且邻近OD鳍的侧面的STI 206(由横向箭头213、215标示)，从而在半导体结构中形成T形空隙217。在该实例中，实现1nm至10nm的横向蚀刻。
图6中示出了在金属栅极沉积和抛光之后的示例性半导体器件。示出了具有凸起的鳍204的OD区202、STI 206、ILD层208以及在金属栅极线端中具有T形结构(由椭圆219标示)的金属栅极214。
图7A和图7B是示出对于具有图中指定的宽度和长度比率(W/L)的NMOS和PMOS晶体管的预测的漏致势垒降低(DIBL)相对于阈值电压(Vts)的图。图7A与NMOS晶体管有关，而图7B与PMOS晶体管相关。这些图示出，利用T形栅极结构的晶体管(由方形符号表示)与不利用T形栅极结构的晶体管(由圆形符号表示)相比具有改进的DIBL性能。
图8A和图8B是示出对于具有图中指定的宽度和长度比率(W/L)的NMOS和PMOS晶体管的预测的截止源电流(Isof)相对于饱和电流(Isat)的图。图8A与NMOS晶体管有关，而图8B与PMOS晶体管相关。这些图示出，利用T形栅极结构的晶体管(由方形符号表示)与不利用T形栅极结构的晶体管(由圆形符号表示)相比具有改进的Isof性能。
与在金属栅极线端具有T形结构的晶体管相比，在金属栅极线端中不具有T形结构的平面晶体管可能具有较小的有效OD宽度和较弱的栅极控制能力。通过应用本文中描述的方法，可以使用RPG工艺制造在金属栅极线端中具有T形结构的晶体管。
本文中公开的实例示出了用于获得更大的有效OD宽度和更好的栅极控制能力的方法，并且由此获得更好的器件性能，诸如改进的DIBL和Ion-Isof性能。湿和干蚀刻允许实现1nm至10nm的横向蚀刻并且在金属栅极线端中实现T形栅极结构。
在一个实施例中，公开了一种在半导体器件中制造金属栅极结构的方法。该方法包括：去除伪多晶硅栅极，使用干蚀刻工艺和湿横向蚀刻工艺去除IL氧化物和STI以在半导体器件中形成T形空隙，以及在T形空隙中沉积金属栅极材料以在金属栅极线端中形成T形结构。
这些方面和其他实施例可以包括以下特征中的一个或多个。干和湿横向蚀刻工艺引起1nm至10nm的横向蚀刻。去除伪多晶硅栅极产生保留在OD部分之上的IL氧化物。去除IL氧化物和STI引起OD部分的顶面上的IL氧化物去除以及邻近OD部分的侧面的STI去除。去除IL氧化物和STI引起ILD层的部分下方的STI去除。DIBL性能比在金属栅极线端中未形成T形结构的半导体器件的DIBL性能高。Isof性能比在金属栅极线端中未形成T形结构的半导体器件的Isof性能高。
在另一实施例中，公开了一种制造晶体管的方法。该方法包括制造半导体结构，半导体结构包括具有凸起的鳍的OD区、位于凸起的鳍的侧边上的STI、位于鳍之上的IL氧化物、横跨鳍的伪多晶硅栅极、以及位于伪多晶硅栅极的侧边上的ILD层。该方法还包括：抛光ILD层和伪多晶硅栅极以减小它们的高度，去除伪多晶硅栅极，去除IL氧化物和部分STI以在半导体结构中形成T形空隙，以及在T形空隙中沉积金属栅极材料以在金属栅极线端中形成T形结构。
这些方面和其他实施例可以包括以下特征中的一个或多个。使用干蚀刻工艺和湿横向蚀刻工艺实现去除IL氧化物和STI。干和湿横向蚀刻工艺的性能引起1nm至10nm的横向蚀刻。去除IL氧化物和STI引起OD部分的顶面上的IL氧化物去除以及邻近OD部分的侧面的STI去除。去除IL氧化物和STI引起ILD层的部分下方的STI去除。DIBL性能比在金属栅极线端中未形成T形结构的晶体管的DIBL性能高。Isof性能比在金属栅极线端中未形成T形结构的晶体管的Isof性能高。
在另一实施例中，公开了由包括伪多晶硅栅极的去除的工艺制造的半导体器件。该半导体器件包括OD鳍以及在OD鳍的部分之上制造并且邻近OD鳍的侧部的金属栅极。金属栅极在金属栅极线端中具有T形结构。通过使用干蚀刻工艺和湿横向蚀刻工艺去除IL氧化物和STI以形成T形空隙来形成T形结构。
这些方面和其他实施例可以包括以下特征中的一个或多个。干和湿横向蚀刻工艺引起1nm至10nm的横向蚀刻。所述湿横向蚀刻工艺的应用引起邻近OD鳍的所述侧部的STI去除。所述干蚀刻工艺和所述湿横向蚀刻工艺的应用引起ILD层的部分下方的STI去除。DIBL性能比在金属栅极线端中未形成T形结构的类似的晶体管的DIBL性能高。Isof性能比在金属栅极线端中未形成T形结构的类似的晶体管的Isof性能高。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种在半导体器件中制造金属栅极结构的方法，所述方法包括：
去除伪多晶硅栅极；
使用干蚀刻工艺和湿横向蚀刻工艺去除层间(IL)氧化物和浅沟槽隔离(STI)以在所述半导体器件中形成T形空隙；
在所述T形空隙中沉积金属栅极材料以在金属栅极线端中形成T形结构。
2.根据权利要求1所述的方法，其中，所述干蚀刻工艺和湿横向蚀刻工艺引起1nm至10nm的横向蚀刻。
3.根据权利要求1所述的方法，其中，去除所述伪多晶硅栅极产生保留在氧化扩散(OD)部分之上的IL氧化物。
4.根据权利要求1所述的方法，其中，去除所述IL氧化物和所述STI引起氧化扩散(OD)部分的顶面上的IL氧化物去除以及邻近所述OD部分的侧面的STI去除。
5.根据权利要求1所述的方法，其中，去除所述IL氧化物和所述STI引起层间介电(ILD)层的部分下方的STI去除。
6.根据权利要求1所述的方法，其中，漏致势垒降低(DIBL)性能比在所述金属栅极线端中未形成T形结构的半导体器件的DIBL性能高
7.根据权利要求1所述的方法，其中，截止源电流(Isof)性能比在所述金属栅极线端中未形成T形结构的半导体器件的Isof性能高。
8.一种制造晶体管的方法：
制造半导体结构，所述半导体结构包括具有凸起的鳍的氧化扩散(OD)区、位于所述凸起的鳍的侧边上的浅沟槽隔离(STI)、位于鳍之上的层间(IL)氧化物、横跨鳍的伪多晶硅栅极、以及位于所述伪多晶硅栅极的侧边上的层间介电(ILD)层；
抛光所述ILD层和所述伪多晶硅栅极以减小它们的高度；
去除所述伪多晶硅栅极；
去除所述IL氧化物和部分所述STI以在所述半导体结构中形成T形空隙；以及
在所述T形空隙中沉积金属栅极材料以在金属栅极线端中形成T形结构。
9.根据权利要求8所述的方法，其中，使用干蚀刻工艺和湿横向蚀刻工艺实现去除所述IL氧化物和所述STI。
10.一种由包括伪多晶硅栅极的去除的工艺制造的半导体器件，所述半导体器件包括：
氧化扩散(OD)鳍；以及
金属栅极，在所述OD鳍的部分之上制造并且邻近所述OD鳍的侧部，所述金属栅极在金属栅极线端中具有T形结构；
其中，通过使用干蚀刻工艺和湿横向蚀刻工艺去除层间(IL)氧化物和浅沟槽隔离(STI)以形成T形空隙来形成所述T形结构。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1577850A (zh) * 2003-06-27 2005-02-09 英特尔公司 有部分或全包围栅电极的非平面半导体器件及其制造方法
US20050051843A1 (en) * 2003-09-08 2005-03-10 Satoshi Inaba Semiconductor device and manufacturing method thereof
CN1848455A (zh) * 2005-04-05 2006-10-18 精工电子有限公司 半导体器件及其制造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3962009B2 (ja) * 2003-12-05 2007-08-22 株式会社東芝 半導体装置の製造方法
US7335945B2 (en) * 2003-12-26 2008-02-26 Electronics And Telecommunications Research Institute Multi-gate MOS transistor and method of manufacturing the same
WO2009044236A1 (en) * 2007-10-03 2009-04-09 Freescale Semiconductor, Inc. Method of forming an inverted t shaped channel structure for an inverted t channel field effect transistor device
US8264048B2 (en) * 2008-02-15 2012-09-11 Intel Corporation Multi-gate device having a T-shaped gate structure
US7986042B2 (en) * 2009-04-14 2011-07-26 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
CN102479692B (zh) * 2010-11-30 2014-06-04 中芯国际集成电路制造(北京)有限公司 形成栅极的方法
US9041099B2 (en) * 2011-04-11 2015-05-26 Nanya Technology Corp. Single-sided access device and fabrication method thereof
US8637359B2 (en) * 2011-06-10 2014-01-28 International Business Machines Corporation Fin-last replacement metal gate FinFET process
WO2013080378A1 (ja) * 2011-12-02 2013-06-06 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置の製造方法と半導体装置
CN103377896B (zh) * 2012-04-23 2016-08-31 中芯国际集成电路制造(上海)有限公司 高介电层金属栅器件的制造方法
US8877623B2 (en) * 2012-05-14 2014-11-04 United Microelectronics Corp. Method of forming semiconductor device
US8921218B2 (en) * 2012-05-18 2014-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate finFET device and method of fabricating thereof
US8981496B2 (en) * 2013-02-27 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate and gate contact structure for FinFET

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1577850A (zh) * 2003-06-27 2005-02-09 英特尔公司 有部分或全包围栅电极的非平面半导体器件及其制造方法
US20050051843A1 (en) * 2003-09-08 2005-03-10 Satoshi Inaba Semiconductor device and manufacturing method thereof
CN1848455A (zh) * 2005-04-05 2006-10-18 精工电子有限公司 半导体器件及其制造方法

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