CN105009095B - 混合存储器类型混合高速缓存 - Google Patents

混合存储器类型混合高速缓存 Download PDF

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Publication number
CN105009095B
CN105009095B CN201480013145.3A CN201480013145A CN105009095B CN 105009095 B CN105009095 B CN 105009095B CN 201480013145 A CN201480013145 A CN 201480013145A CN 105009095 B CN105009095 B CN 105009095B
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memory
cache
type
sram
hybrid
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CN105009095A (zh
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X·董
J·徐
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0851—Cache with interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1659—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
    • G11C14/0081—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1028—Power efficiency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20—Employing a main memory using a specific memory technology
    • G06F2212/202—Non-volatile memory
    • G06F2212/2024—Rewritable memory not requiring erasing, e.g. resistive or ferroelectric RAM
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20—Employing a main memory using a specific memory technology
    • G06F2212/205—Hybrid memory, e.g. using both volatile and non-volatile memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/22—Employing cache memory using specific memory technology
    • G06F2212/225—Hybrid cache memory, e.g. having both volatile and non-volatile portions
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2245—Memory devices with an internal cache buffer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Hall/Mr Elements (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CN201480013145.3A 2013-03-15 2014-03-13 混合存储器类型混合高速缓存 Active CN105009095B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/843,190 2013-03-15
US13/843,190 US9304913B2 (en) 2013-03-15 2013-03-15 Mixed memory type hybrid cache
PCT/US2014/025971 WO2014151548A1 (en) 2013-03-15 2014-03-13 Mixed memory type hybrid cache

Publications (2)

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CN105009095A CN105009095A (zh) 2015-10-28
CN105009095B true CN105009095B (zh) 2017-12-05

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US (1) US9304913B2 (https=)
EP (1) EP2972892B1 (https=)
JP (1) JP6154060B2 (https=)
KR (1) KR20150132360A (https=)
CN (1) CN105009095B (https=)
WO (1) WO2014151548A1 (https=)

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EP3265907B1 (en) 2016-03-31 2019-08-21 Hewlett-Packard Enterprise Development LP Data processing using resistive memory arrays
US11977484B2 (en) 2016-07-19 2024-05-07 Sap Se Adapting in-memory database in hybrid memory systems and operating system interface
US10540098B2 (en) 2016-07-19 2020-01-21 Sap Se Workload-aware page management for in-memory databases in hybrid main memory systems
US10698732B2 (en) 2016-07-19 2020-06-30 Sap Se Page ranking in operating system virtual pages in hybrid memory systems
US10387127B2 (en) * 2016-07-19 2019-08-20 Sap Se Detecting sequential access data and random access data for placement on hybrid main memory for in-memory databases
US10452539B2 (en) 2016-07-19 2019-10-22 Sap Se Simulator for enterprise-scale simulations on hybrid main memory systems
US10783146B2 (en) 2016-07-19 2020-09-22 Sap Se Join operations in hybrid main memory systems
US10474557B2 (en) 2016-07-19 2019-11-12 Sap Se Source code profiling for line-level latency and energy consumption estimation
US10437798B2 (en) 2016-07-19 2019-10-08 Sap Se Full system simulator and memory-aware splay tree for in-memory databases in hybrid memory systems
KR102835585B1 (ko) * 2016-11-07 2025-07-18 삼성전자주식회사 데이터 처리 방법 및 디바이스
US10235299B2 (en) 2016-11-07 2019-03-19 Samsung Electronics Co., Ltd. Method and device for processing data
US20180374893A1 (en) * 2017-06-22 2018-12-27 Globalfoundries Singapore Pte. Ltd. Differential sensing cell design for stt mram
US11010379B2 (en) 2017-08-15 2021-05-18 Sap Se Increasing performance of in-memory databases using re-ordered query execution plans
CN111971662B (zh) 2018-04-30 2025-01-21 慧与发展有限责任合伙企业 用于处理数据的设备、方法和系统
US10896707B2 (en) * 2018-12-17 2021-01-19 Arm Limited Selective clock adjustment during read and/or write memory operations
CN118732924B (zh) * 2023-03-28 2025-11-11 华为技术有限公司 一种数据访存方法及片上系统

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JP3092557B2 (ja) * 1997-09-16 2000-09-25 日本電気株式会社 半導体記憶装置
JP3604296B2 (ja) * 1998-01-22 2004-12-22 松下電器産業株式会社 半導体メモリおよびメモリシステム
JP2000339954A (ja) 1999-05-31 2000-12-08 Fujitsu Ltd 半導体記憶装置
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Publication number Publication date
US20140281184A1 (en) 2014-09-18
JP2016515274A (ja) 2016-05-26
JP6154060B2 (ja) 2017-06-28
CN105009095A (zh) 2015-10-28
KR20150132360A (ko) 2015-11-25
EP2972892A1 (en) 2016-01-20
WO2014151548A1 (en) 2014-09-25
US9304913B2 (en) 2016-04-05
EP2972892B1 (en) 2021-04-14

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