CN104979337A - 功率半导体模块 - Google Patents

功率半导体模块 Download PDF

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CN104979337A
CN104979337A CN201510151548.0A CN201510151548A CN104979337A CN 104979337 A CN104979337 A CN 104979337A CN 201510151548 A CN201510151548 A CN 201510151548A CN 104979337 A CN104979337 A CN 104979337A
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亨宁·斯托贝尔-麦尔
克里斯蒂安·爱根
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Danfoss Silicon Power GmbH
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
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    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
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Abstract

本发明公开了一种功率半导体模块(10，10’)，该功率半导体模块包括设置在底板(20)上的至少四个基板(DCB1、DCB2、DCB3、DCB4、DCB5、DCB6)，每个基板都具有用于较高电势的第一连接点(a)和用于较低电势的第二连接点(b)，并且该功率半导体模块包括连接到用于较高电势的第一连接点(a)的第一母线(30)和连接到用于较低电势的第二连接点(b)的第二母线(40)。至少一个基板(DCB4)的连接点(b、a)的次序不同于其它基板(DCB1、DCB2、DCB3、DCB5、DCB6)的连接点(a、b)的次序。

Description

功率半导体模块
技术领域
本发明涉及一种功率半导体模块，该功率半导体模块包括设置在底板上的至少四个基板，所述每个基板具有用于较低电势(或电位)的第一连接点和用于较高电势的第二连接点，并且该功率半导体模块包括连接到用于较低电势的第一连接点的第一母线和连接到用于较高电势的第二连接点的第二母线。
背景技术
例如从DE 10 2006 004 031 B3中已知这样的功率半导体模块。
发明内容
本发明的目的是凭借“主电流流动方向”除减少模块电感之外，还在于改进负载电流的平衡，所述主电流流动方向被通过在每种情况下以相同的次序分接(tapping off)基板上的正电势和负电势均匀地设计。
本发明的目的进一步包括改善用于动态过程的电流分布的平衡，并且特别是在短路的情况下以目标的方式来减少单独的开关的负载。
通过具有权利要求1的特征的功率半导体模块来实现该目的。从属权利要求给出了本发明的有利的构造。
在关于对开始提到的主题的测试中，由于基板的镜像(mirroring)并且因此由于基板上电势分接头(tap)的之前已知次序的改变，因而显而易见的是，由于镜像的基板的布置在过载的情况下或短路的情形中实现了电流平衡的改进。精确地在半电桥电路的特别关键的高侧(high side)上，实现了电流的不均等分布的显著减少，并且因此减少了单独的半导体开关上的过载。
与一般的假设相反，不仅每个基板的单独的电流路径的优化是重要的，而且电流路径与由于功率模块的设计是不平衡的负载电流母线的基本匹配也是重要的。不平衡的母线通常导致负载电流流过在DCB布置的方向上具有主电流流动方向的模块，并且产生了在单独基板上的不同强度的寄生耦合。由于母线上的这些耦合，在动态过程的情况下又产生了电流分布的不平衡。这些可以通过对于单独基板的布置进行目标性的改变而被补偿。在高侧上短路的情况下，可以在没有限制模块的实际功能的情况下显著地减少短路电流，并且因此减小破坏的风险。
附图说明
将参照示例性实施例以及如在随附的附图中所示的特别优选的构造，来更详细地描述本发明，其中：
图1示出了具有特别优选的构造的功率半导体模块的透视图；
图2示出了图1的没有母线的功率半导体模块的平面图；
图3示出了图1的具有母线的功率半导体模块的平面图；
图4示出了已知的功率半导体模块IFX和根据本发明构造的功率半导体模块DSP之间的短路电流水平的比较；
图5示出了在高侧上短路的情况下，从DE 10 2006 004 031 B3已知的功率半导体模块IFX和具有根据本发明的构造的功率半导体模块DSP之间的DCB电流分布的比较；和
图6示出了根据本发明的另一个功率半导体模块的平面图。
具体实施方式
图1示出了具有特别优选的构造的功率半导体模块的透视图。功率半导体模块10具有设置有多个基板和连接到该基板的母线30、40、50的底板20。
可以从在图2中图示的功率半导体模块10的平面图中看到优选地成单行的基板的精确布置，其中为了更清楚的图示已经省略了母线30、40、50。根据本发明，提供了设置在底板20上的至少四个基板DCB1、DCB2、DCB3、DCB4、DCB5、DCB6。此处显示的六个基板DCB1、DCB2、DCB3、DCB4、DCB5、DCB6优选地具有并联连接的半电桥电路，每个基板都具有用于较高电势的第一连接点a和用于较低电势的第二连接点b，其中用于较高电势的连接点a电连接到一个母线30并且用于较低电势的连接点b电连接到另一个母线40。
根据本发明，连接点a、b的次序现在对于所有的基板DCB1、DCB2、DCB3、DCB4、DCB5、DCB6是不相同的，但是被设计成使得至少一个基板(即此处由附图标记“DCB4”所标记的基板)的连接点a、b的次序不同于其它基板DCB1、DCB2、DCB3、DCB5、DCB6的连接点a、b的次序。具体地，基板DCB4的连接点b、a的次序与其它基板的连接点a、b的次序相反，即是是反向的次序。
相应地，如图3的平面图中所示，母线30、40的内部连接的连接次序也不是纯粹地重复的，而是对于由“DCB4”所标记的基板来说偏离了该连接次序。如已知地，母线30、40优选地具有从基板DCB1、DCB2、DCB3、DCB4、DCB5、DCB6引出的外部连接。
现在图4示出了从DE 10 2006 004 031 B3已知的功率半导体模块IFX和根据本发明构造的功率半导体模块DSP之间的短路电流水平的比较。可以在以圆圈标记的交叉点处看到，根据本发明构造的功率半导体模块DSP的高侧上的短路电流水平与已知的模块IFX相比较，被显著地减少。
图5示出了从DE 10 2006 004 031 B3已知的功率半导体模块IFX和根据本发明构造的功率半导体模块DSP之间的DCB电流分布的比较。可以清楚地看到，因为电流峰值的持续时间较短，因此DCB平面上的短路对于根据本发明构造的功率半导体模块10来说较不关键。另外，实现了电流在单独的基板DCB1、DCB2、DCB3、DCB4、DCB5、DCB6之间的显著改进的分布。
最后，图6示出了根据本发明的另一个功率半导体模块10’的平面图，其中仅提供了四个基板DCB1、DCB2、DCB3、DCB4。根据本发明，在这种情况下，基板DCB4的连接点b、a的次序与其它基板DCB1、DCB2、DCB3的连接点a、b的次序不同。

Claims (5)

1.一种功率半导体模块(10、10’)，包括：
-设置在底板(20)上的至少四个基板(DCB1、DCB2、DCB3、DCB4、DCB5、DCB6)，每个基板具有用于较高电势的第一连接点(a)和用于较低电势的第二连接点(b)，和
-连接到用于较高电势的第一连接点(a)的第一母线(30)，和连接到用于较低电势的第二连接点(b)的第二母线(40)，
其特征在于，
至少一个基板(DCB4)的连接点(b、a)的次序与其它基板(DCB1、DCB2、DCB3、DCB5、DCB6)的连接点(a、b)的次序不同。
2.根据权利要求1所述的功率半导体模块(10、10’)，其特征在于，所述至少一个基板(DCB4)的连接点(a、b)的次序与其它基板(DCB1、DCB2、DCB3、DCB5、DCB6)的连接点(a、b)的次序相反。
3.根据前述权利要求中的任一权利要求所述的功率半导体模块(10、10’)，其特征在于，所述母线(30、40)具有从基板(DCB1、DCB2、DCB3、DCB4、DCB5、DCB6)引出的外部连接。
4.根据前述权利要求中的任一权利要求所述的功率半导体模块(10、10’)，其特征在于，所述基板(DCB1、DCB2、DCB3、DCB4、DCB5、DCB6)具有并联连接的半电桥电路。
5.根据前述权利要求中的任一权利要求所述的功率半导体模块(10、10’)，其特征在于，所述基板(DCB1、DCB2、DCB3、DCB4、DCB5、DCB6)被布置成一行。
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CN105895608A (zh) * 2016-05-03 2016-08-24 扬州国扬电子有限公司 一种电极包绝缘层的功率模块

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CN105789193A (zh) * 2016-05-03 2016-07-20 扬州国扬电子有限公司 一种设有绝缘隔板的功率模块
CN105895608A (zh) * 2016-05-03 2016-08-24 扬州国扬电子有限公司 一种电极包绝缘层的功率模块
CN105895608B (zh) * 2016-05-03 2018-07-20 扬州国扬电子有限公司 一种电极包绝缘层的功率模块
CN105789193B (zh) * 2016-05-03 2018-09-28 扬州国扬电子有限公司 一种设有绝缘隔板的功率模块

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