CN104952735A - 具有金属柱的芯片封装结构及其形成方法 - Google Patents

具有金属柱的芯片封装结构及其形成方法 Download PDF

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CN104952735A
CN104952735A CN201410114630.1A CN201410114630A CN104952735A CN 104952735 A CN104952735 A CN 104952735A CN 201410114630 A CN201410114630 A CN 201410114630A CN 104952735 A CN104952735 A CN 104952735A
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metal column
photoresist
dielectric layer
chip
electric connection
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CN201410114630.1A
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CN104952735B (zh
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章国伟
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN201410114630.1A priority Critical patent/CN104952735B/zh
Priority to US14/660,376 priority patent/US9324671B2/en
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Abstract

一种具有金属柱的芯片封装结构及其形成方法。本发明通过在金属柱的底部形成连接于本体的外延部，加大了金属柱的底面积，该底面积为金属柱分别与介电层、以及该介电层暴露的电连接结构的接触面积，从而降低了金属柱底壁单位面积所分担的应力，避免了半导体衬底上的介电层断裂，提高了芯片封装结构的成品率。

Description

具有金属柱的芯片封装结构及其形成方法
技术领域
本发明涉及半导体制造技术领域，尤其涉及一种具有金属柱的芯片封装结构及芯片封装结构的形成方法。
背景技术
在晶圆级芯片封装结构中，首先在晶圆半导体衬底上形成集成电路器件，例如晶体管等，然后在集成电路器件上形成连接上述集成电路器件的金属互连结构，之后在金属互连结构上形成金属焊盘以将其电连接至金属互连结构。之后在金属焊盘上形成焊球，以通过上述焊球将芯片封装结构电连接至印刷电路板（PCB）或将两芯片封装结构电连接。
实际工艺中，在芯片封装结构连接到PCB板或与另一芯片封装结构电连接时，为避免焊球熔化造成封装结构相邻焊垫之间短路，相邻焊垫之间需保持一定间距，这使得焊垫密度变低，进而造成晶圆上器件密度变低。针对上述技术问题，目前行业内越来越多使用金属柱技术，即在焊垫上形成较厚的金属柱（Pillar bump），拉大了两芯片封装结构上对应焊垫之间距离，或PCB板上管脚与芯片封装结构上对应焊垫之间距离，从而使得金属柱上的焊球熔化时，不易流到相邻焊垫上短路，从而提高了晶圆上的器件密度。
然而，上述厚度较大的金属柱容易造成该金属柱应力较大，尤其在高温制程中会造成与其接触的半导体衬底上的介电层断裂，这会造成芯片封装结构可靠性较低，甚至失效。针对上述技术问题，现有技术也有一些解决方案，例如在焊垫上形成聚酰亚胺层作为缓冲层以释放应力，但是这又会加入一道聚酰亚胺的刻蚀工艺，造成成本提高且芯片封装工艺所需时间变长。
有鉴于此，实有必要提出一种新的具有金属柱的芯片封装结构及其形成方法，以较低成本提高芯片封装结构的成品率。
发明内容
本发明实现的目的是以较低成本提高芯片封装结构的成品率。
为实现上述目的，本发明的一方面提供一种具有金属柱的芯片封装结构的形成方法，包括：
提供半导体衬底，具有电连接结构及暴露部分所述电连接结构的介电层；
在所述半导体衬底上形成具有开口的光刻胶，所述开口暴露所述电连接结构及部分介电层，其中，与所述开口底壁相连的光刻胶具有缺口；
电镀以在所述开口及缺口内形成金属柱，所述金属柱包括形成在所述开口内的金属柱本体以及形成在所述缺口内的外延部；
在所述金属柱的顶部形成焊球。
可选地，所述电镀的金属为铜。
可选地，所述电连接结构为焊垫或垫重分布层。
可选地，形成具有开口的光刻胶的方法为：
在所述半导体衬底上旋涂光刻胶，烘焙所述光刻胶；
利用具有开口图形的掩膜板曝光所述光刻胶，显影所述曝光后的光刻胶。
可选地，缺口的形成方法为：烘焙所述光刻胶采用的温度低于正常烘焙温度10℃至50℃，所述正常烘焙温度为85℃～140℃。
可选地，缺口的形成方法为：显影所述曝光后的光刻胶所用的显影时间是正常显影时间的1.2倍至2倍，所述正常显影时间为40s～30min。
本发明的另一方面提供一种具有金属柱的芯片封装结构，包括：
半导体衬底，具有电连接结构及暴露部分所述电连接结构的介电层；
形成在所述电连接结构及介电层表面的金属柱及形成在所述金属柱上的焊球；
其中，所述金属柱包括金属柱本体以及连接于所述金属柱本体底部的外延部，所述金属柱本体分别与所述电连接结构、部分介电层接触，所述外延部与所述介电层接触。
可选地，所述金属柱为铜柱。
可选地，所述电连接结构为焊垫或垫重分布层。
可选地，所述介电层为钝化层。
可选地，所述外延部呈三角形。
与现有技术相比，本发明的技术方案具有以下优点：1）本发明通过在金属柱的底部形成连接于本体的外延部，加大了金属柱的底面积，该底面积为金属柱分别与介电层、以及该介电层暴露的电连接结构的接触面积，从而降低了金属柱底壁单位面积所分担的应力，避免了半导体衬底上的介电层断裂，提高了芯片封装结构的成品率。
2）可选方案中，金属柱可以直接形成在焊垫上，也可以形成在连接焊垫的垫重分布层上，利用垫重分布层对焊垫之间的间距、位置进行重新规划，进一步提高了晶圆上的器件密度。
3）可选方案中，该外延部是通过控制光刻胶烘焙温度，使其坚硬度变低，或延长显影时间，使得曝光后的光刻胶过度显影，上述两种方法都在显影后的光刻胶开口内造成底切（Undercut）现象，该底切现象剥离的光刻胶形成了缺口，从而使得开口的底部面积大于开口顶部的面积，进而使得后续电镀的金属在对应底切缺口的区域形成用以加大金属柱底部面积的外延部。此外，上述光刻胶开口是正常形成金属柱的一道工艺，因而上述方案通过控制光刻胶的形状以较低成本提高了封装结构的成品率。
附图说明
图1至图2是本发明一个实施例的芯片封装结构在制作过程中的结构示意图；
图3是图1至图2制作完成后的芯片封装结构的示意图；
图4至图5是本发明另一个实施例的芯片封装结构在制作过程中的结构示意图；
图6是图4至图5制作完成后的芯片封装结构的示意图。
具体实施方式
如背景技术中所述，由于金属柱较厚，因而应力较大，这造成现有的具有金属柱的芯片封装结构易出现与金属柱接触的介电层断裂的问题，上述问题进而会造成封装结构可靠性降低、成品率低。针对上述问题，本发明通过在金属柱的底部形成连接于本体的外延部，加大了金属柱的底面积，该底面积为金属柱分别与介电层、以及该介电层暴露的电连接结构的接触面积，从而降低了金属柱底壁单位面积所分担的应力，避免了半导体衬底上的介电层断裂，提高了芯片封装结构的成品率。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图1至图2是本发明一个实施例的芯片封装结构在制作过程中的结构示意图。图3是图1至图2制作完成后的芯片封装结构的示意图。以下结合图1至图3，详细介绍具有金属柱的芯片封装结构的一种形成方法及形成的芯片封装结构。
首先介绍形成方法。参照图1所示，首先，提供半导体衬底1，该半导体衬底1具有焊垫12及暴露部分所述焊垫12的介电层13。
该焊垫12用于将半导体衬底1上的器件（未图示），例如晶体管的电信号通过金属互连结构11引出。
此外，考虑到防水、防污染等因素，该介电层13优选为钝化层，材质例如为氮化硅等。
接着，参照图2所示，在半导体衬底1（参照图1所示）上形成具有开口15的光刻胶14，该开口15暴露所述焊垫12及部分介电层13，其中，与该开口15底壁相连的光刻胶14具有缺口16。
图案化光刻胶的方法为现有的方案。例如：首先在半导体衬底1上旋涂光刻胶，烘焙所述光刻胶；接着利用具有开口15图形的掩膜板曝光所述光刻胶，显影所述曝光后的光刻胶。
具体地，形成缺口16方法为：（a）控制烘焙光刻胶所用的温度低于正常烘焙温度10℃至50℃，所述正常烘焙温度为85℃～140℃；（b）显影所述曝光后的光刻胶所用的显影时间是正常显影时间的1.2倍至2倍，所述正常显影时间为40s～30min。（a）通过控制光刻胶烘焙温度，使其坚硬度变低，或（b）延长显影时间，使得曝光后的光刻胶过度显影，上述两种方法都在显影后的光刻胶开口15内造成底切（Undercut）现象，该底切现象剥离的光刻胶形成了缺口16，上述缺口16使得开口15的底部面积大于开口顶部的面积。
之后，参照图3所示，电镀以在所述开口15内形成金属柱17，所述金属柱17包括形成在所述开口15（参照图2所示）内的本体171以及形成在所述缺口16（参照图2所示）内的外延部172。
可以看出，缺口16使得电镀的金属在对应底切的区域形成用以加大金属柱17底部面积的外延部172，该底面积为金属柱17分别与介电层13、以及该介电层13暴露的焊垫12的接触面积，上述方案降低了金属柱17底壁单位面积所分担的金属柱应力，避免了半导体衬底上的介电层13断裂，提高了芯片封装结构的成品率。
此外，上述光刻胶开口15是正常形成金属柱的一道工艺，因而上述方案通过控制光刻胶的形状以较低成本提高了封装结构的成品率。
具体地，上述电镀的金属可以为铜，即金属柱17为铜金属柱。
之后，仍参照图3所示，在所述金属柱17的顶部形成焊球18。
本实施例中，灰化去除光刻胶14后，利用现有工艺在金属柱17的顶部形成焊球18。
至此，本实施例形成了一种具有金属柱的芯片封装结构，参照图3所示，该封装结构包括：
半导体衬底，具有焊垫12及暴露部分所述焊垫12的介电层13；
形成在所述焊垫12及介电层13表面的金属柱17及形成在金属柱17上的焊球18；
其中，所述金属柱17包括金属柱本体171以及连接于所述金属柱本体171底部的外延部172，所述金属柱本体171分别与所述焊垫12、部分介电层13接触，所述外延部172与所述介电层13接触。
具体地，该外延部172呈三角形。其它实施例中，该外延部172也可以根据底切造成的光刻胶剥离情况，为其它不规则结构，能实现增大金属柱17底部面积即可。
图4至图5是本发明另一个实施例的芯片封装结构在制作过程中的结构示意图。图6是图4至图5制作完成后的芯片封装结构的示意图。以下结合图4至图6，介绍另一种形成具有金属柱的芯片封装结构的方法及形成的芯片封装结构。
与图1至图3中的形成方法不同的是，参照图4所示，半导体衬底上具有垫重分布层20。该垫重分布层20通过金属互连结构19与焊垫12电连接，垫重分布层20可以根据实际需求对焊垫12之间的间距、位置进行重新规划，从而进一步提高晶圆上的器件密度。
该垫重分布层20被介电层13包埋，且该介电层13暴露部分垫重分布层20的表面。
相应地，参照图5所示，在半导体衬底上形成具有开口15的光刻胶14时，该开口15暴露垫重分布层20及部分介电层13。其中，与该开口15底壁相连的光刻胶14具有缺口16。
参照图6所示，电镀以在所述开口15内形成金属柱17时，所述金属柱17的底部与所述垫重分布层20及部分介电层13接触。其中，金属柱17包括形成在所述开口15内的本体171以及形成在所述缺口16内的外延部172。
之后，如前述实施例中描述，灰化去除光刻胶14后，利用现有工艺在金属柱17的顶部形成焊球18。
本发明中，各实施例采用递进式写法，重点描述与前述实施例的不同之处，各实施例中的相同结构及结构的形成方法参照前述实施例的相同部分。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (11)

1.一种具有金属柱的芯片封装结构的形成方法，其特征在于，包括：
提供半导体衬底，具有电连接结构及暴露部分所述电连接结构的介电层；
在所述半导体衬底上形成具有开口的光刻胶，所述开口暴露所述电连接结构及部分介电层，其中，与所述开口底壁相连的光刻胶具有缺口；
电镀以在所述开口及缺口内形成金属柱，所述金属柱包括形成在所述开口内的金属柱本体以及形成在所述缺口内的外延部；
在所述金属柱的顶部形成焊球。
2.根据权利要求1所述的形成方法，其特征在于，所述电镀的金属为铜。
3.根据权利要求1所述的形成方法，其特征在于，所述电连接结构为焊垫或垫重分布层。
4.根据权利要求1所述的形成方法，其特征在于，形成具有开口的光刻胶的方法为：
在所述半导体衬底上旋涂光刻胶，烘焙所述光刻胶；
利用具有开口图形的掩膜板曝光所述光刻胶，显影所述曝光后的光刻胶。
5.根据权利要求4所述的形成方法，其特征在于，缺口的形成方法为：烘焙所述光刻胶采用的温度低于正常烘焙温度10℃至50℃，所述正常烘焙温度为85℃～140℃。
6.根据权利要求4所述的形成方法，其特征在于，缺口的形成方法为：显影所述曝光后的光刻胶所用的显影时间是正常显影时间的1.2倍至2倍，所述正常显影时间为40s～30min。
7.一种具有金属柱的芯片封装结构，包括：
半导体衬底，具有电连接结构及暴露部分所述电连接结构的介电层；
形成在所述电连接结构及介电层表面的金属柱及形成在所述金属柱上的焊球；
其特征在于，所述金属柱包括金属柱本体以及连接于所述金属柱本体底部的外延部，所述金属柱本体分别与所述电连接结构、部分介电层接触，所述外延部与所述介电层接触。
8.根据权利要求7所述的芯片封装结构，其特征在于，所述金属柱为铜柱。
9.根据权利要求7所述的芯片封装结构，其特征在于，所述电连接结构为焊垫或垫重分布层。
10.根据权利要求7所述的芯片封装结构，其特征在于，所述介电层为钝化层。
11.根据权利要求7所述的芯片封装结构，其特征在于，所述外延部呈三角形。
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