CN104943395A - Operation instruction generation circuit and consumable chip - Google Patents
Operation instruction generation circuit and consumable chip Download PDFInfo
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- CN104943395A CN104943395A CN201510317365.1A CN201510317365A CN104943395A CN 104943395 A CN104943395 A CN 104943395A CN 201510317365 A CN201510317365 A CN 201510317365A CN 104943395 A CN104943395 A CN 104943395A
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- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims abstract description 32
- 238000004146 energy storage Methods 0.000 claims description 22
- 238000013500 data storage Methods 0.000 claims description 12
- 230000005540 biological transmission Effects 0.000 claims description 8
- 238000003384 imaging method Methods 0.000 abstract description 32
- 238000007639 printing Methods 0.000 abstract description 23
- 230000009471 action Effects 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 239000000549 coloured material Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
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- 239000000428 dust Substances 0.000 description 1
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/109—Control signal input circuits
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/17—Ink jet characterised by ink handling
- B41J2/175—Ink supply systems ; Circuit parts therefor
- B41J2/17503—Ink cartridges
- B41J2/17543—Cartridge presence detection or type identification
- B41J2/17546—Cartridge presence detection or type identification electronically
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M11/00—Coding in connection with keyboards or like devices, i.e. coding of the position of operated keys
- H03M11/22—Static coding
- H03M11/24—Static coding using analogue means, e.g. by coding the states of multiple switches into a single multi-level analogue signal or by indicating the type of a device using the voltage level at a specific tap of a resistive divider
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Accessory Devices And Overall Control Thereof (AREA)
- Read Only Memory (AREA)
- Ink Jet (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses an operation instruction generation circuit and a consumable chip, wherein the operation instruction generation circuit comprises a power-on initializing module connected with a signal wire and used for generating an initializing signal according to a signal transmitted by the signal wire, a middle signal generation module connected with the power-on initializing module and the signal wire and used for combining with the signal transmitted by the signal wire to generate a middle signal according to the initializing signal, and an instruction generation module connected with the power-on initializing module and the middle signal generation module and used for generating an operation instruction according to the initializing signal and the middle signal or according to the initializing signal, the middle signal and the signal transmitted by the signal wire. The operation instruction generation circuit can accurately judge the intention of printing imaging equipment according to the type of the signal transmitted in the signal wire ID so as to help the consumable chip to timely and accurately respond to actions of the printing imaging equipment.
Description
the cross reference of correlation technique
This application claims the name enjoying submission on November 28th, 2014 to be called: the priority of the Chinese patent application CN201410715520.0 of " a kind of signal source identification circuit and the consumable chip comprising this circuit ", its full content is incorporated herein by reference.
Background technology
Equipment for being printed as picture is diversified, and now widely used printing imaging device mainly comprises: ink-jet printer, laser printer, LED printer, impact printer and thermal printer etc.In print procedure, print imaging device and can consume the coloured material such as ink, carbon dust, these coloured materials are often placed in consumption material box to supplement easily and to change.
In order to record the information such as source, service condition of consumption material box, the consumable chip that can record these information electronically is just set on consumption material box.Like this, when the coloured material of user in consumption material box runs out of, supplementary coloured material can be carried out by changing consumption material box.Printing imaging device reads the information on consumable chip electronically, just in time, automatically can upgrade the state printing imaging device, and manually input the information such as type, date of manufacture of consumption material box without the need to user.
Existing part prints imaging device and reads information on consumable chip by connected mode as shown in Figure 1 or to written information in consumable chip.As shown in Figure 1, in printing imaging device, current source 101 and voltage source 102 is provided with respectively.Wherein, the output voltage of voltage source 102 is 16V, and drive current is greater than 10mA; The drive current of current source 101 is 1mA, and ceiling voltage amplitude is 15V.Under the control of controller 103, output current source signal or voltage source signal can be switched on holding wire ID through change-over switch 103.
Holding wire ID is connected to consumable chip 105.When printing imaging device when performing read operation, printing the signal that exports to holding wire ID on of imaging device is current source signal, and the voltage utilizing ADC106 to come on signal lines ID, thus the reading of realization to the data that consumable chip stores.When printing imaging device when performing write operation, the signal that printing imaging device exports on holding wire ID is voltage source signal, so that data to be written are write consumable chip.
But how consumable chip accurately judges to print that imaging device needs to carry out is that read operation or this problem of write operation are not solved well according to the signal on holding wire ID, thus causes consumable chip to occur responding the problem of mistake.
Technical field
The present invention relates to printing technical field of imaging, specifically, relate to a kind of operational order generative circuit and consumable chip.
Summary of the invention
For solving the problem, the invention provides a kind of operational order generative circuit, described circuit comprises:
Power-up initializing module, it is connected with holding wire, produces initializing signal for the signal transmitted according to described holding wire;
M signal generation module, it is connected with described power-up initializing module and described holding wire, and it, for according to described initializing signal, in conjunction with the signal of described holding wire transmission, generates M signal;
Directive generation module, it is connected with described power-up initializing module and M signal generation module, for according to described initializing signal and M signal, or according to the signal of described initializing signal, M signal and holding wire transmission, generating run instruction.
According to one embodiment of present invention,
When the signal that described holding wire transmits is current source signal, described M signal is high level signal or low level signal;
When the signal that described holding wire transmits is voltage source signal, described M signal is low level signal or high level signal.
According to one embodiment of present invention, described power-up initializing module comprises the first phase inverter and the first energy-storage units, the input of described first phase inverter is connected with described holding wire by resistance, between the input that described first energy-storage units is connected to described first phase inverter and earth terminal.
According to one embodiment of present invention, described first energy-storage units comprises electric capacity or transistor.
According to one embodiment of present invention, described M signal generation module comprises the first signal generation unit, latch and the second phase inverter, described latch and the first signal generation unit and power-up initializing model calling, described second phase inverter is connected with described latch.
According to one embodiment of present invention, described first signal generation unit comprises:
First switch, its control end is connected with holding wire by the first resistance, and the first external connection end is connected with described holding wire by the second resistance,
Second switch, its control end is connected with the output of described M signal generation module, and the first external connection end is connected with the control end of described first switch by the 3rd resistance, and the second external connection end is connected with the second external connection end of described first switch,
Be connected with the second energy-storage units between the control end of described first switch and its second external connection end, between the first external connection end of described first switch and its second external connection end, be connected with the 3rd energy-storage units.
According to one embodiment of present invention,
When the signal that described holding wire transmits is current source signal, described 3rd ohmically voltage is less than the cut-in voltage of described first switch;
When the signal that described holding wire transmits is voltage source signal, described 3rd ohmically voltage is more than or equal to the cut-in voltage of described first switch.
According to one embodiment of present invention, described directive generation module comprises:
First and door, described first is connected with described holding wire with the first input end of door, and the second input is connected with described M signal generation module; And/or,
First nor gate and second and door, the first input end of described first nor gate is connected with described power-up initializing module and M signal generation module respectively with the second input, and described second is connected with described holding wire and the first nor gate respectively with the first input end of door and the second input.
Present invention also offers a kind of consumable chip, it is characterized in that, described consumable chip comprises:
As above the operational order generative circuit described in any one;
Data storage circuitry, it, for the operational order exported according to described operational order generative circuit, carries out the storage of data or the output of data.
Control command generative circuit provided by the present invention can accurately judge according to the signal type transmitted in holding wire ID the intention printing imaging device.That is, when transmit in holding wire ID for current source signal time, operational order generative circuit can generate exactly and read instruction; When transmit in holding wire ID for voltage source signal time, operational order generative circuit can generate write command exactly.Contribute to like this consumable chip in time, exactly response print the action of imaging device.
Simultaneously, the nonvolatile memory (such as flash memory) of easy rewriting is not directly applied for the printing imaging device conducted interviews with voltage source and current source, operational order generative circuit provided by the present invention then can generate corresponding operational order (such as reading instruction and write command) according to power supply source signal or current source signal, thus makes the nonvolatile memory of this easy rewriting be able to install and use in printing imaging device.
Other features and advantages of the present invention will be set forth in the following description, and, partly become apparent from description, or understand by implementing the present invention.Object of the present invention and other advantages realize by structure specifically noted in description, claims and accompanying drawing and obtain.
Accompanying drawing explanation
Accompanying drawing shows the various embodiments of each aspect of the present invention, and they and description one are used from and explain principle of the present invention.Those skilled in the art understand, specific embodiment shown in the drawings is only exemplary, and they are not intended to limit the scope of the invention.Should be realized that, in some examples, the element be illustrated also can be designed as multiple element, or multiple element also can be designed as an element.In some examples, the element being shown as the internal part of another element also may be implemented as the external component of this another element, and vice versa.In order to clearly, in detail exemplary embodiment of the present invention understand more thorough to enable the advantage of those skilled in the art to each aspect of the present invention and feature thereof, existing accompanying drawing to be introduced, in the accompanying drawings:
Fig. 1 is the annexation schematic diagram of existing printing imaging device and consumable chip;
Fig. 2 is the structural representation of consumable chip according to an embodiment of the invention;
Fig. 3 is the structural representation of operational order generative circuit according to an embodiment of the invention;
Fig. 4 is the circuit theory diagrams of operational order generative circuit according to an embodiment of the invention;
Fig. 5 is the circuit theory diagrams of operational order generative circuit according to an embodiment of the invention;
Fig. 6 is the circuit theory diagrams of operational order generative circuit according to an embodiment of the invention.
Detailed description of the invention
Describe embodiments of the present invention in detail below with reference to drawings and Examples, to the present invention, how application technology means solve technical problem whereby, and the implementation procedure reaching technique effect can fully understand and implement according to this.It should be noted that, only otherwise form conflict, each embodiment in the present invention and each feature in each embodiment can be combined with each other, and the technical scheme formed is all within protection scope of the present invention.
Meanwhile, in the following description, many details have been set forth for illustrative purposes, to provide thorough understanding of embodiments of the invention.But, it will be apparent to those skilled in the art that the present invention can detail here or described ad hoc fashion implement.
The invention provides a kind of new consumable chip, this consumable chip is applicable to the printing imaging device being visited consumable chip data by voltage source and current source.Fig. 2 shows the structural representation of the consumable chip that the present embodiment provides.
As shown in Figure 2, the consumable chip that the present embodiment provides comprises: operational order generative circuit 201, data storage circuitry 202.Particularly, what operational order generative circuit 201 transmitted for identification signal line ID is voltage source signal or current source signal, and namely printing what be connected with holding wire ID in imaging device is voltage source or current source.If what holding wire ID transmitted is voltage source signal, operational order generative circuit 201 exports write command WR; If what holding wire ID transmitted is current source signal, instruction RD is read in 201 outputs of operational order generative circuit.
In the present embodiment, operational order generative circuit 201 comprises one for receiving the input of the signal transmitted in ID holding wire, and two outputs.These two outputs are respectively reads instruction output end RD and write command output WR, and therefore operational order generative circuit is in the present embodiment also referred to as RD/WR identification circuit.
Data storage circuitry 202 and operational order generative circuit 201 read instruction output end RD and write command output WR is connected.Data storage circuitry 202 can adopt easily programming and erasable memory (such as EEPROM, ferroelectric memory, phase transition storage or flash memory etc.), but or is that the combination (SRAM etc. of such as charged pool) of volatile memory and power supply is as memory cell.Data storage circuitry 202 reads instruction or write command according to what receive, and the address information received (transmission path of not shown address information), performs digital independent or data write operation to the destination address of data storage circuitry 202.
In the present embodiment, the information stored in data storage circuitry 202 comprises: the information such as consumption material box identifying information, manufacturer, date of manufacture, used ink amount, ink remaining amount and toner color.Certainly, in other embodiments of the invention, the information stored in data storage circuitry 202 both can be only the subitem in above lising, and can be also other unlisted appropriate messages, the present invention is not limited thereto.
What read instruction output end RD and write command output WR output is high level or low level.In the present embodiment, be defined as useful signal by during output high level.When so reading instruction output end RD output high level, it is effective that instruction is read in expression; When write command output WR exports high level, represent that write command is effective.
Namely or be that to read instruction effective the useful signal exported due to operational order generative circuit 201 only has two kinds, or is that write command is effective.Therefore, in other embodiments of the invention, also can be inner at operational order generative circuit 201, these two outputs are integrated into an output.Such as, when output is high level, write command is defined as effective; And output is when being low level, be defined as that to read instruction effective.Like this, correspondingly, data storage circuitry 202 also just only needs an input port to receive read write command, and receives respectively read instruction and write command without the need to arranging two ports.So not only be conducive to the circuit structure of reduced data memory circuit, also reasonable reduced data memory circuit is to the analyzing and processing process of read write command, thus improves the read-write efficiency of data.
When operational order generative circuit 201 is when reading instruction output end RD and exporting high level, then represent that printing imaging device needs to read the data stored in consumable chip.Print imaging device and read data by the voltage gathering ID holding wire.Now, the data storage circuitry 202 of consumable chip is according to the address information received, the data of destination address in data storage circuitry 202 being outputted on holding wire ID, reading by the data of collection signal line ID the information that corresponding address in consumable chip stores for printing imaging device.
As previously mentioned, the consumable chip that the present embodiment provides judges to print the intention of imaging device by the signal that holding wire ID exports.When the signal that holding wire ID transmits is current source signal, consumable chip then judges to print that imaging device will perform is read operation; And when the signal that holding wire ID transmits is voltage source signal, consumable chip then judges to print that imaging device will perform is write operation (such as programming operation etc.).For this reason, operational order generative circuit is as shown in Figure 3 present embodiments provided.
The control command generative circuit 201 that the present embodiment provides comprises two main parts and relevant peripheral circuit, a main part is power-up initializing module 301, the circuit that another main part is made up of M signal generation module 302 and directive generation module 303.
Power-up initializing module 301 is connected with holding wire ID, and it can produce initializing signal according to the signal of holding wire transmission, and this initializing signal is transferred to M signal generation module 302 and directive generation module 303.M signal generation module 302 is connected with power-up initializing module and holding wire ID, and it according to the signal transmitted in initializing signal and holding wire ID, can produce M signal.Directive generation module 303 is connected with power-up initializing module 301, M signal generation module 302 and holding wire ID, and it is according to the signal generating run instruction of initializing signal, M signal and holding wire ID transmission.In the present embodiment, the operational order that operational order generative circuit 201 generates comprises reads instruction and write command.
Fig. 4 shows the physical circuit schematic diagram of the operational order generative circuit that the present embodiment provides.
As shown in Figure 4, in the present embodiment, power-up initializing module 301 comprises resistance R1, as the transistor T1 of the first energy-storage units and the first phase inverter of being made up of transistor T2 and transistor T3.Power-up initializing module 301 can produce initializing signal according to the signal of holding wire transmission.
It should be noted that, in other embodiments of the invention, the first energy-storage units and/or the first phase inverter can also adopt other rational components and parts or circuit to realize, and the present invention is not limited thereto.Such as, in one embodiment of the invention, electric capacity can be adopted to be used as the first energy-storage units.
M signal generation module 302 comprises the first signal generation unit 302a, latch 302b and the second phase inverter J3.Wherein, the input of latch 302b is respectively with the first signal generation unit 302a with power-up initializing module 301 is corresponding connects, the input of the second phase inverter J3 is connected with the output of latch 302b, and the output of the second phase inverter J3 simultaneously and instruction generation module 303 is connected with the first signal generation unit 302a.
Particularly, as shown in Figure 4, the first signal generation unit 302a comprise the first resistance R2 of being connected in series and the 3rd resistance R3, the phase inverter be made up of the first switch T4 and the second resistance R4, rise feedback effect second switch T6, as the transistor T5 of the second energy-storage units and the transistor T7 as the 3rd energy-storage units.First signal generation unit 302a exports the first signal Vr.
In the present embodiment, the first switch T4 and second switch T6 all adopts transistor to realize.Certainly, in other embodiments of the invention, the first switch, second switch, the second energy-storage units and/or the 3rd energy-storage units can also adopt other rational components and parts or circuit to realize, and the present invention is not limited thereto.
The control end (i.e. grid) of the first switch (i.e. transistor T4) is connected with holding wire ID by the second resistance R2, its first external connection end (i.e. source electrode) is connected with holding wire ID by the second resistance R4, and the second external connection end (namely draining) is connected with ground Vss.The control end (i.e. grid) of second switch (i.e. transistor T6) is connected with the output of M signal generation module, first external connection end (i.e. source electrode) is connected with the control end of the first switch by the 3rd resistance R3, and the second external connection end (namely draining) is connected with ground Vss.
Between the control end that second energy-storage units is connected to the first switch T4 and the second external connection end, between the first external connection end that the 3rd energy-storage units is connected to the first switch T4 and the second external connection end.Particularly, in the present embodiment, the grid as the transistor T5 of the second energy-storage units is connected with the control end of the first switch T4, and its source electrode and drain electrode are all connected with ground Vss.Grid as the transistor T7 of the 3rd energy-storage units is connected with first external connection end of the first switch T4, and its source electrode and drain electrode are all connected with ground Vss.
It should be noted that, in other embodiments of the invention, other rational circuit forms or components and parts (such as electric capacity etc.) can also be adopted to replace transistor T5 and/or transistor T7 as energy-storage units, the present invention is not limited thereto.
In the present embodiment, directive generation module 303 comprises first and door J7, the first nor gate J4 and second and door J5.Wherein, first is connected with holding wire ID with the first input end of door J7, and the second input is connected with the output of the second phase inverter J3.The first input end of the first nor gate J4 is connected with the output of power-up initializing module 301 and the second phase inverter J3 respectively with the second input, and second is connected with the output of holding wire ID and the first nor gate J4 respectively with the first input end of door J5 and the second input.
Initializing signal POR and the first signal Vr outputs to the SR latch be made up of nor gate J1 and nor gate J2 respectively, and the output of this latch exports M signal Vc after the second phase inverter (i.e. not gate J3) negate.M signal Vc mono-aspect is transferred to the grid of transistor T6, outputs to two inputs of the first nor gate J4 on the other hand together with initializing signal POR respectively.Second receives the output of the first nor gate J4 and the signal of holding wire ID respectively with two inputs of door J5, exports read instruction at output RD.On the other hand, first distinguishes signal and the M signal Vc of Received signal strength line ID with two inputs of door J7, and exports write command at output WR.
Wherein, resistance R3 should meet: when holding wire ID transmit signal be current source signal time, transistor T6 conducting time, the dividing potential drop of current source on resistance R3 does not reach the cut-in voltage of transistor T4; When the signal that holding wire ID transmits is voltage source signal, transistor T6 conducting, the dividing potential drop of voltage source on resistance R3 reaches or exceedes the cut-in voltage of transistor T5.
When the signal that holding wire ID transmits just has been transferred to operational order generative circuit, operational order generative circuit can carry out power-up initializing.Particularly, when the signal that holding wire ID transmits just has outputted to operational order generative circuit, the effect played due to transistor T5 has been equal to electric capacity, and the signal that therefore holding wire ID transmits can charge to transistor T5.Now the grid of transistor T4 is low level, and such transistor T4 does not just have conducting.In like manner, the effect played due to transistor T7 is equal to electric capacity equally, and the first signal Vr that therefore now the first signal generation unit 302a exports is low level signal.
In like manner, when the signal that holding wire ID transmits just has been transferred to operational order generative circuit, the signal that holding wire ID transmits charges to the transistor T1 playing electric capacity effect through resistance R1, guarantees that the signal that the phase inverter be made up of transistor T2 and transistor T3 receives when just starting is low level signal.This phase inverter just can export the initializing signal POR of high level like this.
Because the first signal Vr is low level, initializing signal POR is high level, and the initial output low level signal of the SR latch be therefore now made up of nor gate J1 and nor gate J2 to not gate J3, thus makes M signal Vc be high level in the starting stage.
When the transistor T1 playing electric capacity effect be charged to be enough to turn-on transistor T3 time, initializing signal POR then through transistor T3 discharge and return to low level.Meanwhile, because M signal Vc is high level, transistor T6 is by conducting.
What operational order generative circuit 201 transmitted for identification signal line ID is voltage source signal or current source signal, and namely printing what be connected with holding wire ID in imaging device is voltage source or current source.If what holding wire ID transmitted is voltage source signal, operational order generative circuit 201 exports write command WR; If what holding wire ID transmitted is current source signal, instruction RD is read in 201 outputs of operational order generative circuit.
In order to clearly set forth the object of invention, principle and advantage, just how operational order generative circuit 201 being generated write command WR according to voltage source signal and how being generated according to current source signal below and reading instruction and set forth further.
If the signal that holding wire ID transmits is current source signal, in the present embodiment, suppose that the drive current of current source is 1mA, ceiling voltage amplitude is 15V, and the cut-in voltage of transistor T4 is 1.5V, then the resistance of resistance R3 should be less than 1.5k Ω.
After initialization completes, transistor T6 conducting.Resistance due to resistance R3 is less than 1.5k Ω, and the electric current flowing through resistance R3 is 1mA, and the dividing potential drop (being less than 1.5V) therefore on resistance R3 will be not enough to turn-on transistor T4.And at this moment, the transistor T7 playing electric capacity effect has completed charging, such first signal Vr will be high level signal.
Meanwhile, because initializing signal POR reverts to low level, so now the output signal of latch 302b becomes high level, and the M signal Vc of phase inverter J3 output is then low level.Because initializing signal POR and M signal Vc is low level simultaneously, the signal that therefore nor gate J4 exports is high level signal.Easily learn, now read instruction output end RD and export high level, and write command output WR output low level.These two combinations exported represent that to read instruction effective.
If the signal that holding wire ID transmits is voltage source signal, in the present embodiment, suppose that the output voltage of voltage source is 16V, drive current is greater than 10mA, the cut-in voltage of transistor T4 is 1.5V, then the ratio dividing potential drop that should meet on resistance R3 of resistance R3 and R2 is greater than in 1.5V (such as resistance R3 value 1k Ω, resistance R2 value 3k Ω).
After initialization completes, transistor T6 conducting, the dividing potential drop on resistance R3 is 4V, and this voltage is greater than the cut-in voltage of transistor T4, therefore now transistor T4 conducting.During transistor T4 conducting, the transistor T7 playing electric capacity effect can discharge through transistor T4, thus makes the first signal Vr return to low level.
Because now initializing signal POR and the first signal Vr is low level simultaneously, therefore M signal Vc will maintain high level, and nor gate J4 is by output low level signal.Easily learn, read instruction output end RD by output low level signal, and write command output WR will export high level signal, and these two combinations exported represent that write command is effective.
Certainly, in other embodiments of the invention, when the signal that also can transmit at holding wire ID is current source signal, export the M signal Vc of high level, when the signal that holding wire ID transmits is current source signal, the M signal Vc of output low level, the present invention is not limited thereto.At this moment, command generating circuit then exports high level signal and at write command output WR output low level signal according to the M signal Vc of high level reading instruction output end RD.
Namely or be that to read instruction effective the useful signal exported due to operational order generative circuit 201 only has two kinds, or is that write command is effective.Therefore, in other embodiments of the invention, also can be inner at operational order generative circuit 201, these two outputs are integrated into an output.This structure is conducive to the simplification to operational order generative circuit, thus reduces volume and the cost of circuit.
Such as, in one embodiment of the invention, operational order generative circuit can adopt circuit structure as shown in Figure 5, and the high level signal that this circuit exports represents reads instruction, and the low level signal of output is at expression write command.And in another embodiment of the present invention, operational order generative circuit can adopt circuit structure as shown in Figure 6, the high level signal that this circuit exports represents write command, and the low level signal of output reads instruction in expression.
As can be seen from foregoing description, the control command generative circuit that the present embodiment provides can accurately judge according to the signal type transmitted in holding wire ID the intention printing imaging device.That is, when transmit in holding wire ID for current source signal time, operational order generative circuit can generate exactly and read instruction; When transmit in holding wire ID for voltage source signal time, operational order generative circuit can generate write command exactly.Contribute to like this consumable chip in time, exactly response print the action of imaging device.
Simultaneously, the nonvolatile memory (such as flash memory) of easy rewriting is not directly applied for the printing imaging device conducted interviews with voltage source and current source, the operational order generative circuit that the present embodiment provides then can generate corresponding operational order (such as reading instruction and write command) according to power supply source signal or current source signal, thus makes the nonvolatile memory of this easy rewriting be able to install and use in printing imaging device.
It should be understood that disclosed embodiment of this invention is not limited to ad hoc structure disclosed herein, treatment step or material, and the equivalent of these features that those of ordinary skill in the related art understand should be extended to substitute.It is to be further understood that term is only for describing the object of specific embodiment as used herein, and and do not mean that restriction.
Special characteristic, structure or characteristic that " embodiment " mentioned in description or " embodiment " mean to describe in conjunction with the embodiments comprise at least one embodiment of the present invention.Therefore, description various places throughout occur phrase " embodiment " or " embodiment " might not all refer to same embodiment.
Conveniently, multiple project, construction module and/or comprising modules can appear in common list as used herein.But each element that these lists should be interpreted as in this list is identified as member unique separately respectively.Therefore, when not having reverse side to illustrate, in this list, neither one member only can appear in common list the actual equivalent of other member any being just interpreted as same list based on them.In addition, can also come together with reference to various embodiment of the present invention and example together with for the alternative of each element at this.Should be understood that, these embodiments, example and substitute and be not interpreted as equivalent each other, and be considered to representative autonomous separately of the present invention.
Although above-mentioned example is for illustration of the principle of the present invention in one or more application, but for a person skilled in the art, when not deviating from principle of the present invention and thought, obviously can in form, the details of usage and enforcement does various amendment and need not creative work be paid.Therefore, the present invention is limited by appending claims.
Claims (9)
1. an operational order generative circuit, is characterized in that, described circuit comprises:
Power-up initializing module, it is connected with holding wire, produces initializing signal for the signal transmitted according to described holding wire;
M signal generation module, it is connected with described power-up initializing module and described holding wire, and it, for according to described initializing signal, in conjunction with the signal of described holding wire transmission, generates M signal;
Directive generation module, it is connected with described power-up initializing module and M signal generation module, for according to described initializing signal and M signal, or according to the signal of described initializing signal, M signal and holding wire transmission, generating run instruction.
2. circuit as claimed in claim 1, is characterized in that,
When the signal that described holding wire transmits is current source signal, described M signal is high level signal or low level signal;
When the signal that described holding wire transmits is voltage source signal, described M signal is low level signal or high level signal.
3. circuit as claimed in claim 1, it is characterized in that, described power-up initializing module comprises the first phase inverter and the first energy-storage units, the input of described first phase inverter is connected with described holding wire by resistance, between the input that described first energy-storage units is connected to described first phase inverter and earth terminal.
4. circuit as claimed in claim 3, it is characterized in that, described first energy-storage units comprises electric capacity or transistor.
5. the circuit according to any one of Claims 1 to 4, it is characterized in that, described M signal generation module comprises the first signal generation unit, latch and the second phase inverter, described latch and the first signal generation unit and power-up initializing model calling, described second phase inverter is connected with described latch.
6. circuit as claimed in claim 5, it is characterized in that, described first signal generation unit comprises:
First switch, its control end is connected with holding wire by the first resistance, and the first external connection end is connected with described holding wire by the second resistance,
Second switch, its control end is connected with the output of described M signal generation module, and the first external connection end is connected with the control end of described first switch by the 3rd resistance, and the second external connection end is connected with the second external connection end of described first switch,
Be connected with the second energy-storage units between the control end of described first switch and its second external connection end, between the first external connection end of described first switch and its second external connection end, be connected with the 3rd energy-storage units.
7. circuit as claimed in claim 6, is characterized in that,
When the signal that described holding wire transmits is current source signal, described 3rd ohmically voltage is less than the cut-in voltage of described first switch;
When the signal that described holding wire transmits is voltage source signal, described 3rd ohmically voltage is more than or equal to the cut-in voltage of described first switch.
8. the circuit according to any one of Claims 1 to 4, is characterized in that, described directive generation module comprises:
First and door, described first is connected with described holding wire with the first input end of door, and the second input is connected with described M signal generation module; And/or,
First nor gate and second and door, the first input end of described first nor gate is connected with described power-up initializing module and M signal generation module respectively with the second input, and described second is connected with described holding wire and the first nor gate respectively with the first input end of door and the second input.
9. a consumable chip, is characterized in that, described consumable chip comprises:
Operational order generative circuit according to any one of claim 1 ~ 8;
Data storage circuitry, it, for the operational order exported according to described operational order generative circuit, carries out the storage of data or the output of data.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510317365.1A CN104943395B (en) | 2014-11-28 | 2015-06-10 | A kind of operational order generative circuit and consumable chip |
| US15/528,925 US9865314B2 (en) | 2014-11-28 | 2015-11-25 | Operation instruction generating circuit and consumable chip |
| PCT/CN2015/095537 WO2016082761A1 (en) | 2014-11-28 | 2015-11-25 | Operation instruction generating circuit and consumable chip |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
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| CN2014107155200 | 2014-11-28 | ||
| CN201410715520 | 2014-11-28 | ||
| CN201510317365.1A CN104943395B (en) | 2014-11-28 | 2015-06-10 | A kind of operational order generative circuit and consumable chip |
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| CN104943395A true CN104943395A (en) | 2015-09-30 |
| CN104943395B CN104943395B (en) | 2016-08-31 |
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| CN201510317377.4A Active CN104952485B (en) | 2014-11-28 | 2015-06-10 | A kind of resistance switching circuit, storage circuit and consumable chip |
| CN201510317365.1A Active CN104943395B (en) | 2014-11-28 | 2015-06-10 | A kind of operational order generative circuit and consumable chip |
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| Country | Link |
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| US (2) | US9633701B2 (en) |
| EP (1) | EP3109864B1 (en) |
| CN (2) | CN104952485B (en) |
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| WO (2) | WO2016082761A1 (en) |
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| WO2016082761A1 (en) * | 2014-11-28 | 2016-06-02 | 珠海艾派克微电子有限公司 | Operation instruction generating circuit and consumable chip |
| CN109334261A (en) * | 2018-10-09 | 2019-02-15 | 杭州旗捷科技有限公司 | Command generating circuit, consumable chip and consumptive material |
| CN111703210A (en) * | 2019-12-31 | 2020-09-25 | 珠海艾派克微电子有限公司 | Consumable chip and response method of consumable chip |
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Also Published As
| Publication number | Publication date |
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| US9633701B2 (en) | 2017-04-25 |
| WO2016082760A1 (en) | 2016-06-02 |
| EP3109864A1 (en) | 2016-12-28 |
| CN104952485A (en) | 2015-09-30 |
| CN104943395B (en) | 2016-08-31 |
| CN104952485B (en) | 2019-07-19 |
| US9865314B2 (en) | 2018-01-09 |
| US20170330604A1 (en) | 2017-11-16 |
| WO2016082761A1 (en) | 2016-06-02 |
| EP3109864B1 (en) | 2019-04-24 |
| EP3109864A4 (en) | 2017-07-26 |
| US20170069357A1 (en) | 2017-03-09 |
| ES2735751T3 (en) | 2019-12-20 |
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