CN109346117A - EEPROM storage circuit, EEPROM storage chip, consumable container and imaging device - Google Patents
EEPROM storage circuit, EEPROM storage chip, consumable container and imaging device Download PDFInfo
- Publication number
- CN109346117A CN109346117A CN201811360841.8A CN201811360841A CN109346117A CN 109346117 A CN109346117 A CN 109346117A CN 201811360841 A CN201811360841 A CN 201811360841A CN 109346117 A CN109346117 A CN 109346117A
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- China
- Prior art keywords
- data
- circuit
- storage unit
- eeprom
- storage
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
Abstract
The present invention provides a kind of EEPROM storage circuit, EEPROM storage chip, consumable container and imaging device, the circuit includes address decoding circuitry, data input circuit, read-write control circuit, EEPROM storage array and data output circuit, EEPROM storage array includes multiple memory cell groups, each memory cell group includes the first storage unit and the second storage unit, first storage unit and the second storage unit are electrically connected with data input circuit respectively, data input circuit sends the in-phase data of input data to the first storage unit and sends the oppisite phase data of input data to the second storage unit；Data output circuit includes comparator, and the bit line end of the first storage unit is electrically connected with the normal phase input end of comparator, and the bit line end of the second storage unit is electrically connected with the inverting input terminal of comparator.EEPROM storage chip, consumable container and the imaging device for applying the circuit are also provided.EEPROM storage circuit data storage performance under high temperature environment can be improved using the present invention.
Description
Technical field
The present invention relates to storage chip technical fields, specifically, being related to a kind of EEPROM storage circuit, further relate to apply and be somebody's turn to do
EEPROM storage chip, consumable container and the imaging device of circuit.
Background technique
Imaging device described in the present invention refer to by the electric signals such as text, pattern be converted on the media such as paper formed can
The equipment of visible image, such as printer, duplicator, facsimile machine and the all-in-one multifunctional machine of ink-jet approaches or laser class.Common two
Kind of printer is ink-jet printer and laser printer, ink-jet printer use accommodate the print cartridge of ink as consumable container to
Printer provides the ink of printing, to form the text or pattern that need to print on paper；Laser printer is then using appearance
The cartridge of carbon dust received provides the carbon dust of printing to printer as consumable container, needs to print to be formed on medium
Text or pattern, duplicator, facsimile machine and all-in-one multifunctional machine image-forming principle, use consumable container etc. and the basic phase of printer
Together.
The image-forming information of imaging device also is stored in storage chip other than being stored in imaging device itself.Wherein deposit
Storage chip is mounted on consumable container needed for imaging device is imaged, and effect one is to provide the number that consumable container is matched with imaging device
According to, second is that the data of record imaging material consumption and be supplied to imaging device inquiry, prevent from being finished because of material rear imaging device after
Continue work and damages equipment.General storage chip includes control unit, storage unit, interface unit, is wherein deposited in storage unit
The initial informations such as manufacturer's Storage Box model, build date, color, institute's package material quantity are contained, and is imaged and sets after being stored with
The standby information such as consumable material quantity and date in imaging process.Matching consumable container is generally stored in imaging device
The initial informations such as model, color.
Storage chip is internally provided with the storage unit for saving data, such as EEPROM memory cell, and EEPROM storage is single
Member is FGS floating gate structure, as shown in Figure 1, EEPROM memory cell includes bit line end BL, word line end WL, control terminal CG and ground terminal
AG.When storing data is " 0 ", floating-gate pipe conducting, but there are certain conducting resistance, when storing data position " 1 ", floating-gate pipe is cut
Only, conducting resistance is infinitely great.Pull-up resistor must be had or provide current source by reading data bit line end BL, therefore read data " 1 "
When, bit line end voltage is high level, is then low level when reading data " 0 ".When reading the data of EEPROM storage chip storage,
Bit line end BL can generally connect a current source or a larger pull-up resistor, and bit line end BL connects a phase inverter as reading
EEPROM data output, because the conducting resistance is increased with temperature there are certain conducting resistance when floating-gate pipe storing data " 0 "
And increase, when chip operation is at 80 DEG C or more, the equivalent conducting resistance of floating-gate pipe is increased to so that bit line end voltage is higher than output
The turnover voltage of door causes reading data mistake occur, misreads as " 1 ", therefore limit the range of chip operating temperature.
In addition EEPROM storage chip is with the extension of storage time, and charge will appear loss on floating gate, if storage
Data are " 0 ", then the equivalent conducting resistance of floating gate can it is longer with storage time and increase, in chip reading memory data, have
" 0 " may be misread as " 1 ", therefore, eeprom memory can cause reading data to miss with the extension of time data memory
Difference.
Summary of the invention
The first object of the present invention is to provide a kind of EEPROM storage that data storage performance under high temperature environment can be improved
Circuit.
The second object of the present invention is to provide a kind of EEPROM storage that data storage performance under high temperature environment can be improved
Chip.
The third object of the present invention is to provide a kind of consumable container that data storage performance under high temperature environment can be improved.
The fourth object of the present invention is to provide a kind of imaging device that data storage performance under high temperature environment can be improved.
In order to realize that above-mentioned first purpose, EEPROM storage circuit of the invention include address decoding circuitry, data input
Circuit, read-write control circuit, EEPROM storage array and data output circuit, address decoding circuitry, data input circuit, reading
Write control circuit and data output circuit are electrically connected with EEPROM memory cell respectively, and EEPROM storage array includes multiple deposits
Storage unit group, each memory cell group include the first storage unit and the second storage unit, and the first storage unit and second is deposited
Storage unit is electrically connected with data input circuit respectively, and data input circuit sends the same number of phases of input data to the first storage unit
According to and to the second storage unit send input data oppisite phase data；Data output circuit includes comparator, the first storage unit
Bit line end be electrically connected with the normal phase input end of comparator, the inverting input terminal electricity of the bit line end of the second storage unit and comparator
Connection.
By above scheme as it can be seen that EEPROM storage circuit of the invention is single by the first storage unit of setting and the second storage
Member is arranged comparator to store the in-phase data and oppisite phase data of input data, and in data output circuit, is reading data
When, while reading in-phase data and oppisite phase data is compared, thus when guaranteeing to read data, regardless of environment temperature becomes
Change, the equivalent conducting resistance of the floating gate of the first storage unit and the second storage unit will not be equal, and two input terminals of comparator are deposited
In potential difference, so that the data of comparator output are identical as input data, to improve data storage in a high temperauture environment
Energy.Further, since the arithmetic speed of operational amplifier is very fast, so, data output circuit carries out the reading of data using comparator
It takes, the reading speed of EEPROM storage circuit can be promoted.
In further embodiment, data input circuit includes the first latch, the positive output end of the first latch and the
The control terminal of one storage unit is electrically connected, and the reversed-phase output of the first latch is electrically connected with the control terminal of the second storage unit.
It can be seen that data input circuit input data can will be converted into and be inputted simultaneously by the first latch of setting
Data with phase in-phase data and be converted into oppisite phase data with input data reverse phase, the setting of circuit can be simplified.
In further embodiment, data output circuit further includes the second latch, and the input terminal of the second latch is compared with
The output end of device is electrically connected.
It can be seen that the second latch is arranged in the output end in comparator, the data of reading can be stored, if subsequent
It does not need then to be again read out memory cell array when being read out same data, improves reading speed.
In further embodiment, data output circuit further includes buffer, the input terminal of buffer and the second latch
Output end electrical connection.
It can be seen that setting buffer, can realize the synchronous of data transmission with the circuit of subsequent connecting.
In order to realize above-mentioned second purpose, EEPROM storage chip of the invention is provided with EEPROM storage circuit,
EEPROM storage circuit includes address decoding circuitry, data input circuit, read-write control circuit, EEPROM storage array and number
According to output circuit, address decoding circuitry, data input circuit, read-write control circuit and data output circuit respectively with EEPROM
Storage unit electrical connection, EEPROM storage array include multiple memory cell groups, each memory cell group includes the first storage
Unit and the second storage unit, the first storage unit and the second storage unit are electrically connected with data input circuit respectively, the number
The in-phase data of input data is sent to first storage unit according to input circuit and sends institute to second storage unit
State the oppisite phase data of input data；Data output circuit includes comparator, and the bit line end and comparator of the first storage unit are just
The electrical connection of phase input terminal, the bit line end of the second storage unit are electrically connected with the inverting input terminal of comparator.
By above scheme it is found that EEPROM storage circuit of the invention is single by the first storage unit of setting and the second storage
Member is arranged comparator to store the in-phase data and oppisite phase data of input data, and in data output circuit, is reading data
When, while reading in-phase data and oppisite phase data is compared, thus when guaranteeing to read data, regardless of environment temperature becomes
Change, the equivalent conducting resistance of the floating gate of the first storage unit and the second storage unit will not be equal, and two input terminals of comparator are deposited
In potential difference, so that the data of comparator output are identical as input data, to improve data storage in a high temperauture environment
Energy.
In order to realize above-mentioned third purpose, consumable container of the invention is equipped with EEPROM storage chip, EEPROM storage
Chip applies above-mentioned EEPROM storage circuit.
In order to realize above-mentioned 4th purpose, imaging device includes consumable container, and consumable container is equipped with EEPROM storage core
Piece, EEPROM storage chip apply above-mentioned EEPROM storage circuit.
Detailed description of the invention
Fig. 1 is the schematic diagram of existing EEPROM FGS floating gate structure.
Fig. 2 is the circuit structure block diagram of EEPROM storage circuit embodiment of the present invention.
Fig. 3 is the circuit diagram of data input circuit in EEPROM storage circuit embodiment of the present invention.
Fig. 4 is the circuit diagram of EEPROM storage array in EEPROM storage circuit embodiment of the present invention.
Fig. 5 is the circuit diagram of data output circuit in EEPROM storage circuit embodiment of the present invention.
The invention will be further described with reference to the accompanying drawings and embodiments.
Specific embodiment
EEPROM storage circuit embodiment:
As shown in Fig. 2, EEPROM storage circuit includes address decoding circuitry 1, data input circuit 2, reads in the present embodiment
Write control circuit 3, EEPROM storage array 4 and data output circuit 5, address decoding circuitry 1, data input circuit 2, read-write
Control circuit 3 and data output circuit 5 are electrically connected with EEPROM memory cell 4 respectively.Address decoding circuitry 1 is for receiving ground
Location signal simultaneously decodes it, selects storage unit corresponding with this address, to carry out read/write operation to the unit.
Address decoding circuitry 1 uses known address decoder, and details are not described herein.Read-write control circuit 3 generate and provide piece choosing and
Read/write control logic signal, for completing the read/write operation to data bit each in selected storage unit.Read-write control circuit 3
Using known address decoding circuitry, details are not described herein.
Referring to Fig. 3, data input circuit 2 includes that the input terminal D of the first latch U1, the first latch U1 obtains input number
According to the positive output end Q and reversed-phase output QN of the first latch U1 is electrically connected with EEPROM storage array 4 respectively.This implementation
In example, the first latch U1 is D-latch.Referring to fig. 4, EEPROM storage array 4 includes multiple memory cell groups 41, each
Memory cell group 41 includes the first storage unit 411 and the second storage unit 412, and the first storage unit 411 and the second storage are single
Member 412 is electrically connected with data input circuit 2 respectively, and data input circuit 2 sends the same of input data to the first storage unit 411
Phase data and the oppisite phase data that input data is sent to the second storage unit 412.In the present embodiment, the positive of the first latch U1
Output end Q is electrically connected with the control terminal of the first storage unit 411, and the storage of the reversed-phase output QN of the first latch U1 and second is single
The control terminal electrical connection of member 412.It is of course also possible to be the positive output end Q and the second storage unit 412 of the first latch U1
Control terminal electrical connection, the reversed-phase output QN of the first latch U1 are electrically connected with the control terminal of the first storage unit 411, after only needing
Corresponding decision logic is arranged to output data in continuous circuit.
Referring to Fig. 5, data output circuit 5 includes comparator U2, the second latch U3 and phase inverter U4, the first storage unit
411 bit line end is electrically connected with the normal phase input end of comparator U2, and the bit line end of the second storage unit 422 is anti-with comparator U2's
The electrical connection of phase input terminal, the input terminal U3 of the second latch are electrically connected with the output end of comparator U2, the input terminal of buffer U4
It is electrically connected with the output end of the second latch U3.In the present embodiment, the second latch U3 is D-latch.
EEPROM storage circuit of the invention is when carrying out data write operation, the first latch of data input circuit 2
U1 latches input data, and to the in-phase data and oppisite phase data of 4 input-output data of EEPROM storage array, inputs
The in-phase data and oppisite phase data of data are respectively stored in the first storage unit 411 and the second storage of same memory cell group 41
In unit 412.In the present embodiment, when input data is " 0 ", output end Q exports " 0 ", and output end QN exports " 1 ", the first storage
411 storing data of unit " 0 ", 412 storing data of the second storage unit " 1 "；When input data is " 1 ", then the first storage unit
411 storing datas " 1 ", 412 storing data of the second storage unit " 0 ".
When reading data, the normal phase input end of comparator U2 obtains storage number from the bit line end of the first storage unit 411
According to the inverting input terminal of comparator U2 obtains storing data from the bit line end of the second storage unit 422, and comparator U2 is defeated to positive
The data for entering end and inverting input terminal are compared and export output data to the second latch U3, and the second latch U3 is to output
Data are sent after being latched to phase inverter U4, are finally exported by the output end Dout of phase inverter U4.
Since the storage of each bit data is all that pairs of (a same to phase, a reverse phase) occurs, therefore when reading data,
Regardless of environment temperature changes or increases, the equivalent conducting resistance of floating gate of corresponding two storage units of the same bit data is not
Can be equal, therefore, the bit line end voltage of corresponding two storage units of the same bit data is also never equal.
For example, a certain 41 storing data of memory cell group is " 0 ", when reading data, the storage of the first storage unit 411 is
" 0 ", then the bit line end voltage of the first storage unit 411 is equal to the equivalent conducting resistance of floating gate multiplied by current source current, due to floating gate
Equivalent conducting resistance increases with temperature and is increased, and therefore, the bit line end voltage of the first storage unit 411 also increases, but not
Operating supply voltage can be reached；The storage of second storage unit 412 is " 1 ", then the bit line equivalent resistance of the second storage unit 412
For infinity, therefore, the bit line end voltage of the second storage unit 412 is equal to operating supply voltage；The position of first storage unit 411
Line end voltage and the bit line end voltage of the second storage unit 412 are separately input to comparator U2 normal phase input end and inverting input terminal
Afterwards, even if the bit line end voltage of the first storage unit 411 is raised to the voltage that can be judged to high level or more, but amplifier output electricity
Pressure is still low level.When 41 storing data of memory cell group is " 1 " similarly.Therefore, EEPROM storage circuit can be reduced due to temperature
Degree increases the influence for causing to misread.
EEPROM storage chip:
EEPROM storage chip is provided with EEPROM storage circuit, in EEPROM storage circuit application above-described embodiment
EEPROM storage circuit.
Cartridge embodiment:
Cartridge includes shell, which surrounds the cavity for accommodating carbon dust, and EEPROM storage is equipped on the outer wall of shell
Chip, EEPROM storage chip are provided with EEPROM storage circuit, EEPROM in EEPROM storage circuit application above-described embodiment
Storage circuit.
As a kind of transformation of cartridge embodiment of the present invention, the ink for being equipped with above-mentioned EEPROM storage chip can be
Box, the print cartridges structure is similar to above-mentioned carbon dust box structure, and the EEPROM storage core of embodiment as above is equipped on housing exterior walls
Piece.
Printer embodiment:
Laser printer includes imaging unit and cartridge, and EEPROM storage chip as above is equipped on the cartridge,
EEPROM storage chip is provided with EEPROM storage circuit, EEPROM storage electricity in EEPROM storage circuit application above-described embodiment
Road.
As a kind of transformation of printer embodiment of the present invention, ink-jet printer, structure and above-described embodiment can be
Similar, ink-jet printer includes imaging unit and print cartridge, and EEPROM storage chip as above is equipped on print cartridge.
As the another kind transformation of printer embodiment of the present invention, duplicator or facsimile machine or multifunctional integrated can also be
The purpose of the present invention equally may be implemented in other imaging devices such as machine, above-mentioned transformation.
It can be seen from the above, EEPROM storage circuit of the invention passes through the first storage unit of setting and the second storage unit,
To store the in-phase data and oppisite phase data of input data, and in data output circuit, comparator is set, when reading data,
It reads in-phase data simultaneously and oppisite phase data is compared, thus when guaranteeing to read data, regardless of environment temperature changes, the
The equivalent conducting resistance of the floating gate of one storage unit and the second storage unit will not be equal, and there are current potentials for two input terminals of comparator
Difference, so that the data of comparator output are identical as input data, to improve data storage performance in a high temperauture environment.This
Outside, since the arithmetic speed of operational amplifier is very fast, so, data output circuit carries out the reading of data using comparator, can
Promote the reading speed of EEPROM storage circuit.
It should be noted that the above is only a preferred embodiment of the present invention, but the design concept invented is not limited thereto,
All insubstantial modifications made using this design to the present invention, are also fallen within the scope of protection of the present invention.
Claims (10)
1. a kind of EEPROM storage circuit, including address decoding circuitry, data input circuit, read-write control circuit, EEPROM are deposited
Store up array and data output circuit, the address decoding circuitry, the data input circuit, the read-write control circuit and
The data output circuit is electrically connected with the EEPROM memory cell respectively, it is characterised in that:
The EEPROM storage array includes multiple memory cell groups, each described memory cell group includes the first storage unit
With the second storage unit, first storage unit and second storage unit are electrically connected with the data input circuit respectively
It connects, the data input circuit sends the in-phase data of input data to first storage unit and stores to described second single
Member sends the oppisite phase data of the input data；
The data output circuit includes comparator, the first bit line end of first storage unit and the positive of the comparator
Input terminal electrical connection, the second bit line end of second storage unit are electrically connected with the inverting input terminal of the comparator.
2. EEPROM storage circuit according to claim 1, it is characterised in that:
The data input circuit includes the first latch, and the positive output end of first latch and first storage are single
The control terminal electrical connection of member, the reversed-phase output of first latch are electrically connected with the control terminal of second storage unit.
3. EEPROM storage circuit according to claim 1 or 2, it is characterised in that:
The data output circuit further includes the second latch, the output of the input terminal and the comparator of second latch
End electrical connection.
4. EEPROM storage circuit according to claim 3, it is characterised in that:
The data output circuit further includes buffer, the output end electricity of the input terminal of the buffer and second latch
Connection.
5. a kind of EEPROM storage chip is provided with EEPROM storage circuit, the EEPROM storage circuit includes address decoding
Circuit, data input circuit, read-write control circuit, EEPROM storage array and data output circuit, the address decoding electricity
Road, the data input circuit, the read-write control circuit and the data output circuit are stored with the EEPROM respectively
Unit electrical connection, it is characterised in that:
The EEPROM storage array includes multiple memory cell groups, each described memory cell group includes the first storage unit
With the second storage unit, first storage unit and second storage unit are electrically connected with the data input circuit respectively
It connects, the data input circuit sends the in-phase data of input data to first storage unit and stores to described second single
Member sends the oppisite phase data of the input data；
The data output circuit includes comparator, and the bit line end of first storage unit and the positive of the comparator input
End electrical connection, the bit line end of second storage unit are electrically connected with the inverting input terminal of the comparator.
6. EEPROM storage chip according to claim 5, it is characterised in that:
The data input circuit includes the first latch, and the positive output end of first latch and first storage are single
The control terminal electrical connection of member, the reversed-phase output of first latch are electrically connected with the control terminal of second storage unit.
7. EEPROM storage chip according to claim 5 or 6, it is characterised in that:
The data output circuit further includes the second latch, the output of the input terminal and the comparator of second latch
End electrical connection.
8. EEPROM storage chip according to claim 7, it is characterised in that:
The data output circuit further includes buffer, the output end electricity of the input terminal of the buffer and second latch
Connection.
9. a kind of consumable container is equipped with EEPROM storage chip, it is characterised in that:
The described in any item EEPROM storage circuits of EEPROM storage chip application Claims 1-4.
10. a kind of imaging device, including consumable container, the consumable container is equipped with EEPROM storage chip, it is characterised in that:
The described in any item EEPROM storage circuits of EEPROM storage chip application Claims 1-4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811360841.8A CN109346117A (en) | 2018-11-15 | 2018-11-15 | EEPROM storage circuit, EEPROM storage chip, consumable container and imaging device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811360841.8A CN109346117A (en) | 2018-11-15 | 2018-11-15 | EEPROM storage circuit, EEPROM storage chip, consumable container and imaging device |
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| Publication Number | Publication Date |
|---|---|
| CN109346117A true CN109346117A (en) | 2019-02-15 |
Family
ID=65315691
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811360841.8A Pending CN109346117A (en) | 2018-11-15 | 2018-11-15 | EEPROM storage circuit, EEPROM storage chip, consumable container and imaging device |
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| CN (1) | CN109346117A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113643746A (en) * | 2021-07-02 | 2021-11-12 | 深圳市宏旺微电子有限公司 | Flash memory data analysis method and device, terminal equipment and storage medium |
| CN114067860A (en) * | 2020-08-03 | 2022-02-18 | 长鑫存储技术有限公司 | Storage system |
| US11823765B2 (en) | 2020-08-03 | 2023-11-21 | Changxin Memory Technologies, Inc. | Storage system |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020110022A1 (en) * | 2001-02-13 | 2002-08-15 | Masanori Miyagi | Complementary non-volatile memory circuit |
| US20040257871A1 (en) * | 2003-06-20 | 2004-12-23 | Swift Craig T. | Memory with multiple state cells and sensing method |
| CN101154448A (en) * | 2006-09-29 | 2008-04-02 | 海力士半导体有限公司 | Page buffer circuit of memory device and program method |
| US20110063924A1 (en) * | 2009-09-11 | 2011-03-17 | Semiconductor Manufacturing International (Shanghai) Corporation | Method of flash memory design with differential cell for better endurance |
| JP2011192329A (en) * | 2010-03-12 | 2011-09-29 | Seiko Epson Corp | Nonvolatile storage device, integrated circuit device and electronic equipment |
| CN104347114A (en) * | 2013-07-26 | 2015-02-11 | 珠海艾派克微电子有限公司 | Nonvolatile memory cell and memory |
-
2018
- 2018-11-15 CN CN201811360841.8A patent/CN109346117A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020110022A1 (en) * | 2001-02-13 | 2002-08-15 | Masanori Miyagi | Complementary non-volatile memory circuit |
| US20040257871A1 (en) * | 2003-06-20 | 2004-12-23 | Swift Craig T. | Memory with multiple state cells and sensing method |
| CN101154448A (en) * | 2006-09-29 | 2008-04-02 | 海力士半导体有限公司 | Page buffer circuit of memory device and program method |
| US20110063924A1 (en) * | 2009-09-11 | 2011-03-17 | Semiconductor Manufacturing International (Shanghai) Corporation | Method of flash memory design with differential cell for better endurance |
| JP2011192329A (en) * | 2010-03-12 | 2011-09-29 | Seiko Epson Corp | Nonvolatile storage device, integrated circuit device and electronic equipment |
| CN104347114A (en) * | 2013-07-26 | 2015-02-11 | 珠海艾派克微电子有限公司 | Nonvolatile memory cell and memory |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114067860A (en) * | 2020-08-03 | 2022-02-18 | 长鑫存储技术有限公司 | Storage system |
| US11823765B2 (en) | 2020-08-03 | 2023-11-21 | Changxin Memory Technologies, Inc. | Storage system |
| CN114067860B (en) * | 2020-08-03 | 2024-03-26 | 长鑫存储技术有限公司 | Storage system |
| CN113643746A (en) * | 2021-07-02 | 2021-11-12 | 深圳市宏旺微电子有限公司 | Flash memory data analysis method and device, terminal equipment and storage medium |
| CN113643746B (en) * | 2021-07-02 | 2023-09-26 | 深圳市宏旺微电子有限公司 | Flash memory data analysis method and device, terminal equipment and storage medium |
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Application publication date: 20190215 |