CN101853214B - Storage device - Google Patents
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- CN101853214B CN101853214B CN 201010154233 CN201010154233A CN101853214B CN 101853214 B CN101853214 B CN 101853214B CN 201010154233 CN201010154233 CN 201010154233 CN 201010154233 A CN201010154233 A CN 201010154233A CN 101853214 B CN101853214 B CN 101853214B
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
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- G11C2211/5641—Multilevel memory having cells with different number of storage levels
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Abstract
A storage device includes: a binary flash memory that has a first storage area and a capacity of storing two values per each cell; a multivalued flash memory that has a second storage area and a capacity of storing at least three values per each cell; and a controller configured to arrange the first storage area ahead of the second storage area, logically combine the first storage area with the second storage area to form a single combined storage area, and perform data reading and data writing from and into the combined storage area. Data management information is stored in a head of the combined storage area according to a predetermined file system. The storage device of this arrangement has the advantages of both an SLC flash memory and an MLC flash memory.
Description
It is 200810098116.8 that the application is based on application number, and the applying date is on May 13rd, 2008, and the application people is Babbilu Inc., and name is called the dividing an application of application for a patent for invention of " memory storage ".
Technical field
The present invention relates to be stored in the data storage device that uses in computing machine or the various electronic equipment.
Background technology
In recent years, as the external memory of computing machine, popularize for the storage card of representative, USB flash memory driver (USBflash drive) with compact flash (compactflash) (registered trademark, below identical).Be built-in with flash memory in these external memories, this flash memory is rewritable non-volatile ROM.The flash memory (for example, with reference to following patent documentation 1) that the SLC of being called as (Single Level Cell, single stage unit) type and MLC (Multi Level Cell, multi-level unit) type are arranged.
Patent documentation 1: Japanese documentation JP 2002-8380 communique.
SLC type flash memory is the storer that all the time is widely used, and is the every individual unit storer that can store 1 information (below be also referred to as " two-value storer ").Relative therewith, MLC type memory cell is the every individual unit storer that can store the information more than 2 (below be also referred to as " multivalued storage ").MLC type flash memory can take completely charged state, electric weight residue by each unit that 2/3rds state, electric weight residue have 1/3rd state, these four kinds of states of state of being discharged fully and with the information of 2 of every individual unit storages.
Usually, but MLC type flash memory has few but the characteristics that memory capacity is larger than SLC type of low speed action number of rewrites.On the other hand, but SLC type flash memory has many but the characteristics that memory capacity is less than MLC type of high speed motion number of rewrites.
Summary of the invention
Invent problem to be solved
In view of the above problems, problem to be solved by this invention provides a kind of the two memory storage of advantage of characteristics of SLC type flash memory and MLC type flash memory of having brought into play.
For the means of dealing with problems
In view of above-mentioned problem, the following formation of the memory storage of an embodiment of the invention.
Namely, the invention provides a kind of memory storage, this memory storage is in the management information of the beginning record data of storage area, and can store data according to predetermined file system, described memory storage is characterised in that, comprise: the two-value flash memory, have the first storage area, every individual unit can be stored 2 kinds of values; Many-valued flash memory has the second storage area, and every individual unit can be stored the value more than 3 kinds; And control part, logic is in conjunction with described the first storage area and described the second storage area, and as carrying out the read-write of data for the calmodulin binding domain CaM of single storage area in the zone that described the first storage area is disposed at beginning.
According to the memory storage of aforesaid way, the first storage area that the two-value flash memory is had is disposed at the beginning of calmodulin binding domain CaM.Therefore, the management information of the data such as file allocation table is written in the two-value flash memory.In case since file allocation table be carry out data write or wipe the management information that will be rewritten continually, therefore the two-value flash configuration by responsiveness being higher than many-valued flash memory is in the beginning of calmodulin binding domain CaM, compared by the memory storage that many-valued flash memory consists of with Zone Full, can store at high speed data.In addition, but to compare number of rewrites many with many-valued flash memory because the two-value flash memory has, and therefore write the two-value flash memory by the file allocation table that will be rewritten continually, can improve the reliability of data storage.Like this, according to the memory storage of aforesaid way, realized high capacity by using many-valued flash memory, simultaneously by also using the two-value flash memory to can be provided in the good memory storage of high speed and reliability aspect of action.
The memory storage of aforesaid way also can adopt following constituted mode, that is, described control part comprises: address translation section, carry out the address translation between described calmodulin binding domain CaM and described the first storage area and described the second storage area; And selection portion, according to the result of described address translation, from described two-value flash memory and described many-valued flash memory, select the read-write destination of described data.According to this mode, can be according to the result of address translation and easily judge the read-write destination of data.
The memory storage of aforesaid way also can adopt following constituted mode, namely, described control part will undertaken by described address translation section will sending to be used to the instruction of the read-write of carrying out described data described selecteed flash memory after the address after the conversion sends to described two-value flash memory and described many-valued flash memory.
According to this mode, send address after the conversion to all flash memories, then only send instruction to selecteed flash memory.According to this mode, because processing speed can be improved in the transmission destination of the address after not needing to select to change from two-value flash memory and many-valued flash memory therefore.
The memory storage of aforesaid way also can adopt following constituted mode, that is, described the first storage area is more than the 0.5% and zone of arbitrary ratio of less than 100% that accounts for described calmodulin binding domain CaM.By the first storage area is set as such zone, can reliably the management information such as file allocation table be stored in the two-value flash memory.
The memory storage of aforesaid way also can adopt following constituted mode, that is, this memory storage is connected with host apparatus via predetermined interface, and described control part is according to carrying out the read-write of described data from the indication of described host apparatus.According to this mode, can be with external memory or the internal storage device of this memory storage as host apparatus.As predetermined interface, such as using the interfaces such as USB, IEEE1394, serial ATA, Parallel ATA.
The memory storage of aforesaid way also can adopt following constituted mode, that is, described control part returns the memory capacity of described calmodulin binding domain CaM when the inquiry of the memory capacity that receives this memory storage from described host apparatus.According to this mode, can notify to host apparatus in connection with the capacity of zone integral body rather than the memory capacity that each flash memory had individually.
The memory storage of aforesaid way also can adopt following constituted mode, namely, comprise a plurality of described many-valued flash memories, described control part in the zone that described the first storage area is disposed at beginning logic in conjunction with described the first storage area and a plurality of described the second storage area.According to this mode, can have a plurality of many-valued flash memories, therefore can provide the memory storage with jumbo storage area.
The present invention also can be applied to the memory storage of following mode.That is, this memory storage is in the management information of the beginning record data of storage area, and can store data according to predetermined file system, described memory storage is characterised in that, comprise: the two-value flash memory, have the first storage area, every individual unit can be stored 2 kinds of values; Many-valued flash memory has second storage area larger than described the first storage area, and every individual unit can be stored the value more than 3 kinds; Comparing section is to comparing from the address of the host apparatus appointment that is connected with this memory storage with according to the predetermined threshold value that the max cap. of described the first storage area has been determined; And control part, be that described threshold value switches to described two-value flash memory with the read-write destination of data in the situation of interior address in described address, in the situation of described address for the address that surpasses described threshold value, described read-write destination switched to described many-valued flash memory.
According to the memory storage of this mode, the so simple control in the read-write destination of switch data between many-valued flash memory and two-value flash memory can be carried out the read-write of data to these different flash memories of characteristic by carrying out according to appointed address.As a result, realized high capacity by using many-valued flash memory, simultaneously by also using the two-value flash memory to can be provided in the good memory storage of high speed and reliability aspect of action.
The memory storage of aforesaid way also can adopt following constituted mode, namely, described control part is under described read-write destination is switched to any one situation in described two-value flash memory and the described many-valued flash memory, and all former state is used the value of described address and described two-value flash memory or described many-valued flash memory are carried out the read-write of data.According to this mode, be the processing of the address of other systems owing to not needing to carry out the address translation by the host apparatus appointment, therefore can realize the simplification of processing.
The memory storage of aforesaid way also can adopt following constituted mode, that is, described control part returns the memory capacity of described the second storage area when the inquiry of the memory capacity that receives this memory storage from described host apparatus.The maximum storage capacity of the memory storage of aforesaid way is consistent with the second storage area.Therefore, can return the so simple processing of memory capacity of the second storage area and the memory capacity of this memory storage is notified to host apparatus by former state.
Description of drawings
Fig. 1 is that expression is as the key diagram of the concise and to the point formation of the memory storage of the first embodiment;
The key diagram of the concept of Fig. 2 address translation that to be expression undertaken by the Single Component Management circuit of the first embodiment;
Fig. 3 schematically shows the block diagram that the inside of the Single Component Management circuit of the first embodiment consists of;
Fig. 4 is the process flow diagram that the Single Component Management among the first embodiment is processed;
Fig. 5 is that expression is as the key diagram of the concise and to the point formation of the memory storage of the second embodiment;
Fig. 6 is the key diagram of concept of the switching controls of the Single Component Management circuit of expression by the second embodiment storage unit of carrying out;
Fig. 7 is the block diagram that schematically shows the inside formation of the Single Component Management circuit among the second embodiment;
Fig. 8 is the key diagram of the details of the change action that carries out of the control switching circuit of expression by the second embodiment.
Embodiment
Below, the effect for further clear and definite the invention described above illustrates embodiments of the present invention according to embodiment.
A. the first embodiment:
Fig. 1 is that expression is as the key diagram of the concise and to the point formation of the memory storage 10 of embodiments of the invention.The memory storage 10 of the present embodiment is connected with host apparatus 80 take computing machine as representative via USB interface, is used as external memory.Host apparatus 80 formats memory storage 10 by the file system (FAT16 or FAT32 etc.) of stipulating and carries out the read-write of data.
As shown in the figure, memory storage 10 comprises master controller 20, also comprises in addition the first storage unit 30, the second storage unit 40, the 3rd storage unit 50 and the 4th storage unit 60 that are connected and have respectively nand flash memory with this master controller 20.
The first storage unit 30 comprises two-value storer 31, and this two-value storer 31 is nand flash memories of SLC type.In addition, the first storage unit 30 comprises the first module controller 32 of controlling this two-value storer 31 according to the electrical characteristics of this two-value storer 31.In the present embodiment, adopt the compact flash memory controller of widespread use as first module controller 32.First module controller 32 receives instruction or data based on the ATA specification from master controller 20, and this two-value storer 31 is carried out the read-write of data.In the present embodiment, the first storage unit 30 has the storage area of 1G byte capacity.In the situation of the storage area that can't realize by a two-value storer 31 the 1G byte capacity, also can be connected to realize the storage area of 1G byte by making a plurality of two-value storeies 31 and first module controller 32.
The second storage unit 40 comprises multivalued storage 41, and this multivalued storage 41 is nand flash memories of MLC type.The multivalued storage 41 of the present embodiment is the storer that can store the information of 4 values (2).Certainly, as multivalued storage 41, can suitably adopt the storer that to store the above information of 3 values.The second storage unit 40 also comprises the second unit controller 42 of controlling this multivalued storage 41 according to the electrical characteristics of this multivalued storage 41.In the present embodiment, the same with the first storage unit 30, adopt the compact flash of widespread use to be used as second unit controller 42 with memory controller.The formation of the 3rd storage unit 50 and the 4th storage unit 60 is identical with the second storage unit 40.In the present embodiment, the second storage unit 40, the 3rd storage unit 50 and the 4th storage unit 60 have respectively the storage area of 15G byte capacity.Therefore, the memory storage 10 of the present embodiment has the storage area of 46G (1G+15G+15G+15G) byte capacity as a whole.In the situation of the storage area that can't realize by a multivalued storage 15G byte capacity, also can be connected to realize the storage area of 15G byte with cell controller by making a plurality of multivalued storages.
Single Component Management circuit 22 has two-value storer and the storage area of multivalued storage and the function that operates as single storage area that logic has in conjunction with each storage unit 30～60.Single Component Management circuit 22 carries out address translation according to LBA (Logical Block addressing, the LBA (Logical Block Addressing)) address of having been carried out the ATA signal after the conversion by bus switching circuit 21, realizes thus the logic combination of each storage unit 30～60.LBA refers to all sectors of storage area are distributed continuous number and specified the mode of the sector that conducts interviews by this continuous number.The LBA address represents by this continuous number." LBA address " is also referred to as " LBA parameter ".
Fig. 2 is the key diagram of the concept of the expression address translation of being undertaken by Single Component Management circuit 22.Represented the storage area by each storage unit 30～60 of Single Component Management circuit 22 management in the left side of figure.As shown in the figure, in the present embodiment, the storage area in the first storage unit 30 represents by the LBA address from " 0 " to " W ".In addition, the second storage unit 40 represents by the LBA address from " 0 " to " X ", and the 3rd storage unit represents by the LBA address from " 0 " to " Y ", and the 4th storage unit represents by the LBA address from " 0 " to " Z ".
Represented in conjunction with the storage area behind the storage area of each storage unit 30～60 on the right side of Fig. 2.As shown in the figure, the storage area of the two-value storer 31 that Single Component Management circuit 22 has the first storage unit 30 is configured in the zone of beginning, then configures the storage area of the multivalued storage 41～61 that other storage unit 40～60 have.As shown in Figure 2, in conjunction with after the continuous LBA address of storage area by from " 0 " to " W+X+Y+Z " represent.By next in conjunction with storage area like this by Single Component Management circuit 22, host apparatus 80 can identify the storage areas in the memory storage 10 as the storage area that the continuous LBA address by from " 0 " to " W+X+Y+Z " represents.In the following description, in connection with after storage area be called " calmodulin binding domain CaM UA ".
Fig. 3 is the block diagram that schematically shows the inside formation of Single Component Management circuit 22.Single Component Management circuit 22 also has the function that the ATA instruction of will send from host apparatus 80 or data send each storage unit 30～60 to except carrying out address above mentioned conversion.In Fig. 3, represented to be used for realizing that the inside of this transmitting function consists of.
The cell controller 32～62 that each storage unit 30～60 has comprises respectively follows the 8 kinds of registers ATA specification, that be called as the instruction block register.These 8 kinds of registers are called: (1) characteristic register, (2) sector number register, (3) equipment/head (head) register, the high bit register of (4) cylinder, the low bit register of (5) cylinder, (6) sector number register, (7) order register, (8) data register.Cell controller 32～62 is controlled read-write to the data of two-value storer or multivalued storage according to the various parameters that arrange in these registers.Host apparatus 80 will send to the interrogation signal of these registers memory storage 10 when reading and writing data.
When receiving above-mentioned interrogation signal via USB interface and bus switching circuit 21 from host apparatus 80, Single Component Management circuit 22 changes transfer approach to the interrogation signal of each storage unit 30～60 according to the kind as the register of access object.Single Component Management circuit 22 comprises for the register decision circuitry 78 of judgement as the kind of the register of access object.
Register decision circuitry 78 is according to the state from the address signal A0～A2 of bus switching circuit 21 inputs, judges kind as the register of access object based on the ATA specification.For example as shown in the figure, be that " 0 ", address signal A0 are " 1 " if address signal A2 is " 0 ", address signal A1, then register decision circuitry 78 can be judged the interrogation signal of having inputted the characteristic register.
In situation about receiving from host apparatus 80 interrogation signal of characteristic register and sector number register, Single Component Management circuit 22 passes through this interrogation signal former state, sends this interrogation signal to all memory cells 30～60.This is because these registers are not for the register of directly specifying the position in the calmodulin binding domain CaM UA.Specifically, the characteristic register be for according to ATA instruction to specify the register of various parameters, sector number register be for the register of specifying its sector number when a plurality of sector of connected reference.An equipment described later/register, the high bit register of cylinder, the low bit register of cylinder, sector number register are used in the appointment to " initial sector " during about connected reference.
An equipment/register, the high bit register of cylinder, the low bit register of cylinder, sector number register are the registers that is used to specify the position (sector) in the calmodulin binding domain CaM UA.Input respectively the part of the LBA address of the sector in the expression calmodulin binding domain CaM UA to these registers.Specifically, if the LBA address is 28 long parameters, then to sector number register input from the 0th to the 7th rank, to the low bit register input of cylinder from the 8th to the 15th rank.In addition, to the input of the high bit register of cylinder from the 16th to the 23rd rank, to an equipment/register input from the 24th to the 27th rank.When the interrogation signal that receives these registers, Single Component Management circuit 22 temporarily with this signal latch in latch cicuit 70～73.
The interrogation signal that is latched in the latch cicuit 70～73 is transfused to address decoder 90.Address decoder 90 has and will be stored in discretely LBA address in each latch cicuit 70～73 and combine and be restored to the function of 28 long LBA addresses.In addition, address decoder 90 has the function that the maximum sector number to the LBA address after restoring and each storage unit compares.The back will explain this function.
Order register is the register that is used to specify based on the various instructions of ATA specification.As such instruction, reading the sector instruction, write the sector instruction to the sector data writing of appointment from the sector reading data of appointment for example arranged.When the command signal that receives order register, Single Component Management circuit 22 inputs to command decoder 91 and latch cicuit 74 with this signal.
When having inputted command signal, command decoder 91 is judged the kind of the instruction of input, and this judged result is exported to address conversion circuit 92 and unit selector switch 94.The command signal that is input to latch cicuit 74 remained in the latch cicuit 74 before the output indication that has from unit selector switch 94.
It is the function of the LBA address of each memory cell 30～60 that address conversion circuit 92 has the LBA address translation about calmodulin binding domain CaM UA as shown in Figure 2, that will input from address decoder 90.Specifically, address conversion circuit 92 is inputted the LBA addresses from address decoder 90, and inputs the kind of instructions from command decoder 91.Then, whether the kind of the instruction of judgement input needs the instruction of LBA address.Need the instruction of LBA address to refer to usually address (sector) be specified and the address of appointment is carried out the instruction of certain access, such as " reading the sector instruction ", " writing the sector instruction ", " repeatedly reading instruction ", " repeatedly write command ", " reading the DMA instruction ", " writing the DMA instruction ", " instruction of read check sector ", " look-up command " etc. are arranged.If address conversion circuit 92 judges that the kind of the instruction of input is the instruction that needs the LBA address, to be the LBA address (back will illustrate conversion method) of each storage unit from the LBA address translation of address decoder 90 inputs then, and the LBA address after will changing send all storage unit 30～60 to.As described later, master controller 20 can not transmit the ATA instruction that needs the LBA address to a plurality of storage unit simultaneously, and therefore the LBA address after the conversion can send all storage unit 30～60 to.Thus, address conversion circuit 92 can omit the processing of selecting to transmit the destination.Certainly, also can be only transmit LBA address after the conversion to this storage unit.
If be the instruction that does not need the LBA address from the kind of the instruction of command decoder 91 input, then address conversion circuit 92 will send all storage unit 30～60 to from the parameter former state of address decoder 90 inputs.This is because in for the situation of instruction that does not need the LBA address, and the interrogation signal that is input to an equipment/register etc. is not limited to represent the LBA address.The instruction that does not need the LBA address refer in the situation that not assigned address (sector) flash memory is carried out the instruction of certain operation, such as " identification equipment (identify device) instruction ", " the characteristic instruction is set ", " checking the power mode instruction ", " sleep instruction ", " standby command ", " idle instruction " etc. are arranged.Be not need in the situation of instruction of LBA address in the kind from the instruction of command decoder 91 input, address conversion circuit 92 also can similarly transmit LBA address after the conversion to storage unit 30～60 with the instruction that needs the LBA address.This is because not need the instruction of LBA address be the instruction that no matter has or not the LBA address all can be performed.Certainly, also can be to change but do not transmit the formation of the LBA address after the conversion.
The timing that remains on the command signal in the latch cicuit 74 to the output of each unit is set to LBA address after the address translation and is sent to each storage unit from address conversion circuit 92 and finished timing after the switching of the first on-off circuit 96 by unit selector switch 94.This is because stipulate in the ATA specification: need in transmission before the instruction of LBA address, need to set in advance the LBA address in register.In addition, if the kind of instruction of input is the instruction that does not need the LBA address, unit selector switch 94 controls the first on-off circuit 96 then is so that latch cicuit 74 is connected with all storage unit.Thus, can transmit the instruction that does not need the LBA address to all storage unit.Be not need in the situation of instruction of LBA address in the kind of instruction of input, latch cicuit 74 also can not make the output delay of instruction.
In a single day unit selector switch 94 has controlled the first on-off circuit 96 according to the LBA address of input, just controls in the same manner therewith second switch circuit 98.Second switch circuit 98 is for the switch that switches the interrogation signal of data register.After second switch circuit 98 was switched, data-signal also was transmitted to the storage unit identical with the storage unit that has been transmitted the instruction that needs the LBA address.
Between second switch circuit 98 and register decision circuitry 78, be connected with state storage circuitry 79.In state storage circuitry 79, store the capacity (all sector numbers) of calmodulin binding domain CaM UA integral body, the device id of fabricator's information of expression memory storage 10.Usually, in the situation that require to obtain status information from host apparatus 80, from the storage unit return state information of selecting by second switch circuit 98.But, such as in the situation of all sector numbers that have by inquiry memory storages 10 such as " identification equipment " instructions or device id etc., the 80 return state information from this state storage circuitry 79 to host apparatus.Like this, if be can be from the formation of state storage circuitry 79 return state information, then can with can't tackle by each storage unit, correctly send host apparatus 80 to about the status information of memory storage 10 integral body.
Fig. 4 is the process flow diagram of address translation that expression realizes by address decoder 90 and address conversion circuit 92 flow process processing and processed by the selection to storage unit that unit selector switch 94 is realized.Below, should process referred to as " Single Component Management processing ".
Address conversion circuit 92 is judged the instruction (step S10) that whether needs the LBA address from the kind of the instruction of command decoder 91 inputs.As a result, if do not need the instruction (step S10: no) of LBA address, then address conversion circuit 92 does not carry out address translation and transmits the parameter that is input to an equipment/register etc. to all unit former states.On the other hand, unit selector switch 94 is selected all storage unit (step S20) and end process.Thus, same instruction is transmitted to all storage unit.In addition, as previously mentioned, inputted when not needing the instruction of LBA address when being judged as in step S10, address conversion circuit 92 also can similarly carry out location, address conversion as described below with the instruction that needs the LBA address.
In above-mentioned steps S10, if the instruction of input is the instruction (step S10: be) that needs the LBA address, the address decoder 90 LBA address n following value (step S30) of maximal value W (with reference to Fig. 2) of the LBA address of the first storage unit 30 whether of judging input then.If the n following value (step S30: be) that is maximal value W in LBA address then makes the LBA address m after changing by address conversion circuit 92 be the original LBA address n (step S40) from address decoder 90 inputs.And in this case, unit selector switch 94 selects the first storage unit 30 as the transmission destination (step S50) of instruction.
When judging that in above-mentioned steps S30 LBA address n is not value below the maximal value W of LBA address of the first storage unit 30 (step S30: no), address decoder 90 is judged the whether value (step S60) below the maximal value X sum (W+X) of maximal value W and the LBA address of the second storage unit 40 of the LBA address of the first storage unit 30 of LBA address n.If LBA address n is described and (W+X) following value (step S60: be), then make the value (step S70) that obtains behind the maximal value W of LBA address m for the LBA address that deducted the first storage unit 30 from LBA address n after changing by address conversion circuit 92.And in this case, unit selector switch 94 selects the second storage unit 40 as the transmission destination (step S80) of instruction.
When judging that in above-mentioned steps S60 LBA address n is not described and (W+X) (step S60: no) during following value, address decoder 90 is judged the whether value (step S90) below the maximal value Y sum (W+X+Y) of the LBA address of the maximal value X of the LBA address of maximal value W, second storage unit 40 of the LBA address of the first storage unit 30 and the 3rd storage unit 50 of LBA address n.If LBA address n is described and (W+X+Y) following value (step S90: be), then make LBA address m after changing by address conversion circuit 92 for to have deducted the value (step S100) that obtains behind W and the X from LBA address n.And in this case, unit selector switch 94 selects the 3rd storage unit 50 as the transmission destination (step S110) of instruction.
When judging that in above-mentioned steps S90 LBA address n is not described and (W+X+Y) (step S90: no) during following value, address decoder 90 is judged the whether value (step S120) below the maximal value Z sum (W+X+Y+Z) of the maximal value Y of the LBA address of maximal value X, the 3rd storage unit 50 of the LBA address of maximal value W, second storage unit 40 of the LBA address of the first storage unit 30 and the 4th storage unit 60 of LBA address n.If LBA address n is described and (W+X+Y+Z) following value (step S120: be), then make LBA address m after changing by address conversion circuit 92 for to have deducted the value (step S130) that obtains behind W, X and the Y from LBA address n.And in this case, unit selector switch 94 selects the 4th storage unit 60 as the transmission destination (step S140) of instruction.
When judging that in above-mentioned steps S120 LBA address n is not described and (W+X+Y+Z) (step S120: no) during following value, specifies the LBA address above calmodulin binding domain CaM UA.Therefore, the mistake that puts rules into practice is in this case processed (step S150).The mistake of regulation is processed and is referred to such as the discarded current processing such as instruction of inputting.Process according to Single Component Management described above, can only easily carry out the conversion of address and the selection of storage unit by simple comparison operation.
Formation and the action of the memory storage 10 of the present embodiment more than have been described.As mentioned above, the memory storage 10 of the present embodiment carries out address translation according to the initial distribution to calmodulin binding domain CaM UA as the mode of the two-value storer 31 of SLC type flash memory.Therefore, behind memory storage 10 file system format such by FAT16 or FAT32, in the file allocation table (hereinafter referred to as " FAT information ") of two-value storer 31 interior generations as the management information of data.In case FAT information is the management information that writes or wipe then can be rewritten continually of carrying out data.In the present embodiment, the SLC type flash memory that is higher than MLC type flash memory (multivalued storage 41～61) at the area configurations writing speed that writes such management information.Therefore, according to the present embodiment, realize high capacity by adopting MLC type flash memory, compared with the memory storage that is only consisted of by MLC type flash memory simultaneously, can improve significantly the writing speed of data.In addition, be 600nsec if write the time of FAT information to MLC type flash memory, then write the general 200nsec of being of time of FAT information to SLC type flash memory.
The comparative example of writing speed here, is described.As everyone knows, in management information, write the FAT information of two same contents according to FAT16 or FAT32.So, if the memory storage that only is made of MLC type flash memory, then the rewriting of first FAT information needs 600nsec, and the rewriting of second FAT information needs 600nsec, and the rewriting of data needs 600nsec.So, need as a whole time of 1800nsec.Relative therewith, in the present embodiment, owing to SLC type flash memory is used for writing the zone of FAT information, so the rewriting of first FAT information needs 200nsec, the rewriting of second FAT information needs 200nsec, and the rewriting of (in the multivalued storage) data needs 600nsec.So, as a whole, finished the rewriting of data by 1000nsec.That is, according to the present embodiment, for the memory storage that is only consisted of by MLC type flash memory, the rewriting time of data can be cut down about 45%.
In addition, but usually the number of rewrites of the data of SLC type flash memory is about 10～20 times of MLC type flash memory.Therefore, by as the present embodiment at the area configurations SLC type flash memory of writing the management information that rewritten continually of affiliation, can improve significantly the reliability of data storage.As a result, not only can be used as external memory, but also can the bootstrap driver that easily be used as operating system the same as hard disk in the past.
In addition, in the present embodiment, used the compact flash controller as the cell controller of controlling two-value storer or multivalued storage.Usually, the widespread use of compact flash is high, can control the flash memory of various characteristics.Therefore, if as the present embodiment, make each storage unit have the compact flash controller, even the flash memory that then adopts different manufacturers to make to each storage unit also can sponge the difference of characteristic and it is normally moved.As a result, can easily consist of the memory storage that has loaded in mixture two-value storer and multivalued storage.In addition, in the present embodiment, adopt the compact flash controller as cell controller, also can use the SD storer with controller or multimedia card controller.
In the present embodiment, the function that has of master controller 20 realizes by hardware mode.Relative therewith, also can realize by master controller 20 being constituted the microcomputer that is built-in with CPU, ROM and RAM the function of address above mentioned conversion or Single Component Management by the mode of software.In addition, also can control each storage unit by adopting the RAID chip to be used as master controller 20 and making this RAID chip cross over (spanning) action.
In addition, in the present embodiment, have altogether four storage unit, but to the not restriction of this quantity.Bottom line is to have storage unit and the storage unit with multivalued storage with two-value storer to get final product.
In addition, in the present embodiment, the capacity of two-value storer is the 1G byte, but also can followingly decide this capacity.For example, format memory storage 10 by FAT32, the memory capacity that makes the integral body of memory storage 10 is the x GB.For FAT32, each sector is the capacity of 4K byte under many circumstances, and therefore integral body is (x/4) 1,000,000 sector numbers.In addition, for FAT32, the data volume of needs 4 bytes in order to represent an address.Therefore, the capacity of each FAT informational needs x megabyte (=4 bytes * (x/4) 1,000,000).As mentioned above, for FAT32, write under many circumstances two FAT information, therefore adding up to needs (the management area of 2 * x) megabytes.In addition, as management information, not only record FAT information, but also therefore the information such as record Main Boot Record, directory entry need more management area as a whole.Here, enumerating concrete example describes.If the capacity of the integral body of memory storage 10 is 128 GB, then by above-mentioned computing method, the needed capacity of FAT information is 256 megabytes.And if add on this basis for the zone of recording Main Boot Record, directory entry etc., then integral body needs the two-value storer of the capacity about 500 megabytes.That is, for the zone (calmodulin binding domain CaM UA) of the integral body of memory storage 10, need at least the capacity of 0.5% two-value storer, if the capacity about 1% is arranged, then can be rich in surplus ground and come management information.Certainly, because the two-value storer has the characteristic better than multivalued storage aspect responsiveness and the reliability, therefore also can constitute the capacity above 1%.
B. the second embodiment:
Fig. 5 is that expression is as the key diagram of the concise and to the point formation of the memory storage of the second embodiment of the present invention.As shown in the figure, the memory storage 110 of the present embodiment comprises: master controller 20, the second storage unit 40 that the first storage unit 30 of two-value storer 31 is installed and multivalued storage 41 is installed.Identical with the first embodiment, master controller 20 comprises bus switching circuit 21 and Single Component Management circuit 122.Wherein, the Single Component Management circuit 122 of the present embodiment has following functions: according to address, data, the instruction from host apparatus 80 appointments, switch the object of the read-write of carrying out data between the first storage unit 30 and the second storage unit 40.
Fig. 6 is the key diagram of concept of the switching controls of the expression storage unit of being undertaken by Single Component Management circuit 122.In Fig. 6, begin to have represented successively the storage area UA2 of the integral body of the memory storage 110 when observing memory storage 110 from host apparatus 80, the storage area of the first storage unit 30, the storage area of the second storage unit 40 from the left side.
In the present embodiment, the storage area in the first storage unit 30 represents by the LBA address from " 0 " to " W ".On the other hand, the storage area in the second storage unit 40 represents by the LBA address from " 0 " to " X ".LBA address " X " is than the large value in LBA address " W ".
In the present embodiment, if specified LBA address from " 0 " to " W " from host apparatus 80, then Single Component Management circuit 122 switches to the first storage unit that two-value storer 31 has been installed with the object of the read-write of data.Relative therewith, if specified the LBA address that surpasses " W ", then Single Component Management circuit 122 switches to the second storage unit 40 that multivalued storage 41 is installed with the read-write object of data.That is, in the present embodiment, Single Component Management circuit 122 is by comparing to switch employed memory cell to LBA address and threshold value " W " from host apparatus 80 appointments.The result who carries out above-mentioned switching controls is: in the present embodiment, produce the zone (LBA address " 0 "～" W ") that is not used in the part of the second storage unit 40.
Fig. 7 is the block diagram that schematically shows the inside formation of Single Component Management circuit 122.As shown in the figure, the Single Component Management circuit 122 of the present embodiment comprises register decision circuitry 178, control switching circuit 194, the first on-off circuit 196, second switch circuit 198.
The first on-off circuit 196 makes according to the indication from control switching circuit 194 and is connected between bus switching circuit 21 and the first memory unit 30 or disconnects.
As shown in the figure, control switching circuit 194 comprises address decoder 190, address comparison circuit 192, size (size) register 179 and command decoder 191.
In sized registers 179, store the threshold value that the max cap. according to the first storage unit 30 determines.In the present embodiment, the max cap. of establishing the first storage unit 30 is the 512M byte, and the threshold value that is stored in the sized registers 179 is the LBA address of the capacity of the expression 480M byte slightly less than this max cap..This is because produce sometimes defect block (bad piece) in flash memory, therefore sometimes can't utilize all 512M bytes.Certainly, as threshold value, also can former state the LBA address of max cap. of storage expression the first storage unit 30.In addition, the 480M byte can be expressed as by the binary bit based on the LBA mode " 0000000011110000000000000000 ".Therefore, be the 480M byte if make threshold value, can whether be whether " 00000000 " has surpassed threshold value (480M byte) with the address of judging appointment according to the value of the most-significant byte from 28 of host apparatus 80 appointments long LBA addresses then.That is, address comparison circuit 192 described later can be only the high bit register of cylinder high 4 and in the situation of the value of not using the low bit register of cylinder or sector number register, easily judge whether surpassed threshold value by using 4 an equipment/register and 8.
The LBA address that 192 pairs of address decoders 190 of address comparison circuit are resolved and the threshold value that is stored in the sized registers 179 compare, and select the storage unit as the candidate of access object as shown in Figure 6 between the first storage unit 30 and the second storage unit 40.
Fig. 8 is the key diagram of the details of the change action that undertaken by control switching circuit 194 of expression.In the drawings, " switching " refer to the storage unit of being selected by address comparison circuit 192 is conducted interviews.Relative therewith, " simultaneously access " refers to that irrespectively the two carries out same access to the first storage unit 30 and the second storage unit 40 with the selection of address comparison circuit 192.
In addition, in Fig. 8, the situation of write command has been sent in " when writing " expression from host apparatus 80.In write command, comprise write order to the instruction of order register, to the write order of the data of data register, to the write order of the various parameters such as LBA address of other registers.In addition, " when reading " expression has been sent the situation of reading instruction from host apparatus 80.In reading instruction, comprise the order of reading in various states or data from storage unit.
As shown in Figure 8, as principle, the access of data register and order register is all carried out the storage unit of being selected by address comparison circuit 192 when writing and when reading.Relative therewith, the access of other registers is only carried out selecteed storage unit when reading, when writing, two storage unit are carried out same access.Register beyond data register and the order register mainly is the register that is used to specify the address.Therefore, as long as sent rightly to selecteed storage unit as data or the instruction of the object of writing, even when writing, write same address to the first storage unit 30 and the second storage unit 40 these two kinds of registers, can not bring any impact yet.
In Fig. 8, " exception 1 " represents following situation: by the result that 191 pairs of instructions of command decoder are resolved, the instruction that transmits from host apparatus 80 is the instruction of the operating state of the switched memory cells integral body such as idle instruction or standby command.In the situation that transmitted this instruction, the two transmits this instruction to control switching circuit 194 to the first storage unit 30 and the second storage unit 40 exceptionally.
In addition, in Fig. 8, " exception 2 " expression is read for the data capacity (whole sector number) of memory storage 110 by identification equipment instruction etc.In this case, control switching circuit 194 conducts interviews to the second storage unit 40 exceptionally.This is that in the present embodiment, the data capacity of memory storage 110 is consistent with the data capacity of the second storage unit 40 because as shown in Figure 6.
Formation and action as the memory storage 110 of the second embodiment more than have been described, memory storage 110 according to the present embodiment, can with the memory storage 10 of the first embodiment similarly to the initial region allocation SLC type flash memory of storage area, and in addition region allocation MLC type flash memory.Therefore, but the FAT information that number of rewrites is many, responsiveness is high SLC type flash memory storage can be rewritten continually.As a result, identical with the first embodiment, realized high capacity by adopting MLC type flash memory, compare with the memory storage that is only consisted of by MLC type flash memory simultaneously, can improve significantly the writing speed of data and the reliability of data storage.
In addition, according to the memory storage 110 of the present embodiment, can be used as it is from the address of host apparatus 80 appointments and two kinds of storage unit are carried out the read-write of data.As a result, owing to not needing circuit complicated, that carry out address translation, therefore can dwindle the circuit scale of master controller 20.As a result, can reduce manufacturing cost.
Various embodiment of the present invention more than has been described, but has the invention is not restricted to above-described embodiment, self-evidently can in the scope that does not break away from its purport, adopt various formations.For example, adopted in the above-described embodiments the USB interface of the interface that is connected with host apparatus as memory storage, but the kind of interface is not limited to this.Also can adopt the various interfaces such as IEEE1394 interface, serial ATA interface, Parallel ATA interface.
Claims (1)
1. memory storage, described memory storage be in the management information of the beginning record data of storage area, and can store data according to predetermined file system, and described memory storage comprises:
Memory cell with two-value flash memory, it has the first storage area, and every individual unit can be stored 2 kinds of values;
Memory cell with many-valued flash memory, it has the second storage area, and every individual unit can be stored the value more than 3 kinds; And
Control part, described the first storage area integral body is compared the zone that is disposed at beginning with described the second storage area, logic is in conjunction with described the first storage area and described the second storage area, and carries out the read-write of data as the calmodulin binding domain CaM for single storage area;
Described control part comprises the RAID chip, crosses over action by making this RAID chip, and described each memory cell is controlled.
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