CN101853214A - Memory storage - Google Patents
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- CN101853214A CN101853214A CN 201010154233 CN201010154233A CN101853214A CN 101853214 A CN101853214 A CN 101853214A CN 201010154233 CN201010154233 CN 201010154233 CN 201010154233 A CN201010154233 A CN 201010154233A CN 101853214 A CN101853214 A CN 101853214A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5641—Multilevel memory having cells with different number of storage levels
Abstract
The invention provides a kind of the two memory storage of advantage of SLC type flash memory and MLC type flash memory of having brought into play fully.Memory storage comprises: the two-value flash memory, have first storage area, and every individual unit can be stored 2 kinds of values; Many-valued flash memory has second storage area, and every individual unit can be stored the value more than 3 kinds; And control part, logic is in conjunction with first storage area and second storage area, and as carrying out data write for the calmodulin binding domain CaM of single storage area in the zone that first storage area is disposed at beginning.Store the management information of data in the beginning of storage area according to predetermined file system.
Description
It is 200810098116.8 that the application is based on application number, and the applying date is on May 13rd, 2008, and the application people is Babbilu Inc., and name is called the dividing an application of application for a patent for invention of " memory storage ".
Technical field
The present invention relates to be stored in the memory storage of the data of using in computing machine or the various electronic equipment.
Background technology
In recent years, as the external memory of computing machine, popularize for the storage card of representative, USB flash memory driver (USBflash drive) with compact flash (compactflash) (registered trademark, below identical).Be built-in with flash memory in these external memories, this flash memory is rewritable non-volatile ROM.The flash memory (for example, with reference to following patent documentation 1) that the SLC of being called as (Single Level Cell, single stage unit) type and MLC (Multi Level Cell, multi-level unit) type are arranged.
Patent documentation 1: the Japanese documentation spy opens the 2002-8380 communique.
SLC type flash memory is the storer that all the time is widely used, and is the every individual unit storer that can store 1 information (below be also referred to as " two-value storer ").Relative therewith, MLC type memory cell is the every individual unit storer that can store the information more than 2 (below be also referred to as " multivalued storage ").MLC type flash memory can have that 2/3rds state, electric weight residue have 1/3rd state by state, the electric weight residue that charging is got fully in each unit, these four kinds of states of state of being discharged fully and with the information of 2 of every individual unit storages.
Usually, but MLC type flash memory has few but the characteristics that memory capacity is bigger than SLC type of low speed action number of rewrites.On the other hand, but SLC type flash memory has many but the characteristics that memory capacity is littler than MLC type of high speed motion number of rewrites.
Summary of the invention
Invent problem to be solved
In view of the above problems, problem to be solved by this invention provides a kind of the two memory storage of advantage of characteristics of SLC type flash memory and MLC type flash memory of having brought into play.
The means that are used to deal with problems
In view of above-mentioned problem, the following formation of the memory storage of an embodiment of the invention.
Promptly, the invention provides a kind of memory storage, this memory storage is in the management information of the beginning record data of storage area, and can store data according to predetermined file system, described memory storage is characterised in that, comprise: the two-value flash memory, have first storage area, every individual unit can be stored 2 kinds of values; Many-valued flash memory has second storage area, and every individual unit can be stored the value more than 3 kinds; And control part, logic is in conjunction with described first storage area and described second storage area, and as carrying out data write for the calmodulin binding domain CaM of single storage area in the zone that described first storage area is disposed at beginning.
According to the memory storage of aforesaid way, first storage area that the two-value flash memory is had is disposed at the beginning of calmodulin binding domain CaM.Therefore, the management information of data such as file allocation table is written in the two-value flash memory.In case since file allocation table be carry out data write or wipe the management information that will be rewritten continually, therefore the two-value flash configuration by responsiveness being higher than many-valued flash memory is in the beginning of calmodulin binding domain CaM, compare by the memory storage that many-valued flash memory constitutes with Zone Full, can store data at high speed.In addition, but to compare number of rewrites many with many-valued flash memory because the two-value flash memory has, and therefore write the two-value flash memory by the file allocation table that will be rewritten continually, can improve reliability of data storage.Like this,, realized high capacity, simultaneously by also using the two-value flash memory to can be provided in the good memory storage of high speed and reliability aspect of action by using many-valued flash memory according to the memory storage of aforesaid way.
The memory storage of aforesaid way also can adopt following constituted mode, that is, described control part comprises: address translation portion, carry out the address translation between described calmodulin binding domain CaM and described first storage area and described second storage area; And selection portion, according to the result of described address translation, from described two-value flash memory and described many-valued flash memory, select described data write destination.According to this mode, can be according to the result of address translation and easily judge the data write destination.
The memory storage of aforesaid way also can adopt following constituted mode, promptly, described control part will undertaken by described address translation portion after the address after the conversion sends to described two-value flash memory and described many-valued flash memory, and the instruction that will be used to carry out described data write sends to described selecteed flash memory.
According to this mode, the address after all flash memories send conversion only sends instruction to selecteed flash memory then.According to this mode, because processing speed can be improved in the transmission destination of the address after not needing to select to change from two-value flash memory and many-valued flash memory therefore.
The memory storage of aforesaid way also can adopt following constituted mode, that is, described first storage area is more than the 0.5% and zone of arbitrary ratio of less than 100% that accounts for described calmodulin binding domain CaM.By first storage area is set at such zone, can reliably management information such as file allocation table be stored in the two-value flash memory.
The memory storage of aforesaid way also can adopt following constituted mode, that is, this memory storage is connected with host apparatus via predetermined interface, and described control part is according to carrying out described data write from the indication of described host apparatus.According to this mode, can be with external memory or the internal storage device of this memory storage as host apparatus.Interface as predetermined for example can use interfaces such as USB, IEEE1394, serial ATA, Parallel ATA.
The memory storage of aforesaid way also can adopt following constituted mode, that is, described control part returns the memory capacity of described calmodulin binding domain CaM when the inquiry of the memory capacity that receives this memory storage from described host apparatus.According to this mode, the capacity of calmodulin binding domain CaM integral body rather than the memory capacity that each flash memory had individually can be notified to host apparatus.
The memory storage of aforesaid way also can adopt following constituted mode, promptly, comprise a plurality of described many-valued flash memories, described control part in the zone that described first storage area is disposed at beginning logic in conjunction with described first storage area and a plurality of described second storage area.According to this mode, can have a plurality of many-valued flash memories, therefore can provide memory storage with jumbo storage area.
The present invention also can be applied to the memory storage of following mode.That is, this memory storage is in the management information of the beginning record data of storage area, and can store data according to predetermined file system, described memory storage is characterised in that, comprise: the two-value flash memory, have first storage area, every individual unit can be stored 2 kinds of values; Many-valued flash memory has second storage area bigger than described first storage area, and every individual unit can be stored the value more than 3 kinds; Comparing section is to comparing from the address of the host apparatus appointment that is connected with this memory storage with according to the predetermined threshold value that the max cap. of described first storage area has been determined; And control part, in described address is that described threshold value switches to described two-value flash memory with the data write destination under with the situation of interior address, under the situation of described address for the address that surpasses described threshold value described read-write destination is switched to described many-valued flash memory.
According to the memory storage of this mode, by carrying out and the so simple control in the read-write destination of switch data between many-valued flash memory and two-value flash memory can be carried out data write to these different flash memories of characteristic according to appointed address.As a result, realized high capacity, simultaneously by also using the two-value flash memory to can be provided in the good memory storage of high speed and reliability aspect of action by using many-valued flash memory.
The memory storage of aforesaid way also can adopt following constituted mode, promptly, described control part is under described read-write destination is switched to any one situation in described two-value flash memory and the described many-valued flash memory, and all former state is used the value of described address and described two-value flash memory or described many-valued flash memory are carried out data write.According to this mode, be the processing of the address of other systems owing to not needing to carry out with address translation by the host apparatus appointment, therefore can realize the simplification of handling.
The memory storage of aforesaid way also can adopt following constituted mode, that is, described control part returns the memory capacity of described second storage area when the inquiry of the memory capacity that receives this memory storage from described host apparatus.The maximum storage capacity of the memory storage of aforesaid way is consistent with second storage area.Therefore, can return the so simple processing of memory capacity of second storage area by former state and the memory capacity of this memory storage is notified to host apparatus.
Description of drawings
Fig. 1 is the key diagram of expression as the concise and to the point formation of the memory storage of first embodiment;
The key diagram of the notion of Fig. 2 address translation that to be expression undertaken by the Single Component Management circuit of first embodiment;
Fig. 3 schematically shows the block diagram that the inside of the Single Component Management circuit of first embodiment constitutes;
Fig. 4 is the process flow diagram that the Single Component Management among first embodiment is handled;
Fig. 5 is the key diagram of expression as the concise and to the point formation of the memory storage of second embodiment;
Fig. 6 is the key diagram of notion of the switching controls of the Single Component Management circuit of expression by second embodiment storage unit of carrying out;
Fig. 7 is the block diagram that schematically shows the inside formation of the Single Component Management circuit among second embodiment;
Fig. 8 is the key diagram of the details of the change action that carries out of the control switching circuit of expression by second embodiment.
Embodiment
Below, effect and effect for further clear and definite the invention described above illustrate embodiments of the present invention according to embodiment.
A. first embodiment:
Fig. 1 is the key diagram of expression as the concise and to the point formation of the memory storage 10 of embodiments of the invention.The memory storage 10 of present embodiment is connected with the host apparatus 80 that with the computing machine is representative via USB interface, is used as external memory.Host apparatus 80 formats memory storage 10 by the file system of stipulating (FAT16 or FAT32 etc.) and carries out data write.
As shown in the figure, memory storage 10 comprises master controller 20, also comprises first storage unit 30, second storage unit 40, the 3rd storage unit 50 and the 4th storage unit 60 that are connected and have respectively nand flash memory with this master controller 20 in addition.
Single Component Management circuit 22 has two-value storer and the storage area of multivalued storage and the function of operating as single storage area that logic is had in conjunction with each storage unit 30～60.Single Component Management circuit 22 carries out address translation according to LBA (Logical Block addressing, the LBA (Logical Block Addressing)) address of having been carried out the ATA signal after the conversion by bus switching circuit 21, realizes the logic combination of each storage unit 30～60 thus.LBA is meant all sectors of storage area is distributed continuous number and specified the mode of the sector that conducts interviews by this continuous number.The LBA address is represented by this continuous number." LBA address " is also referred to as " LBA parameter ".
Fig. 2 is the key diagram of the notion of the expression address translation of being undertaken by Single Component Management circuit 22.Represented storage area by each storage unit 30～60 of Single Component Management circuit 22 management in the left side of figure.As shown in the figure, in the present embodiment, the storage area in first storage unit 30 is represented by the LBA address from " 0 " to " W ".In addition, second storage unit 40 represents that by the LBA address from " 0 " to " X " the 3rd storage unit represents that by the LBA address from " 0 " to " Y " the 4th storage unit is represented by the LBA address from " 0 " to " Z ".
Represented in conjunction with the storage area behind the storage area of each storage unit 30～60 on the right side of Fig. 2.As shown in the figure, the storage area of the two-value storer 31 that Single Component Management circuit 22 is had first storage unit 30 is configured in the zone of beginning, disposes the storage area of the multivalued storage 41～61 that other storage unit 40～60 are had then.As shown in Figure 2, in conjunction with after storage area represent by the continuous LBA address of from " 0 " to " W+X+Y+Z ".By next like this in conjunction with storage area by Single Component Management circuit 22, host apparatus 80 can identify the storage areas in the memory storage 10 as the storage area of representing by the continuous LBA address of from " 0 " to " W+X+Y+Z ".In the following description, will in conjunction with after storage area be called " calmodulin binding domain CaM UA ".
Fig. 3 is the block diagram that schematically shows the inside formation of Single Component Management circuit 22.Single Component Management circuit 22 except carrying out above-mentioned address translation, also have will send from host apparatus 80 ATA instruction or the data function that sends each storage unit 30～60 to.In Fig. 3, represented to be used to realize that the inside of this transmitting function constitutes.
The cell controller 32～62 that each storage unit 30～60 is had comprises respectively follows the 8 kinds of registers ATA specification, that be called as the instruction block register.These 8 kinds of registers are called: (1) characteristic register, (2) sector number register, (3) equipment/head (head) register, the high bit register of (4) cylinder, the low bit register of (5) cylinder, (6) sector number register, (7) order register, (8) data register.Cell controller 32～62 is controlled data write to two-value storer or multivalued storage according to the various parameters that are provided with in these registers.Host apparatus 80 will send to memory storage 10 to the interrogation signal of these registers when reading and writing data.
When via USB interface and bus switching circuit 21 when host apparatus 80 receives above-mentioned interrogation signal, Single Component Management circuit 22 changes transfer approach to the interrogation signal of each storage unit 30～60 according to the kind as the register of access object.Single Component Management circuit 22 comprises the register decision circuitry 78 that is used to judge as the kind of the register of access object.
Register decision circuitry 78 is according to the state from the address signal A0～A2 of bus switching circuit 21 inputs, judges kind as the register of access object based on the ATA specification.For example as shown in the figure, be that " 0 ", address signal A0 are " 1 " if address signal A2 is " 0 ", address signal A1, then register decision circuitry 78 can be judged the interrogation signal of having imported the characteristic register.
Under situation about receiving from host apparatus 80 interrogation signal of characteristic register and sector number register, Single Component Management circuit 22 passes through this interrogation signal former state, sends this interrogation signal to all memory cells 30～60.This is because these registers are not the registers that is used for directly specifying the position in the calmodulin binding domain CaM UA.Specifically, the characteristic register is to be used for instructing the register of specifying various parameters, sector number register to be the registers that is used for specifying when a plurality of sector of connected reference its sector number according to ATA.An equipment described later/register, the high bit register of cylinder, the low bit register of cylinder, sector number register are used in the appointment to " initial sector " during about connected reference.
An equipment/register, the high bit register of cylinder, the low bit register of cylinder, sector number register are the registers that is used to specify the position (sector) in the calmodulin binding domain CaM UA.The part of the LBA address of the sector in these registers are imported expression calmodulin binding domain CaM UA respectively.Specifically, if the LBA address is 28 long parameters, then to sector number register input from the 0th to the 7th rank, to the low bit register input of cylinder from the 8th to the 15th rank.In addition, to the input of the high bit register of cylinder from the 16th to the 23rd rank, to an equipment/register input from the 24th to the 27th rank.When the interrogation signal that receives these registers, Single Component Management circuit 22 temporarily with this signal latch in latch cicuit 70～73.
The interrogation signal that is latched in the latch cicuit 70～73 is transfused to address decoder 90.It is the function of 28 long LBA addresses that address decoder 90 has being stored in discretely that LBA address in each latch cicuit 70～73 combines and restore.In addition, address decoder 90 has the function that the maximum sector number to the LBA address after restoring and each storage unit compares.The back will explain this function.
Order register is the register that is used to specify based on the various instructions of ATA specification.As such instruction, for example have and read in reading the sector instruction, writing the sector instruction of data from the sector of appointment to what the sector of appointment write data.When the command signal that receives order register, Single Component Management circuit 22 inputs to command decoder 91 and latch cicuit 74 with this signal.
When having imported command signal, command decoder 91 is judged the kind of the instruction of input, and this judged result is exported to address conversion circuit 92 and unit selector switch 94.The command signal that is input to latch cicuit 74 remained in the latch cicuit 74 before the output indication that has from unit selector switch 94.
It is the function of the LBA address of each memory cell 30～60 that address conversion circuit 92 has the LBA address translation about calmodulin binding domain CaM UA as shown in Figure 2, that will import from address decoder 90.Specifically, address conversion circuit 92 is from address decoder 90 input LBA addresses, and from the kind of command decoder 91 input instructions.Then, whether the kind of the instruction of judgement input is the instruction that needs the LBA address.Need the instruction of LBA address to be meant usually address (sector) to be specified and the instruction of certain visit is carried out in the address of appointment, " reading the sector instruction ", " writing the sector instruction ", " repeatedly reading instruction ", " repeatedly write command ", " reading the DMA instruction ", " writing the DMA instruction ", " instruction of read check sector ", " look-up command " etc. are for example arranged.If address conversion circuit 92 judges that the kind of the instruction of input is the instruction that needs the LBA address, to be the LBA address (back will illustrate conversion method) of each storage unit then, and the LBA address after will changing send all storage unit 30～60 to from the LBA address translation of address decoder 90 inputs.As described later, master controller 20 can not transmit the ATA instruction that needs the LBA address to a plurality of storage unit simultaneously, and therefore the LBA address after the conversion can send all storage unit 30～60 to.Thus, address conversion circuit 92 can omit the processing of selecting to transmit the destination.Certainly, also can be only LBA address after this storage unit transmits conversion.
If from the kind of the instruction of command decoder 91 input is the instruction that does not need the LBA address, then address conversion circuit 92 will send all storage unit 30～60 to from the parameter former state of address decoder 90 inputs.This is because under for the situation of instruction that does not need the LBA address, and the interrogation signal that is input to an equipment/register etc. is not limited to represent the LBA address.Do not need the instruction of LBA address to be meant the instruction of under the situation of assigned address (sector) not, flash memory being carried out certain operation, " identification equipment (identify device) instruction ", " the characteristic instruction is set ", " checking the power mode instruction ", " sleep instruction ", " standby command ", " idle instruction " etc. are for example arranged.In the kind from the instruction of command decoder 91 input is not need under the situation of instruction of LBA address, address conversion circuit 92 also can with the instruction that needs the LBA address LBA address after storage unit 30～60 transmits conversion similarly.This is because not need the instruction of LBA address be the instruction that no matter has or not the LBA address all can be performed.Certainly, also can be to change but do not transmit the formation of the LBA address after the conversion.
LBA address after the timing that the output of each unit remains on the command signal in the latch cicuit 74 is set to address translation is sent to each storage unit and has been finished timing after the switching of first on-off circuit 96 by unit selector switch 94 from address conversion circuit 92.This is because stipulate in the ATA specification: need in transmission before the instruction of LBA address, need to set in advance the LBA address in register.In addition, if the kind of instruction of input is the instruction that does not need the LBA address, unit selector switch 94 controls first on-off circuit 96 then is so that latch cicuit 74 is connected with all storage unit.Thus, can transmit the instruction that does not need the LBA address to all storage unit.In the kind of instruction of input is not need under the situation of instruction of LBA address, and latch cicuit 74 also can not make the output delay of instruction.
In a single day unit selector switch 94 has controlled first on-off circuit 96 according to the LBA address of input, just controls second switch circuit 98 therewith in the same manner.Second switch circuit 98 is the switches that are used to switch to the interrogation signal of data register.After second switch circuit 98 was switched, data-signal also was transmitted to the storage unit identical with the storage unit that has been transmitted the instruction that needs the LBA address.
Between second switch circuit 98 and register decision circuitry 78, be connected with state storage circuitry 79.In state storage circuitry 79, store the capacity (all sector numbers) of calmodulin binding domain CaM UA integral body, the device id of fabricator's information of expression memory storage 10.Usually, requiring to obtain under the situation of status information, from the storage unit return state information of selecting by second switch circuit 98 from host apparatus 80.But, for example under situation by all sector numbers that inquiry memory storage 10 had such as " identification equipment " instruction or device id etc., from this state storage circuitry 79 to host apparatus 80 return state information.Like this, if be can be from the formation of state storage circuitry 79 return state information, then can with can't tackle by each storage unit, correctly send host apparatus 80 to about the status information of memory storage 10 integral body.
Fig. 4 is the process flow diagram of address translation that expression realizes by address decoder 90 and address conversion circuit 92 flow process handling and handled by the selection to storage unit that unit selector switch 94 is realized.Below, this processing is abbreviated as " Single Component Management processing ".
Address conversion circuit 92 judges whether from the kind of the instruction of command decoder 91 inputs are the instructions (step S10) that need the LBA address.As a result, if do not need the instruction (step S10: not) of LBA address, then address conversion circuit 92 does not carry out address translation and transmits the parameter that is input to an equipment/register etc. to all unit former states.On the other hand, unit selector switch 94 is selected all storage unit (step S20) and end process.Thus, same instruction is transmitted to all storage unit.In addition, as previously mentioned, imported when not needing the instruction of LBA address when being judged as in step S10, address conversion circuit 92 also can similarly carry out location, address conversion as described below with the instruction that needs the LBA address.
In above-mentioned steps S10, if the instruction of input is the instruction (step S10: be) that needs the LBA address, then address decoder 90 judges whether the LBA address n of input is the following value (step S30) of maximal value W (with reference to Fig. 2) of the LBA address of first storage unit 30.If the n following value (step S30: be) that is maximal value W in LBA address then makes the LBA address m after changing by address conversion circuit 92 be the original LBA address n (step S40) from address decoder 90 inputs.And in this case, unit selector switch 94 is selected the transmission destination (step S50) of first storage unit 30 as instruction.
(step S30: not), address decoder 90 judges that whether LBA address n is the value (step S60) below the maximal value X sum (W+X) of LBA address of the maximal value W of LBA address of first storage unit 30 and second storage unit 40 when judging that in above-mentioned steps S30 LBA address n is not a value below the maximal value W of LBA address of first storage unit 30.If LBA address n is described and (W+X) following value (step S60: be), then make the value (step S70) that obtains behind the maximal value W of LBA address m after changing by address conversion circuit 92 for the LBA address that deducted first storage unit 30 from LBA address n.And in this case, unit selector switch 94 is selected the transmission destination (step S80) of second storage unit 40 as instruction.
When judging that in above-mentioned steps S60 LBA address n is not described and (W+X) during following value (step S60: not), address decoder 90 judges that whether LBA address n is the value (step S90) below the maximal value Y sum (W+X+Y) of LBA address of the maximal value X of LBA address of maximal value W, second storage unit 40 of the LBA address of first storage unit 30 and the 3rd storage unit 50.If LBA address n is described and (W+X+Y) following value (step S90: be), then make LBA address m after changing by address conversion circuit 92 for to have deducted the value (step S100) that obtains behind W and the X from LBA address n.And in this case, unit selector switch 94 is selected the transmission destination (step S110) of the 3rd storage unit 50 as instruction.
When judging that in above-mentioned steps S90 LBA address n is not described and (W+X+Y) during following value (step S90: not), address decoder 90 judges that whether LBA address n is the value (step S120) below the maximal value Z sum (W+X+Y+Z) of the maximal value Y of LBA address of maximal value X, the 3rd storage unit 50 of LBA address of maximal value W, second storage unit 40 of the LBA address of first storage unit 30 and the 4th storage unit 60.If LBA address n is described and (W+X+Y+Z) following value (step S120: be), then make LBA address m after changing by address conversion circuit 92 for to have deducted the value (step S130) that obtains behind W, X and the Y from LBA address n.And in this case, unit selector switch 94 is selected the transmission destination (step S140) of the 4th storage unit 60 as instruction.
When judging that in above-mentioned steps S120 LBA address n is not described and (W+X+Y+Z) (step S120: not), specify the LBA address above calmodulin binding domain CaM UA during following value.Therefore, the fault processing that puts rules into practice in this case (step S150).The fault processing of regulation is meant for example discarded current processing of importing such as instruction.Single Component Management according to above explanation is handled, and can only easily carry out the conversion of address and the selection of storage unit by simple comparison operation.
The formation and the action of the memory storage 10 of present embodiment more than have been described.As mentioned above, the memory storage 10 of present embodiment carries out address translation according to the initial distribution to calmodulin binding domain CaM UA as the mode of the two-value storer 31 of SLC type flash memory.Therefore, after memory storage 10 file system formatization such, in two-value storer 31, generate file allocation table (hereinafter referred to as " FAT information ") as the management information of data by FAT16 or FAT32.In case FAT information is the management information that writes or wipe then can be rewritten continually of carrying out data.In the present embodiment, the SLC type flash memory that is higher than MLC type flash memory (multivalued storage 41～61) at the area configurations writing speed that writes such management information.Therefore,, realized high capacity, compared with the memory storage that only constitutes simultaneously, can improve the writing speed of data significantly by MLC type flash memory by adopting MLC type flash memory according to present embodiment.In addition, be 600nsec, then write the general 200nsec of being of time of FAT information to SLC type flash memory if write the time of FAT information to MLC type flash memory.
The comparative example of writing speed here, is described.As everyone knows, in management information, write the FAT information of two same contents according to FAT16 or FAT32.So, if the memory storage that is made of MLC type flash memory only, then the rewriting of first FAT information needs 600nsec, and the rewriting of second FAT information needs 600nsec, and the rewriting of data needs 600nsec.So, need time of 1800nsec as a whole.Relative therewith, in the present embodiment, owing to the zone that SLC type flash memory is used to write FAT information, so the rewriting of first FAT information needs 200nsec, the rewriting of second FAT information needs 200nsec, and the rewriting of (in the multivalued storage) data needs 600nsec.So, as a whole, finished the rewriting of data by 1000nsec.That is,,, the rewriting time of data can be cut down about 45% for the memory storage that only constitutes by MLC type flash memory according to present embodiment.
In addition, but usually the number of rewrites of the data of SLC type flash memory be about 10～20 times of MLC type flash memory.Therefore, by as present embodiment at the area configurations SLC type flash memory of writing the management information that affiliation rewritten continually, can improve reliability of data storage significantly.As a result, not only can be used as external memory, but also can the same bootstrap driver that easily is used as operating system with hard disk in the past.
In addition, in the present embodiment, used the compact flash controller as the cell controller of controlling two-value storer or multivalued storage.Usually, the widespread use height of compact flash can be controlled the flash memory of various characteristics.Therefore, if as present embodiment, make each storage unit have the compact flash controller, even the flash memory that adopts different manufacturers to make to each storage unit then also can sponge the difference of characteristic and it is normally moved.As a result, can easily constitute the memory storage that has loaded in mixture two-value storer and multivalued storage.In addition, in the present embodiment, adopted the compact flash controller, also can use the SD storer with controller or multimedia card controller as cell controller.
In the present embodiment, the function that had of master controller 20 realizes by hardware mode.Relative therewith, also can be by master controller 20 being constituted the microcomputer that is built-in with CPU, ROM and RAM the function that realizes above-mentioned address translation or Single Component Management by the mode of software.In addition, also can control each storage unit by adopting the RAID chip to be used as master controller 20 and making this RAID chip cross over (spanning) action.
In addition, in the present embodiment, have four storage unit altogether, but to this quantity without limits.Bottom line is to have a storage unit and the storage unit with multivalued storage with two-value storer to get final product.
In addition, in the present embodiment, the capacity of two-value storer is the 1G byte, but also can followingly decide this capacity.For example, format memory storage 10 by FAT32, the memory capacity that makes the integral body of memory storage 10 is the x GB.For FAT32, each sector is the capacity of 4K byte under many circumstances, and therefore integral body is (x/4) 1,000,000 sector numbers.In addition, for FAT32, the data volume of needs 4 bytes in order to represent an address.Therefore, the capacity of each FAT informational needs x megabyte (=4 bytes * (x/4) 1,000,000).As mentioned above, for FAT32, write two FAT information under many circumstances, therefore adding up to needs (the management area of 2 * x) megabytes.In addition,, not only write down FAT information, but also therefore information such as record Main Boot Record, directory entry need more management area as a whole as management information.Here, enumerating concrete example describes.If the capacity of the integral body of memory storage 10 is 128 GB, then by the aforementioned calculation method, the needed capacity of FAT information is 256 megabytes.And, if add the zone that is used to write down Main Boot Record, directory entry etc. on this basis, the then whole two-value storer that needs the capacity about 500 megabytes.That is,, need the capacity of 0.5% two-value storer at least,, then can be rich in surplus ground and come management information if the capacity about 1% is arranged for the zone (calmodulin binding domain CaM UA) of the integral body of memory storage 10.Certainly, because the two-value storer has than multivalued storage excellent characteristic aspect responsiveness and the reliability, therefore also can constitute capacity above 1%.
B. second embodiment:
Fig. 5 is the key diagram of expression as the concise and to the point formation of the memory storage of the second embodiment of the present invention.As shown in the figure, the memory storage 110 of present embodiment comprises: master controller 20, second storage unit 40 that first storage unit 30 of two-value storer 31 is installed and multivalued storage 41 is installed.Identical with first embodiment, master controller 20 comprises bus switching circuit 21 and Single Component Management circuit 122.Wherein, the Single Component Management circuit 122 of present embodiment has following function: according to address, data, the instruction from host apparatus 80 appointments, switch the object that carries out data write between first storage unit 30 and second storage unit 40.
Fig. 6 is the key diagram of notion of the switching controls of the expression storage unit of being undertaken by Single Component Management circuit 122.In Fig. 6, begin from the left side to have represented successively when the storage area UA2 of the integral body of the memory storage 110 when host apparatus 80 is observed memory storages 110, the storage area of first storage unit 30, the storage area of second storage unit 40.
In the present embodiment, the storage area in first storage unit 30 is represented by the LBA address from " 0 " to " W ".On the other hand, the storage area in second storage unit 40 is represented by the LBA address from " 0 " to " X ".LBA address " X " is than the big value in LBA address " W ".
In the present embodiment, if specified LBA address from " 0 " to " W " from host apparatus 80, then Single Component Management circuit 122 switches to first storage unit that two-value storer 31 has been installed with the object of data write.Relative therewith, if specified the LBA address that surpasses " W ", then Single Component Management circuit 122 switches to the data write object second storage unit 40 that multivalued storage 41 is installed.That is, in the present embodiment, Single Component Management circuit 122 is by switching employed memory cell to comparing from the LBA address of host apparatus 80 appointments and threshold value " W ".The result who carries out above-mentioned switching controls is: in the present embodiment, produce the zone (LBA address " 0 "～" W ") that is not used in the part of second storage unit 40.
Fig. 7 is the block diagram that schematically shows the inside formation of Single Component Management circuit 122.As shown in the figure, the Single Component Management circuit 122 of present embodiment comprises register decision circuitry 178, control switching circuit 194, first on-off circuit 196, second switch circuit 198.
Register decision circuitry 178 is connected with bus switching circuit 21 shown in Figure 5.Identical with first embodiment, register decision circuitry 178 is according to the state from the address signal A0～A2 of bus switching circuit 21 inputs, judges kind as the register of access object based on the ATA specification.Then, the kind according to the register of judging will send control switching circuit 194 from the interrogation signal that bus switching circuit 21 receives to.
Control switching circuit 194 carries out following control: according to register decision circuitry 178 judge as the kind of the register of access object with from address, data, the instruction of host apparatus 80 appointments, between first storage unit 30 and second storage unit 40, switch storage unit as access object.
First on-off circuit 196 makes according to the indication from control switching circuit 194 and is connected between bus switching circuit 21 and the first memory unit 30 or disconnects.
Second switch circuit 198 makes according to the indication from control switching circuit 194 and is connected between bus switching circuit 21 and second storage unit 40 or disconnects.
As shown in the figure, control switching circuit 194 comprises address decoder 190, address comparison circuit 192, size (size) register 179 and command decoder 191.
Address decoder 190 is according to the interrogation signal to an equipment/register, the high bit register of cylinder, the low bit register of cylinder, sector number register, resolves the specified LBA address of host apparatus 80.In addition, 191 pairs of instructions from host apparatus 80 indications of command decoder are resolved.
In sized registers 179, store the threshold value that the max cap. according to first storage unit 30 determines.In the present embodiment, the max cap. of establishing first storage unit 30 is the 512M byte, and the threshold value that is stored in the sized registers 179 is the LBA address of the capacity of the expression 480M byte slightly littler than this max cap..This is because produce defect block (bad piece) sometimes in flash memory, therefore can't utilize all 512M bytes sometimes.Certainly, as threshold value, the LBA address of max cap. that also can former state storage representation first storage unit 30.In addition, the 480M byte can be expressed as " 0000000011110000000000000000 " by the binary bit based on the LBA mode.Therefore, be the 480M byte if make threshold value, can whether be whether " 00000000 " has surpassed threshold value (480M byte) with the address of judging appointment then according to the value of the most-significant byte from 28 of host apparatus 80 appointments long LBA addresses.That is, address comparison circuit 192 described later can be only the high bit register of cylinder high 4 and under the situation of the value of not using low bit register of cylinder or sector number register, easily judge whether surpassed threshold value by using an equipment/register of 4 and 8.
LBA address that 192 pairs of address decoders 190 of address comparison circuit are resolved and the threshold value that is stored in the sized registers 179 compare, and select the storage unit as the candidate of access object as shown in Figure 6 between first storage unit 30 and second storage unit 40.
Fig. 8 is the key diagram of the details of the change action that undertaken by control switching circuit 194 of expression.In the drawings, " switching " be meant that the storage unit to being selected by address comparison circuit 192 conducts interviews.Relative therewith, " visit " simultaneously is meant that irrespectively the two carries out same visit to first storage unit 30 and second storage unit 40 with the selection of address comparison circuit 192.
In addition, in Fig. 8, the situation of write command has been sent in " when writing " expression from host apparatus 80.In write command, comprise write order to the instruction of order register, to the write order of the data of data register, to the write order of the various parameters such as LBA address of other registers.In addition, " when reading " expression has been sent situation about reading instruction from host apparatus 80.In reading instruction, comprise the order of reading in various states or data from storage unit.
As shown in Figure 8, as principle, the visit of data register and order register is all carried out the storage unit of being selected by address comparison circuit 192 when writing and when reading.Relative therewith, the visit of other registers is only carried out selecteed storage unit when reading, when writing, two storage unit are carried out same visit.Register beyond data register and the order register mainly is the register that is used to specify the address.Therefore, as long as sent to selecteed storage unit rightly,, can not bring any influence even when writing, write same address to first storage unit 30 and second storage unit, 40 these two kinds of registers as the data or the instruction of the object of writing yet.
In Fig. 8, " exception 1 " represents following situation: by the result that 191 pairs of instructions of command decoder are resolved, the instruction that transmits from host apparatus 80 is the instruction of the operating state of switched memory cells integral body such as idle instruction or standby command.Under the situation that has transmitted this instruction, the two transmits this instruction to control switching circuit 194 to first storage unit 30 and second storage unit 40 exceptionally.
In addition, in Fig. 8, " exception 2 " expression is read at the data capacity (all sector numbers) of memory storage 110 by identification equipment instruction etc.In this case, control switching circuit 194 conducts interviews to second storage unit 40 exceptionally.This is that in the present embodiment, the data capacity of memory storage 110 is consistent with the data capacity of second storage unit 40 because as shown in Figure 6.
Formation and action as the memory storage 110 of second embodiment more than have been described, memory storage 110 according to present embodiment, can with the memory storage 10 of first embodiment similarly to the initial region allocation SLC type flash memory of storage area, and in addition region allocation MLC type flash memory.Therefore, but the FAT information that number of rewrites is many, responsiveness is high SLC type flash memory storage can be rewritten continually.As a result, identical with first embodiment, realized high capacity by adopting MLC type flash memory, compare with the memory storage that only constitutes simultaneously by MLC type flash memory, can improve the writing speed and the reliability of data storage of data significantly.
In addition, according to the memory storage 110 of present embodiment, can be used as it is from the address of host apparatus 80 appointments and two kinds of storage unit are carried out data write.As a result, owing to do not need circuit complicated, that carry out address translation, therefore can dwindle the circuit scale of master controller 20.As a result, can reduce manufacturing cost.
Various embodiment of the present invention more than has been described, but has the invention is not restricted to the foregoing description, self-evidently can in the scope that does not break away from its purport, adopt various formations.For example, adopted the USB interface of the interface that is connected with host apparatus as memory storage in the above-described embodiments, but the kind of interface is not limited thereto.Also can adopt various interfaces such as IEEE1394 interface, serial ATA interface, Parallel ATA interface.
Claims (2)
1. a memory storage can be stored data according to predetermined file system, and described memory storage comprises:
The two-value flash memory has first storage area, and every individual unit can be stored 2 kinds of values;
Many-valued flash memory has second storage area, and every individual unit can be stored the value more than 3 kinds; And
Control part, logic be in conjunction with described first storage area and described second storage area, and carry out data write as the calmodulin binding domain CaM for single storage area;
Described control part comprises the RAID chip, makes described two-value flash memory and described many-valued flash memory cross over action by this RAID chip, and logic is in conjunction with described first storage area and described second storage area thus.
2. memory storage as claimed in claim 1, wherein,
Described predetermined file system is the file system in the management information of the beginning record data of described calmodulin binding domain CaM,
Described control part is compared the zone that is disposed at beginning with the described first storage area integral body with described second storage area, and logic is in conjunction with described first storage area and described second storage area simultaneously.
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| JP2008004691A JP4781373B2 (en) | 2007-05-14 | 2008-01-11 | Storage device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103019882A (en) * | 2012-11-12 | 2013-04-03 | 记忆科技(深圳)有限公司 | RAID4 (redundant array of independent disks 4) system of solid-state disc |
Families Citing this family (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101751982B (en) * | 2008-12-12 | 2014-08-13 | 苏州亮智科技有限公司 | Connection method between flesh memory controller and flesh memory chip in flesh memory storing device |
| CN101814318B (en) * | 2009-02-25 | 2013-05-01 | 群联电子股份有限公司 | Multi level cell NAND flash storage system as well as controller and access method thereof |
| US20100262773A1 (en) * | 2009-04-08 | 2010-10-14 | Google Inc. | Data striping in a flash memory data storage device |
| CN101866678A (en) * | 2009-04-17 | 2010-10-20 | 常州南基天盛科技有限公司 | Flash disk |
| JP5330136B2 (en) * | 2009-07-22 | 2013-10-30 | 株式会社東芝 | Semiconductor memory device |
| US8868853B2 (en) | 2009-08-12 | 2014-10-21 | Nec Corporation | Data processing device, data recording method and data recording program |
| JP5027198B2 (en) * | 2009-10-08 | 2012-09-19 | 技嘉科技股▲ふん▼有限公司 | Flash memory access device and access method |
| JP2011145838A (en) | 2010-01-13 | 2011-07-28 | Toshiba Corp | Storage device management device and method for managing storage device |
| CN102142277A (en) * | 2010-01-28 | 2011-08-03 | 深圳市江波龙电子有限公司 | Memory and memory read-write control method and system |
| CN102385553A (en) * | 2010-08-31 | 2012-03-21 | 点序科技股份有限公司 | Access device and access method for flash memory |
| CN102324249B (en) * | 2011-09-09 | 2013-10-30 | 黑龙江大学 | Bi-multi-converting circuit of embedded DRAM of K value storing unit and constructing method thereof |
| CN103748565A (en) * | 2012-08-16 | 2014-04-23 | 华为终端有限公司 | Terminal and file access method therefor |
| CN103077121B (en) * | 2013-01-07 | 2016-01-27 | 深圳市江波龙电子有限公司 | The method of data management in a kind of flash memory device and device |
| CN103914410B (en) * | 2013-01-08 | 2020-01-31 | 联想(北京)有限公司 | Storage device, electronic apparatus, and data access method |
| CN103164344B (en) * | 2013-03-12 | 2015-09-16 | 深圳市江波龙电子有限公司 | The method of data management in a kind of flash memory device and device |
| CN103246615B (en) * | 2013-04-24 | 2015-09-16 | 深圳市江波龙电子有限公司 | The method of data management in a kind of flash memory device and device |
| CN106650901A (en) * | 2016-12-31 | 2017-05-10 | 重庆工业职业技术学院 | Rotary switching mobile memory equipped with two independent storage devices |
| CN108228478A (en) * | 2018-01-05 | 2018-06-29 | 湖南国科微电子股份有限公司 | A kind of raising method and device of SSD write performances |
| US10809942B2 (en) * | 2018-03-21 | 2020-10-20 | Micron Technology, Inc. | Latency-based storage in a hybrid memory system |
| US10705963B2 (en) * | 2018-03-21 | 2020-07-07 | Micron Technology, Inc. | Latency-based storage in a hybrid memory system |
| JP2019179455A (en) | 2018-03-30 | 2019-10-17 | 東芝メモリ株式会社 | Storage device and computer system |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3807012B2 (en) * | 1997-03-21 | 2006-08-09 | セイコーエプソン株式会社 | Storage device |
| JPH1131102A (en) * | 1997-07-14 | 1999-02-02 | Toshiba Corp | Data storage system and access control method applied to the system |
| JPH11176178A (en) * | 1997-12-15 | 1999-07-02 | Sony Corp | Non-volatile semiconductor storage and ic memory card using it |
| JP2000173281A (en) * | 1998-12-04 | 2000-06-23 | Sony Corp | Semiconductor memory |
| JP2001306393A (en) * | 2000-04-20 | 2001-11-02 | Mitsubishi Electric Corp | Storage device |
| JP2003015942A (en) * | 2001-07-03 | 2003-01-17 | Casio Comput Co Ltd | Method of writing data into memory, data write processing program and data write device |
| US7554842B2 (en) * | 2001-09-17 | 2009-06-30 | Sandisk Corporation | Multi-purpose non-volatile memory card |
| US6807106B2 (en) * | 2001-12-14 | 2004-10-19 | Sandisk Corporation | Hybrid density memory card |
| JP2006048746A (en) * | 2004-07-30 | 2006-02-16 | Renesas Technology Corp | Memory card |
| US7877539B2 (en) * | 2005-02-16 | 2011-01-25 | Sandisk Corporation | Direct data file storage in flash memories |
| US20060184719A1 (en) * | 2005-02-16 | 2006-08-17 | Sinclair Alan W | Direct data file storage implementation techniques in flash memories |
| US8055833B2 (en) * | 2006-10-05 | 2011-11-08 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
| US7752382B2 (en) * | 2005-09-09 | 2010-07-06 | Sandisk Il Ltd | Flash memory storage system and method |
| US8521945B2 (en) * | 2005-09-29 | 2013-08-27 | Trek 2000 International Ltd. | Portable data storage using SLC and MLC flash memory |
| US7406578B2 (en) * | 2005-09-30 | 2008-07-29 | Xiotech Corporation | Method, apparatus and program storage device for providing virtual disk service (VDS) hints based storage |
-
2008
- 2008-01-11 JP JP2008004691A patent/JP4781373B2/en active Active
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- 2008-05-13 TW TW97117576A patent/TW200903493A/en unknown
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103019882A (en) * | 2012-11-12 | 2013-04-03 | 记忆科技(深圳)有限公司 | RAID4 (redundant array of independent disks 4) system of solid-state disc |
| CN103019882B (en) * | 2012-11-12 | 2016-02-24 | 记忆科技(深圳)有限公司 | The RAID4 system of solid state hard disc |
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| JP4781373B2 (en) | 2011-09-28 |
| CN101853694B (en) | 2013-06-26 |
| CN101853207A (en) | 2010-10-06 |
| CN101853207B (en) | 2012-10-31 |
| JP2008310793A (en) | 2008-12-25 |
| TW200903493A (en) | 2009-01-16 |
| CN101853214B (en) | 2013-04-24 |
| TWI378454B (en) | 2012-12-01 |
| CN101308698B (en) | 2010-06-16 |
| CN101853694A (en) | 2010-10-06 |
| CN101308698A (en) | 2008-11-19 |
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