CN104935298B - The rest-set flip-flop of silicon substrate low-leakage current cantilever beam gate MOSFET nor gate - Google Patents
The rest-set flip-flop of silicon substrate low-leakage current cantilever beam gate MOSFET nor gate Download PDFInfo
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- CN104935298B CN104935298B CN201510379370.5A CN201510379370A CN104935298B CN 104935298 B CN104935298 B CN 104935298B CN 201510379370 A CN201510379370 A CN 201510379370A CN 104935298 B CN104935298 B CN 104935298B
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 30
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 30
- 239000010703 silicon Substances 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 title claims abstract description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 44
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 22
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 4
- 239000004408 titanium dioxide Substances 0.000 claims description 3
- 206010034133 Pathogen resistance Diseases 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 238000013461 design Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- VDGJOQCBCPGFFD-UHFFFAOYSA-N oxygen(2-) silicon(4+) titanium(4+) Chemical compound [Si+4].[O-2].[O-2].[Ti+4] VDGJOQCBCPGFFD-UHFFFAOYSA-N 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
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Abstract
The rest-set flip-flop of silicon substrate low-leakage current cantilever beam gate MOSFET nor gate of the invention includes the first nor gate (G1) being made up of the first cantilever beam grid NMOS tube (1) and the second cantilever beam grid NMOS tube (2), the second nor gate (G2) being made up of the 3rd cantilever beam grid NMOS tube (3) and the 4th cantilever beam grid NMOS tube (4), each nor gate concatenates a resistance (5), the rest-set flip-flop is produced in P-type silicon substrate (13), four cantilever beam grid (8) are that the grid of NMOS tube is suspended on silicon dioxide layer (7), it is made with Al；One end of cantilever beam grid (8) is fixed in anchor area (9), and the other end is suspended on silicon dioxide layer (7)；Part of the pull-down electrode under cantilever beam grid is covered in silicon dioxide layer, pull-down electrode ground connection；The rest-set flip-flop is supported and suspended on silicon dioxide layer top by anchor area；Make the rest-set flip-flop in the present invention that there is less DC leakage current.
Description
Technical field
The present invention proposes silicon substrate low-leakage current cantilever beam gate MOSFET (mos field effect transistor)
The rest-set flip-flop of nor gate, belongs to the technical field of microelectromechanical systems (MEMS).
Background technology
With continuing to develop for IC design industry, the various chips and circuit for having specific use are devised,
These chips and circuit can realize oneself specific function.But in recent years, the collection of chip circuit is increasing on a large scale, core
The radiating of transistor and quiescent dissipation problem become increasingly severe in piece, and the change of temperature can influence transistor and collection in chip
Into the stability of circuit work.Along with mobile terminal fast development, and the development of battery technology encounters unprecedented bottle
Neck, so the problem for reducing chip power-consumption and radiating is just particularly important.
Rest-set flip-flop circuit as digital circuit important component, it be it is various with sophisticated functions triggers electricity
The basic composition part on road, it is basic due to rest-set flip-flop circuit, have huge in the digital circuits such as central processing unit
Using so the control to the power consumption and temperature of rest-set flip-flop circuit just seems particularly significant, the RS being made up of conventional metal-oxide-semiconductor is touched
Hair device, with the lifting of integrated level, power consumption becomes increasingly severe, and the excessive chip overheating problem brought of power consumption can have a strong impact on
The performance of integrated circuit, the development of MEMS technology make it possible manufacture have can moving grid transistor, with can moving grid
Transistor can effectively reduce the grid leakage current that grid voltage brings, and then reduce the power consumption of rest-set flip-flop circuit.
The content of the invention
Technical problem：Touched it is an object of the invention to provide a kind of RS of silicon substrate low-leakage current cantilever beam gate MOSFET nor gate
Used in traditional rest-set flip-flop two nor gates being made up of conventional metal-oxide-semiconductor are changed to two by cantilever beam grid NMOS by hair device
The nor gate (i.e. four NMOS tubes with cantilever beam grid) that pipe is constituted, can effectively reduce grid leakage current so as to reduce electricity
The power consumption on road.
Technical scheme：A kind of rest-set flip-flop of silicon substrate low-leakage current cantilever beam gate MOSFET nor gate of the invention include by
First nor gate of the first cantilever beam grid NMOS tube and the second cantilever beam grid NMOS tube composition, by the 3rd cantilever beam grid NMOS tube and
Second nor gate of the 4th cantilever beam grid NMOS tube composition, each nor gate concatenates a resistance, and the rest-set flip-flop is produced on p-type
On silicon substrate, four cantilever beam grid are that the grid of NMOS tube is suspended on silicon dioxide layer, are made with Al；Cantilever beam grid
One end be fixed in anchor area, the other end is suspended on silicon dioxide layer, and anchor area polysilicon is produced in silicon dioxide layer,
N+ active areas are source electrode and the drain electrode of NMOS tube, and source electrode and drain electrode are connected by through hole with lead, and pull-down electrode is in cantilever beam grid
Under part covered by silicon dioxide layer；The input that wherein output end of the first nor gate passes through wire and the second nor gate
End connects, and the output end of same second nor gate is connected also by wire with an input of the first nor gate, has been formed
Holosymmetric structure；It is respectively S that rest-set flip-flop has two outer signal inputsDAnd RD, and two output ends Q and Q'.
Cantilever beam grid used by described rest-set flip-flop are supported and suspended on silicon dioxide layer top by anchor area；NMOS tube
Cantilever beam grid actuation voltage design it is equal with the threshold voltage of NMOS tube, only when added on the cantilever beam grid of NMOS tube
Voltage more than NMOS tube threshold voltage when, its cantilever beam grid could be drop-down and contact silicon dioxide layer so that cantilever beam grid
NMOS tube transoid is turned on, and when threshold voltage of institute's making alive less than NMOS tube, cantilever beam grid cannot be drop-down, when RS triggerings
When operating conditions is in the presence of input signal, two NMOS tubes just change device between on or off state, when
NMOS tube is off its cantilever beam grid during state and is at suspended state.
The source electrode for constituting two NMOS tubes in the first nor gate, second nor gate of rest-set flip-flop links together jointly
Ground connection, two grids of NMOS tube are all the inputs of data signal, and the drain electrode of two NMOS tubes links together and then passes through
Resistance connects with supply voltage, and data signal is input on two grids of NMOS tube, is total to it in two drain electrodes of NMOS tube
Exported between same load resistance.
The resistance of described resistance is set to when wherein any one NMOS tube is turned on, compared to the NMOS tube of conducting,
Sufficiently large may be such that of the resistance of the resistance 5 is output as low level, when two NMOS tubes can not all be turned on, compared to cut-off
NMOS tube, sufficiently small may be such that of the resistance of the resistance is output as high level.
When the rest-set flip-flop is in operating conditions, Q=1 is defined, Q '=0 is 1 state of trigger, defines Q=0, Q'=1
It is 0 state of trigger, SDReferred to as set end, RDReferred to as reset terminal.Work as SD=1, RDWhen=0, Q=1, Q'=0, in SD=1 letter
After number disappearing, another input of G2 is taken back due to the high level for there are Q ends, thus 1 state of circuit is maintained；When
SD=0, RDWhen=1, Q=0, Q'=1, in RDAfter=1 blackout, 0 state of circuit keeps constant；Work as SD=RDWhen=0,
The state that circuit remains original is constant；Work as SD=RDWhen=1, Q=Q'=0, this neither definition 1 state, nor definition
0 state, and work as SDAnd RDStill cannot judge which state trigger will be returned to after returning to 0 simultaneously, therefore, in normal work
Input signal should observe S when makingDRD=0 constraints, then SD=RD=1 signal would not allow for input.And the triggering
With the change of input signal, its state also changes NMOS tube in device between conducting and shut-off, when NMOS tube is off state
When its cantilever beam grid be at suspended state, in the absence of electric leakage of the grid on this MOSFET for meaning that in the rest-set flip-flop this moment
Stream, reduces the quiescent dissipation of rest-set flip-flop.
The grid of the cantilever beam grid NMOS tube used by rest-set flip-flop in the present invention is not to abut directly in titanium dioxide
On silicon layer, but silicon dioxide layer top is supported and suspended on by anchor area.The actuation voltage design of the cantilever beam grid of NMOS tube
Obtain equal with the threshold voltage of NMOS tube, only when threshold value electricity of the voltage added on the cantilever beam grid of NMOS tube more than NMOS tube
During pressure, its cantilever beam grid could be drop-down and contacts silicon dioxide layer so that cantilever beam grid NMOS tube transoid is turned on, when being powered up
Cantilever beam grid cannot be drop-down when pressure is less than its threshold voltage, Just because of this, just make rest-set flip-flop in the present invention have compared with
Small DC leakage current.
Beneficial effect：The rest-set flip-flop of silicon substrate low-leakage current cantilever beam gate MOSFET nor gate of the invention is due to can
Dynamic cantilever beam grid, when the NMOS tube is off state, its cantilever beam grid and are at suspended state, reduce direct grid current
Leakage current, is effectively reduced the power consumption of the rest-set flip-flop in the present invention.
Brief description of the drawings
Fig. 1 is the top view of the rest-set flip-flop of silicon substrate low-leakage current cantilever beam gate MOSFET nor gate.
Fig. 2 be the rest-set flip-flop of silicon substrate low-leakage current cantilever beam gate MOSFET nor gate A-A' to profile.
Fig. 3 be the rest-set flip-flop of silicon substrate low-leakage current cantilever beam gate MOSFET nor gate B-B' to profile.
Fig. 4 is the schematic diagram of the rest-set flip-flop of silicon substrate low-leakage current cantilever beam gate MOSFET nor gate.
Figure includes：First cantilever beam grid NMOS tube 1, the second cantilever beam grid NMOS tube 2, the 3rd cantilever beam grid NMOS tube 3,
4th cantilever beam grid NMOS tube 4, resistance 5, lead 6, silicon dioxide layer 7, cantilever beam grid 8, anchor area 9, N+ active areas 10, through hole
11st, pull-down electrode 12, P-type silicon substrate 13, the first nor gate G1, the second nor gate G2.
Specific embodiment
The rest-set flip-flop of silicon substrate low-leakage current cantilever beam gate MOSFET nor gate of the invention is mainly by two by cantilever
The nor gate of beam grid NMOS tube composition is four cantilever beam grid NMOS tubes, and each nor gate is by two cantilever beam grid NMOS tubes and one
The individual suitable resistance 5 of resistance is constituted, and the rest-set flip-flop is produced in P-type silicon substrate 13, four grids of cantilever beam grid NMOS tube
It is suspended on silicon dioxide layer 7, is made with Al；The Liang Gemao areas 9 of cantilever beam grid 8 are produced on silica with polysilicon
On layer 7, N+ active areas 10 are source electrode and the drain electrode of NMOS tube, and source electrode and drain electrode are connected by through hole 11 with lead 6, pull-down electrode
12 part under cantilever beam grid 8 is covered by silicon dioxide layer 7.
The structure for constituting the nor gate of rest-set flip-flop is that the source electrode of two in nor gate NMOS tube links together jointly
Ground connection, two grids of NMOS tube are all the inputs of data signal, the drain electrode of two NMOS tubes link together then with it is same
One resistance 5 connects, and the resistance of resistance 5 is set to when wherein any one NMOS tube is turned on, compared to the NMOS tube of conducting, should
Sufficiently large may be such that of the resistance of resistance 5 is output as low level, when two NMOS tubes can not all be turned on, compared to the NMOS of cut-off
Pipe, sufficiently small may be such that of the resistance of the resistance is output as high level.Resistance 5 connects with supply voltage, and data signal is at two
It is input on the grid of NMOS tube, is exported between two drain electrodes of NMOS tube load resistance 5 together.
The rest-set flip-flop is made up of two identical nor gates, wherein the output end of the first nor gate G1 is by leading
Line connects with an input of the second nor gate G2, and the output end of same second nor gate G2 is also by wire and first or non-
One input of door G1 is connected, and forms full symmetric structure.It is respectively S that rest-set flip-flop has two inputsDAnd RD, with
And two output end Q and Q', SDAnd RDIt is respectively respective input that two nor gates are not connected with output end, Q and Q'
It is then directly to be formed by the output end of two nor gates.
When the rest-set flip-flop is in operating conditions, Q=1 is defined, Q'=0 is 1 state of trigger, defines Q=0, Q'=1
It is 0 state of trigger, SDReferred to as set end, RDReferred to as reset terminal.Work as SD=1, RDWhen=0, Q=1, Q'=0, in SD=1 letter
After number disappearing, another input of G2 is taken back due to the high level for there are Q ends, thus 1 state of circuit is maintained；When
SD=0, RDWhen=1, Q=0, Q'=1, in RDAfter=1 blackout, 0 state of circuit keeps constant；Work as SD=RDWhen=0,
The state that circuit remains original is constant；Work as SD=RDWhen=1, Q=Q'=0, this neither definition 1 state, nor definition
0 state, and work as SDAnd RDStill cannot judge which state trigger will be returned to after returning to 0 simultaneously, therefore, in normal work
Input signal should observe S when makingDRD=0 constraints, then SD=RD=1 signal would not allow for input.And the RS is touched
With the change of input signal, its state also changes cantilever beam grid NMOS tube in hair device between conducting and shut-off, works as NMOS tube
It is off its cantilever beam grid 8 during state and is at suspended state, on this MOSFET for meaning that in the rest-set flip-flop this moment not
There is grid leakage current, reduce the quiescent dissipation of rest-set flip-flop.Due to rest-set flip-flop new state Q* (also referred to as next state) no
State Q (also referred to as initial state) only relevant with input state and original with rest-set flip-flop is relevant, it is possible to using Q as
One variable lists truth table in, then the truth table of the rest-set flip-flop for obtaining is as follows：
| SD | RD | Q | Q* |
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 0 |
The preparation method of the rest-set flip-flop of silicon substrate low-leakage current cantilever beam gate MOSFET nor gate includes following steps：
1) p-type Si substrates 13 are prepared；
2) bottom oxide growth, grows one layer of uniform oxide layer, as cushion by thermal oxide in smooth silicon face；
3) deposited silicon nitride, then photoetching and etch nitride silicon layer, retain the silicon nitride of active area, place
4) silicon nitride removal；
5) field oxidation, high-temperature thermal oxidation is carried out to silicon chip, and required thick oxide layer 7 is grown in place；
6) silicon nitride and basal oxygen sheet are removed, the silicon nitride of silicon chip surface and bottom oxygen is all removed using dry etching technology
Remove；
7) one layer of photoresist, photoetching and etching photoresist are coated on silicon chip, removal needs to make cantilever beam battery lead plate position
The photoresist put.Then one layer of Al, the Al on removal photoresist and photoresist are deposited, pull-down electrode 12 is formed；
8) gate oxidation is carried out, high-quality oxide layer is formed；
9) ion implanting, adjusts the threshold voltage of NMOS；
10) CVD technology deposit polycrystalline silicon, photoetching gate figure and polysilicon lead figure are utilized, by dry etching technology
Etches polycrystalline silicon, retains the polysilicon of input lead 6 and the position of cantilever beam Shan Mao areas 9.
11) PMGI sacrifice layers are formed by spin coating mode, then photoetching sacrifice layer, only retains the sacrificial of the lower section of cantilever beam grid 8
Domestic animal layer；
12) evaporation growth Al；
13) photoresist is coated, retains the photoresist of the top of cantilever beam grid 8；
14) Al is anti-carved, cantilever beam grid 8 are formed；
15) photoresist is coated, photoetching simultaneously etches the hand-hole of phosphorus, injects phosphorus, forms the active area 10 of NMOS tube；
16) through hole 11 and lead 6 are made；
17) PMGI sacrifice layers are discharged, the cantilever beam grid 8 for suspending are formed；
Difference with the prior art of the present invention：
The grid of the cantilever beam gate MOSFET used by rest-set flip-flop in the present invention is not to abut directly in titanium dioxide
Silicon layer, but it is supported and suspended on silicon dioxide layer top by anchor area.The actuation voltage of the cantilever beam grid of NMOS tube sets
Count equal with the threshold voltage of NMOS tube, only when threshold value of the voltage added on the cantilever beam grid of NMOS tube more than NMOS tube
During voltage, its cantilever beam grid could it is drop-down and contact silicon dioxide layer so that cantilever beam grid NMOS tube transoid turn on, when added
Cantilever beam grid cannot be drop-down when voltage is less than the threshold voltage of NMOS tube, when the rest-set flip-flop is located in the presence of input signal
When operating conditions, two NMOS tubes just change between on or off state, its cantilever when NMOS tube is off state
Beam grid are at suspended state, Just because of this, the rest-set flip-flop in the present invention is had less DC leakage current.
The structure for meeting conditions above can be considered silicon substrate low-leakage current cantilever beam gate MOSFET nor gate of the invention
Rest-set flip-flop.
Claims (3)
1. a kind of rest-set flip-flop of silicon substrate low-leakage current cantilever beam gate MOSFET nor gate, it is characterised in that the trigger include by
First nor gate (G1) of the first cantilever beam grid NMOS tube (1) and the second cantilever beam grid NMOS tube (2) composition, by the 3rd cantilever beam
Second nor gate (G2) of grid NMOS tube (3) and the 4th cantilever beam grid NMOS tube (4) composition, each nor gate concatenates a resistance
(5), the rest-set flip-flop is produced in P-type silicon substrate (13), and four cantilever beam grid (8) are that the grid of NMOS tube is suspended in titanium dioxide
On silicon layer (7), it is made with Al；One end of cantilever beam grid (8) is fixed in anchor area (9), and the other end is suspended in titanium dioxide
On silicon layer (7), anchor area (9) are produced in silicon dioxide layer (7) with polysilicon, N+ active areas (10) be NMOS tube source electrode and
Drain electrode, source electrode and drain electrode are connected by through hole (11) with lead (6), part quilt of the pull-down electrode (12) under cantilever beam grid (8)
Silicon dioxide layer (7) is covered；The output end of wherein the first nor gate (G1) is defeated with one of the second nor gate (G2) by wire
Enter end to connect, the output end of same second nor gate (G2) is connected also by wire with an input of the first nor gate (G1)
Connect, form full symmetric structure；It is respectively SD and RD that rest-set flip-flop has two outer signal inputs, and two output ends
Q and Q'；
Cantilever beam grid (8) used by described rest-set flip-flop are supported and suspended on silicon dioxide layer (7) top by anchor area (9)；
It is equal with the threshold voltage of NMOS tube that the actuation voltage of the cantilever beam grid (8) of NMOS tube is designed, only when the cantilever of NMOS tube
When added voltage is more than the threshold voltage of NMOS tube on beam grid (8), its cantilever beam grid (8) could be drop-down and contacts silica
Layer (7) is so that the conducting of cantilever beam grid NMOS tube transoid, cantilever beam grid (8) when threshold voltage of institute's making alive less than NMOS tube
Cannot be drop-down, when the rest-set flip-flop is when operating conditions is in the presence of input signal, two NMOS tubes just turning on or
Change between cut-off state, when NMOS tube is off state, its cantilever beam grid (8) is at suspended state.
2. the rest-set flip-flop of silicon substrate low-leakage current cantilever beam gate MOSFET nor gate according to claim 1, its feature exists
The source electrode of two NMOS tubes in the first nor gate (G1), second nor gate (G2) of composition rest-set flip-flop links together altogether
With ground connection, two grids of NMOS tube are all the inputs of data signal, and the drain electrode of two NMOS tubes links together and then logical
Cross resistance (5) to connect with supply voltage, data signal is input on two grids of NMOS tube, two drain electrodes of NMOS tube with
Exported between its common load resistance (5).
3. the rest-set flip-flop of silicon substrate low-leakage current cantilever beam gate MOSFET nor gate according to claim 1, its feature exists
It is set to when wherein any one NMOS tube is turned in the resistance of described resistance (5), compared to the NMOS tube of conducting, the electricity
Sufficiently large may be such that of resistance of resistance 5 is output as low level, when two NMOS tubes can not all be turned on, compared to the NMOS of cut-off
Pipe, sufficiently small may be such that of the resistance of the resistance is output as high level.
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| CN102735935A (en) * | 2012-06-20 | 2012-10-17 | 东南大学 | Phase detector based on micro-mechanical silicon-based cantilever beam and detection method |
| CN102735933A (en) * | 2012-06-20 | 2012-10-17 | 东南大学 | Micromechanical silicon-based clamped beam-based phase detector and detection method |
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| CN102735935A (en) * | 2012-06-20 | 2012-10-17 | 东南大学 | Phase detector based on micro-mechanical silicon-based cantilever beam and detection method |
| CN102735933A (en) * | 2012-06-20 | 2012-10-17 | 东南大学 | Micromechanical silicon-based clamped beam-based phase detector and detection method |
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