CN104992941B - Silicon substrate low-leakage current clamped beam grid cmos transmission gate and preparation method - Google Patents
Silicon substrate low-leakage current clamped beam grid cmos transmission gate and preparation method Download PDFInfo
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- CN104992941B CN104992941B CN201510378713.6A CN201510378713A CN104992941B CN 104992941 B CN104992941 B CN 104992941B CN 201510378713 A CN201510378713 A CN 201510378713A CN 104992941 B CN104992941 B CN 104992941B
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 36
- 239000010703 silicon Substances 0.000 title claims abstract description 36
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 35
- 239000000758 substrate Substances 0.000 title claims abstract description 25
- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 46
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- 238000001259 photo etching Methods 0.000 claims description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
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- 238000007254 oxidation reaction Methods 0.000 claims description 11
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- 238000013461 design Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
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- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
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- 239000002019 doping agent Substances 0.000 claims description 3
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- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
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- 239000008367 deionised water Substances 0.000 claims 1
- 229910021641 deionized water Inorganic materials 0.000 claims 1
- -1 silicon nitrides Chemical class 0.000 claims 1
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention is a kind of silicon substrate low-leakage current clamped beam grid cmos transmission gate and preparation method, and the transmission gate is made up of clamped beam grid NMOS tube and clamped beam grid PMOS.On a si substrate, its grid is suspended in above gate oxide for the making of the metal-oxide-semiconductor of the transmission gate, forms fixed beam structure.The envisaged underneath of clamped beam grid has battery lead plate.Clamped beam grid actuation voltage is designed as the absolute value of the threshold voltage equal to metal-oxide-semiconductor.When the voltage between clamped beam grid and battery lead plate is less than the absolute value of threshold voltage, clamped beam grid are suspended in the top of gate oxide, and the voltage only between clamped beam grid and battery lead plate is when reaching or surpassing the absolute value of threshold voltage, clamped beam grid can just be pulled down to and are attached on gate oxide, if now input is different from the level value of output end, metal-oxide-semiconductor conducting.Field strength in gate oxide at work of the invention reduces, so reducing grid leakage current, significantly reduces power consumption.
Description
Technical field
The present invention proposes silicon substrate low-leakage current clamped beam grid cmos transmission gate, belongs to the technology neck of microelectromechanical systems
Domain.
Background technology
After the continuous diminution of the characteristic size of electronic device, the particularly appearance of deep submicron process, chip
Scale constantly increases, and the number for the metal-oxide-semiconductor being internally integrated is to sharply increase.Simultaneously as electronic product is to the processing speed of chip
Requirement more and more higher, the clock frequency of chip also more and more higher.More than one hundred million metal-oxide-semiconductors is in very high operation at frequencies so that core
The power problemses of piece become notable.Too high power consumption can make chip overheating, can not only reduce the service behaviour of chip and can also influence
The reliability of chip, shorten the service life of chip.Too high power consumption can also make various Mobile portable formula equipment have to face
The problems such as power supply is continued a journey and radiated.Therefore, the too high power consumption of integrated circuit proposes more to the heat dispersion and stability of equipment
High requirement, the endurance of various Mobile portable formula equipment is also by increasing challenge.So for current designer
For, the power problemses of chip are the major issues having to take into account that.
The power consumption of common MOS transistor device has dynamic power consumption and quiescent dissipation.Exchange letter when dynamic power consumption is metal-oxide-semiconductor work
Number produce；And quiescent dissipation is loss caused by leakage current.And mainly having two kinds for leakage current, one kind is that grid voltage is brought
Grid leakage current, leakage current when ending when another between source and drain.And the research for MOS transistor device focuses mostly at present
Reduction to metal-oxide-semiconductor dynamic power consumption.The research of reduction to leakage current is seldom.The present invention is one kind based on Si technological designs
Silicon substrate low-leakage current clamped beam grid cmos transmission gate with extremely low grid leakage current.
The content of the invention
Technical problem:It is an object of the invention to provide a kind of silicon substrate low-leakage current clamped beam grid cmos transmission gate and preparation side
Method, when COMS transmission gates work, it is often desirable that it is for 0 in the DC current of grid.And in fact, due to conventional MOS pipe
Gate oxide it is very thin, so the field strength in gate oxide is very big, it will usually cause certain DC leakage current.Particularly same
In one cmos transmission gate, the polarity of the voltage added by the grid of NMOS tube and PMOS is opposite, so in two grids
Between be formed DC loop.Simultaneously.In large scale integrated circuit, the presence of this leakage current can increase transmission gate and work
In power consumption.And both leakage currents are effectively reduced in the present invention.
Technical scheme：The silicon substrate low-leakage current clamped beam grid cmos transmission gate of the present invention is by clamped beam grid NMOS tube and clamped
Beam grid PMOS is formed, and clamped beam grid NMOS tube and clamped beam grid PMOS are connected in parallel, and the metal-oxide-semiconductor in the transmission gate is system
Make on p-type Si substrates, its lead is made using polysilicon, and for the metal-oxide-semiconductor in transmission gate, its grid is suspended in grid
Oxide layer, fixed beam structure is formed, this clamped beam Shan Mao areas are produced on gate oxide, are set below clamped beam grid
In respect of battery lead plate, there is the covering of gate oxide above battery lead plate, the battery lead plate of clamped beam grid NMOS tube is ground connection, and clamped beam
The battery lead plate of grid PMOS is to connect power supply.
The threshold voltage designs of clamped beam grid NMOS tube are that just the threshold voltage designs of clamped beam grid PMOS are negative, Gu
The absolute value of the threshold voltage of strutbeam grid NMOS tube and clamped beam grid PMOS is designed as equal, and the actuation voltage of clamped beam grid is set
The absolute value of the threshold voltage equal to metal-oxide-semiconductor is calculated as, at work, clamped beam grid and the clamped beam grid of clamped beam grid NMOS tube
For the signal that the clamped beam grid of PMOS are loaded on the contrary, when transmission gate is opened, the clamped beam grid of clamped beam grid NMOS tube connect high electricity
Flat, the voltage of its clamped beam grid and battery lead plate below is more than the absolute value of threshold voltage, so clamped beam grid pull down to grid oxygen
Change on layer, and the clamped beam grid of clamped beam grid PMOS connect low level, the voltage of its clamped beam grid and battery lead plate below is also big
In the absolute value of threshold voltage, so its clamped beam grid is also pulled down on gate oxide, now transmission gate of the invention and tradition
Cmos transmission gate it is similar, as long as output it is different with incoming level, two metal-oxide-semiconductors will turn on, and realize the transmission of level, and work as
When transmission gate closes, situation is just the opposite, and the clamped beam grid of clamped beam grid NMOS tube connect low level, clamped beam grid PMOS it is clamped
Beam grid connect high level, and the clamped beam grid of two metal-oxide-semiconductors suspend, now no matter input and output is to be in high level or low electricity
It is flat, what two metal-oxide-semiconductors were all off, so transmission level value is unable to, it is achieved thereby that the function of transmission gate.
When the voltage between clamped beam grid and battery lead plate is less than the absolute value of threshold voltage, clamped beam grid are suspended in grid oxygen
Change the top of layer, and clamped beam when the voltage only between clamped beam grid and battery lead plate reaches or surpasses the absolute value of threshold voltage
Grid can just be pulled down to and are attached on gate oxide, if now input is different from the level value of output end, metal-oxide-semiconductor conducting, be compared
In traditional metal-oxide-semiconductor, the present invention is due to the design of suspension clamped beam grid, and the field strength in gate oxide is smaller, therefore DC leakage
Stream greatly reduces, so as to effectively reduce power consumption.
The preparation method of the silicon substrate low-leakage current clamped beam grid cmos transmission gate of the present invention is as follows：
1) p-type Si substrates are prepared；
2) initial oxidation, SiO is grown2Layer, the screen layer as doping；
3) photoetching SiO2Layer, carves N trap hand-holes；
4) N traps inject, and anneal in a nitrogen environment；After the completion of annealing, dopant redistribution is carried out at high temperature, forms N traps；
5) whole oxide layers of silicon face are removed；
6) bottom oxide growth.One layer of uniform oxide layer is grown in smooth silicon face by thermal oxide, as cushion.
7) deposited silicon nitride, then photoetching and etch nitride silicon layer retain the silicon nitride of active area, and the silicon nitride of place is gone
Remove；
8) field aoxidizes.High-temperature thermal oxidation is carried out to silicon chip, required thick oxide layer is grown in place；
9) silicon nitride and basal oxygen sheet are removed, is all gone the silicon nitride of silicon chip surface and bottom oxygen using dry etching technology
Remove.
10) one layer of photoresist, photoetching and etching photoresist are coated on silicon chip, removal needs to make clamped beam battery lead plate position
The photoresist put.Then one layer of Al is deposited, removes the Al on photoresist and photoresist, forms battery lead plate；
11) gate oxidation is carried out.Gate oxidation is carried out, forms the oxide layer of a floor height quality；
12) CVD technology deposit polycrystalline silicon, photoetching gate figure and polysilicon lead figure are utilized, passes through dry etching technology
Etches polycrystalline silicon, retain the polysilicon of the anchor zone position of clamped beam.
13) PMGI sacrifice layers are formed by spin coating mode, then photoetching sacrifice layer, only retains the sacrifice below clamped beam grid
Layer；
14) evaporation growth Al；
15) photoresist is coated, retains the photoresist above clamped beam grid；
16) Al is anti-carved, forms clamped beam grid；
17) photoresist, photoetching and the hand-hole for etching boron are coated, injects boron, forms the active of clamped beam grid PMOS
Area；
18) photoresist, photoetching and the hand-hole for etching phosphorus are coated, injects phosphorus, forms the active of clamped beam grid NMOS tube
Area；
19) through hole and lead are made；
20) polyimide sacrificial layer is discharged：Developer solution soak, remove clamped beam grid under polyimide sacrificial layer, go from
Sub- water soaks slightly, absolute ethyl alcohol dehydration, is volatilized under normal temperature, dries, form the clamped beam grid of suspension.
In the present invention, the grid of metal-oxide-semiconductor is not directly attached on gate oxide, and is suspended in the upper of gate oxide
Side, form a fixed beam structure.In the present invention, the threshold voltage designs of clamped beam grid NMOS tube are just clamped beam grid PMOS
The threshold voltage designs of pipe are negative, and the absolute value of the threshold voltage of two metal-oxide-semiconductors is designed as identical.And two metal-oxide-semiconductors is clamped
The actuation voltage of beam grid is designed as equal with the absolute value of the threshold voltage of metal-oxide-semiconductor.At work, clamped beam grid NMOS tubes is consolidated
Strutbeam grid are opposite with the signal that the clamped beam grid of clamped beam grid PMOS are loaded.When transmission gate is opened, clamped beam grid NMOS tube
Clamped beam grid connect high level, the voltage of its clamped beam grid and battery lead plate below is more than the absolute value of threshold voltage, so solid
Strutbeam grid are pulled down on gate oxide, and the clamped beam grid of clamped beam grid PMOS connect low level, its clamped beam grid with below
The voltage of battery lead plate also greater than threshold voltage absolute value, so its clamped beam grid is also pulled down on gate oxide, now this hair
Bright transmission gate is similar with traditional cmos transmission gate, as long as output is different with incoming level, two metal-oxide-semiconductors will turn on, real
The transmission of existing level.And when transmission gate closes, situation is just the opposite, and the clamped beam grid of clamped beam grid NMOS tube connect low level, Gu
The clamped beam grid of strutbeam grid PMOS connect high level, and the clamped beam grid of two metal-oxide-semiconductors suspend, and now no matter input and output is place
In high level or low level, what two metal-oxide-semiconductors were all off, it is achieved thereby that the function of transmission gate.So in the present invention
Metal-oxide-semiconductor work in, when the voltage between grid and battery lead plate be less than threshold voltage absolute value when, clamped beam grid are suspended in grid
The top of oxide layer, and when the voltage only between grid and battery lead plate reaches or surpasses the absolute value of threshold voltage, clamped beam
Grid can just be pulled down to and are attached on gate oxide, if now input is different from the level value of output end, metal-oxide-semiconductor conducting.Compare
When the clamped beam grid of metal-oxide-semiconductor in traditional metal-oxide-semiconductor, the present invention only have metal-oxide-semiconductor conducting, just it is attached on gate oxide, and its
All it is to suspend in the case of him, so the field strength in gate oxide is smaller, therefore DC leakage current also greatly reduces.
Beneficial effect：Field strength of the clamped beam grid transmission gate of the present invention at work in gate oxide is smaller, can be effective
Reduce grid leakage current.So that the power consumption of the clamped beam grid transmission gate in the present invention is effectively reduced.
Brief description of the drawings
Fig. 1 is the schematic diagram of silicon substrate low-leakage current clamped beam grid cmos transmission gate of the present invention,
Fig. 2 is the top view of silicon substrate low-leakage current clamped beam grid cmos transmission gate of the present invention,
Fig. 3 be Fig. 2 silicon substrate low-leakage current clamped beam grid cmos transmission gates P-P ' to profile,
Fig. 4 be Fig. 2 silicon substrate low-leakage current clamped beam grid cmos transmission gates A-A ' to profile,
Fig. 5 be Fig. 2 silicon substrate low-leakage current clamped beam grid cmos transmission gates B-B ' to profile.
Figure includes：Clamped beam grid NMOS tube 1, clamped beam grid PMOS 2, p-type Si substrates 3, lead 4, gate oxide 5,
Clamped beam grid 6, anchor area 7, battery lead plate 8, N traps 9, clamped beam grid PMOS active area 10, clamped beam grid NMOS tube active area 11, lead to
Hole 12.
Embodiment
The present invention is made up of clamped beam grid NMOS tube 1 and clamped beam grid PMOS 2, clamped beam grid NMOS tube 1 and clamped
Beam grid PMOS 2 is connected in parallel.The MOS of the transmission gate is made based on p-type Si substrates 3, and its lead 4 is made using Al.This
The grid of clamped beam grid NMOS tube 1 and clamped beam grid PMOS 2 in invention is suspended in the top of gate oxide 5, is formed solid
Strutbeam grid 6.The Liang Gemao areas 7 of clamped beam grid 6 are produced on gate oxide 5 using polysilicon.Under each clamped beam grid 6
Side, devises two battery lead plates 8.There is the covering of gate oxide 5 top of battery lead plate 8.The battery lead plate 8 of clamped beam grid NMOS tube 1
It is ground connection, and the battery lead plate 8 of clamped beam grid PMOS 2 is to connect power supply.
In the present invention, the threshold voltage designs of clamped beam grid NMOS tube 1 is just, the threshold value of clamped beam grid PMOS 2 are electric
Pressure is designed as bearing, and the absolute value of the threshold voltage of two metal-oxide-semiconductors is designed as equal, and the grid of metal-oxide-semiconductor is not to be directly attached to grid
In oxide layer 5, and the top of gate oxide 5 is suspended in, forms a clamped beam grid 6.The actuation voltage of the clamped beam grid 6
It is designed as equal with the absolute value of the threshold voltage of metal-oxide-semiconductor.At work, the clamped beam grid 6 of clamped beam grid NMOS tube 1 with it is clamped
The signal that the clamped beam grid 6 of beam grid PMOS 2 are loaded is opposite.When transmission gate is opened, the clamped beam grid of clamped beam grid NMOS tube 1
6 connect high level, and the voltage of its clamped beam grid 6 and battery lead plate 8 below is more than the absolute value of threshold voltage, so clamped beam grid 6
Pull down on gate oxide 5, and the clamped beam grid 6 of clamped beam grid PMOS 2 connect low level, its clamped beam grid 6 and electricity below
The voltage of pole plate 8 also greater than threshold voltage absolute value, so its clamped beam grid 6 is also pulled down on gate oxide 5, now this hair
Bright transmission gate is similar with traditional cmos transmission gate, as long as output is different with incoming level, two metal-oxide-semiconductors will turn on, real
The transmission of existing level.And when transmission gate closes, situation is just the opposite, and the clamped beam grid 6 of clamped beam grid NMOS tube 1 connect low level,
The clamped beam grid 6 of clamped beam grid PMOS 2 connect high level, and the clamped beam grid 6 of two metal-oxide-semiconductors suspend, now no matter input with it is defeated
Go out to be in high level or low level, what two metal-oxide-semiconductors were all off, so transmission level value is unable to, it is achieved thereby that passing
The function of defeated door.So during metal-oxide-semiconductor in the present invention works, when the voltage between clamped beam grid 6 and battery lead plate 8 is less than threshold value electricity
During the absolute value of pressure, clamped beam grid 6 are suspended in the top of gate oxide 5, and only between clamped beam grid 6 and battery lead plate 8
When voltage reaches or surpasses the absolute value of threshold voltage, clamped beam grid 6 can just be pulled down to and are attached on gate oxide, if now inputting
End is different from the level value of output end, then metal-oxide-semiconductor turns on.Compared to traditional metal-oxide-semiconductor, the clamped beam of the metal-oxide-semiconductor in the present invention
Voltage of the grid 6 only between grid and battery lead plate 8 is just attached on gate oxide 5 when being more than or equal to the absolute value of threshold voltage,
And be all to suspend in the case of other, so the field strength in gate oxide 5 is smaller, therefore DC leakage current also greatly reduces.
The preparation method of silicon substrate low-leakage current clamped beam grid cmos transmission gate includes following steps：
1) p-type Si substrates 3 are prepared；
2) initial oxidation, SiO is grown2Layer, the screen layer as doping；
3) photoetching SiO2Layer, carves the hand-hole of N traps 9；
4) N traps 9 inject, and anneal in a nitrogen environment；After the completion of annealing, dopant redistribution is carried out at high temperature, forms N traps
9；
5) whole oxide layers of silicon face are removed；
6) bottom oxide growth.One layer of uniform oxide layer is grown in smooth silicon face by thermal oxide, as cushion.
7) deposited silicon nitride, then photoetching and etch nitride silicon layer retain the silicon nitride of active area, and the silicon nitride of place is gone
Remove；
8) field aoxidizes.High-temperature thermal oxidation is carried out to silicon chip, required thick oxide layer is grown in place；
9) silicon nitride and basal oxygen sheet are removed, is all gone the silicon nitride of silicon chip surface and bottom oxygen using dry etching technology
Remove.
10) one layer of photoresist, photoetching and etching photoresist are coated on silicon chip, removing needs to make the position of battery lead plate 8
Photoresist.Then one layer of Al is deposited, removes the Al on photoresist and photoresist, forms battery lead plate；
11) gate oxidation is carried out.Form the oxide layer of a floor height quality；
12) CVD technology deposit polycrystalline silicon, photoetching gate figure and polysilicon lead figure are utilized, passes through dry etching technology
Etches polycrystalline silicon, retain the polysilicon of the position of anchor area 7 of clamped beam grid 6.
13) PMGI sacrifice layers are formed by spin coating mode, then photoetching sacrifice layer, only retains the sacrificial of the lower section of clamped beam grid 6
Domestic animal layer；
14) evaporation growth Al；
15) photoresist is coated, retains the photoresist of the top of clamped beam grid 6；
16) Al is anti-carved, forms clamped beam grid 6；
17) photoresist, photoetching and the hand-hole for etching boron are coated, injects boron, forms the active of clamped beam grid PMOS 2
Area 10；
18) photoresist, photoetching and the hand-hole for etching phosphorus are coated, injects phosphorus, forms the active of clamped beam grid NMOS tube 1
Area 11；
19) through hole 12 and lead 4 are made；
20) polyimide sacrificial layer is discharged：Developer solution soaks, and removes the polyimide sacrificial layer under clamped beam grid 6, go from
Sub- water soaks slightly, absolute ethyl alcohol dehydration, is volatilized under normal temperature, dries, form the clamped beam grid 6 of suspension.
Difference with the prior art of the present invention is：
The present invention can effectively reduce the grid leakage current of metal-oxide-semiconductor at work, reduce power consumption, improve performance.This hair
Transmission gate in bright is made up of clamped beam grid NMOS tube and clamped beam grid PMOS.Clamped beam grid metal-oxide-semiconductor and traditional metal-oxide-semiconductor are most
Big difference is that the grid of clamped beam grid metal-oxide-semiconductor is suspended in the top of oxide layer, forms fixed beam structure.Clamped beam grid
Actuation voltage be designed as equal to metal-oxide-semiconductor threshold voltage absolute value.When the voltage between clamped beam grid and battery lead plate is less than MOS
During the absolute value of the threshold voltage of pipe, clamped beam grid have certain gap with oxide layer below.And only work as clamped beam
During the absolute value for the threshold voltage that the voltage between grid and battery lead plate is equal to or more than metal-oxide-semiconductor, clamped beam grid can just pulled down to attached
In oxide layer thereunder.So when transmission gate in the present invention works, the voltage only between grid and battery lead plate is big
In or equal to threshold voltage absolute value when be just attached on gate oxide, and be all to suspend in the case of other, in gate oxide
Field strength it is smaller, so direct grid current leakage current will greatly reduce, so that power consumption is effectively lowered.
Meet that the structure of conditions above is considered as the silicon substrate low-leakage current clamped beam grid cmos transmission gate of the present invention.
Claims (2)
- A kind of 1. silicon substrate low-leakage current clamped beam grid cmos transmission gate, it is characterized in that the transmission gate is by clamped beam grid NMOS tube (1) Formed with clamped beam grid PMOS (2), clamped beam grid NMOS tube (1) and clamped beam grid PMOS (2) are connected in parallel, the transmission Metal-oxide-semiconductor in door is produced on p-type Si substrates (3), and its lead (4) is made using polysilicon, in transmission gate Metal-oxide-semiconductor, its grid are suspended in above gate oxide (5), form fixed beam structure, the anchor area (7) of this clamped beam grid (6) It is produced on gate oxide (5), clamped beam grid (6) envisaged underneath has battery lead plate (8), and battery lead plate has gate oxide above (8) (5) covering, the battery lead plate (8) of clamped beam grid NMOS tube (1) is ground connection, and the battery lead plate (8) of clamped beam grid PMOS (2) is Connect power supply；The threshold voltage designs of clamped beam grid NMOS tube is just, the threshold voltage designs of clamped beam grid PMOS are negative, clamped beam The absolute value of the threshold voltage of grid NMOS tube and clamped beam grid PMOS is designed as equal, and the actuation voltage of clamped beam grid is designed as Equal to the absolute value of the threshold voltage of metal-oxide-semiconductor.
- 2. a kind of preparation method of silicon substrate low-leakage current clamped beam grid cmos transmission gate as claimed in claim 1, its feature exist It is as follows in the preparation method：1) prepares p-type Si substrates；2) initial oxidations, SiO is grown2Layer, the screen layer as doping；3) photoetching SiO2Layer, carves N trap hand-holes；4) .N traps inject, and anneal in a nitrogen environment；After the completion of annealing, dopant redistribution is carried out at high temperature, forms N traps；5) removes whole oxide layers of silicon face；6) bottoms oxide growth, one layer of uniform oxide layer is grown in smooth silicon face by thermal oxide, as cushion；7) deposited silicon nitrides, then photoetching and etch nitride silicon layer retain the silicon nitride of active area, and the silicon nitride of place removes；8) fields aoxidize, and carry out high-temperature thermal oxidation to silicon chip, required thick oxide layer is grown in place；9) removes silicon nitride and basal oxygen sheet, is all removed the silicon nitride of silicon chip surface and bottom oxygen using dry etching technology；10) coats one layer of photoresist, photoetching and etching photoresist on silicon chip, and removal needs to make clamped beam electrode Board position Photoresist, then deposit one layer of Al, remove the Al on photoresist and photoresist, form battery lead plate；11) carries out gate oxidation, carries out gate oxidation, forms the oxide layer of a floor height quality；12) utilizes CVD technology deposit polycrystalline silicon, photoetching gate figure and polysilicon lead figure, is etched by dry etching technology Polysilicon, retain the polysilicon of the anchor zone position of clamped beam；13) forms PMGI sacrifice layers by spin coating mode, then photoetching sacrifice layer, only retains the sacrifice layer below clamped beam grid；14) evaporations growth Al；15) coats photoresist, retains the photoresist above clamped beam grid；16) anti-carves Al, forms clamped beam grid；17) coats photoresist, photoetching and the hand-hole for etching boron, injects boron, forms the active area of clamped beam grid PMOS；18) coats photoresist, photoetching and the hand-hole for etching phosphorus, injects phosphorus, forms the active area of clamped beam grid NMOS tube；19) makes through hole and lead；20) discharges polyimide sacrificial layer：Developer solution soaks, and removes the polyimide sacrificial layer under clamped beam grid, deionized water Soak slightly, absolute ethyl alcohol dehydration, volatilized under normal temperature, dry, form the clamped beam grid of suspension.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510378713.6A CN104992941B (en) | 2015-07-01 | 2015-07-01 | Silicon substrate low-leakage current clamped beam grid cmos transmission gate and preparation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510378713.6A CN104992941B (en) | 2015-07-01 | 2015-07-01 | Silicon substrate low-leakage current clamped beam grid cmos transmission gate and preparation method |
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| Publication Number | Publication Date |
|---|---|
| CN104992941A CN104992941A (en) | 2015-10-21 |
| CN104992941B true CN104992941B (en) | 2018-02-23 |
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