CN104918319A - Clock synchronization simplified information exchange method applied to wireless sensor network - Google Patents
Clock synchronization simplified information exchange method applied to wireless sensor network Download PDFInfo
- Publication number
- CN104918319A CN104918319A CN201410093804.0A CN201410093804A CN104918319A CN 104918319 A CN104918319 A CN 104918319A CN 201410093804 A CN201410093804 A CN 201410093804A CN 104918319 A CN104918319 A CN 104918319A
- Authority
- CN
- China
- Prior art keywords
- clock
- node
- time
- bunch head
- head side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
- Mobile Radio Communication Systems (AREA)
Abstract
The invention provides a clock synchronization simplified information exchange method applied to a wireless sensor network. The method comprises steps: a cluster head side sends a message and records a time stamp t1, and a node side receives the message and records a time stamp t2; the node side sends and feeds back the message adn records a time stamp t3; the cluster head side receives the feedback message and records a time stamp t4; the cluster head side combines the time stamps t1 and t4 into a data packet and sends the data packets to the node side; according to the time stamps t2 and t3 and t1 and t4 analyzed from the data packet, the node side calculates clock offset for local clock calibration. The method is simple, synchronization time is greatly reduced, realization is convenient, an IEEE1588 accurate clock synchronization protocol and an IEEE802.15.4 wireless sensor network protocol are combined, at least two message sending and receiving times are saved during each time synchronization process, reliability is high, and the working efficiency is improved.
Description
Technical field
The present invention relates to the Clock Synchronization Technology field in wireless sensor network, particularly a kind of clock synchronous being applied to wireless sensor network simplifies information interacting method.
Background technology
Precision Clock Synchronization technology is widely used in, in the increasing technical field such as intelligent grid distributed equipment room, distributed monitoring and control system, becoming people and paying close attention to the focus with research.
Current Clock Synchronization Technology, is divided into wired and wireless two kinds usually.Cable clock simultaneous techniques is traditional Clock Synchronization Technology, adopt IEEE1588 accurate clock synchronization protocol, as shown in Figure 1, accuracy is good, computing formula is simple, but because be subject to the restriction of track laying, difficult in maintenance, the factor such as dumb of layouting, under many application scenarioss, just gradually substitute by wireless technology.
Current time synchronization in wireless sensor networks, IEEE1588 accurate clock synchronization protocol is directly applied to the protocol stack under IEEE802.15.4 wireless sensor network standards by usual employing, the transmission and reception pattern of existing protocol stack is utilized to carry out synchronizing information transmission between reference clock terminal and synchronous terminal, as shown in Figure 2, but the method is very complicated, need receive and send multiple information to the calculating in the path delay of time and clock jitter that realize clock synchronous two equipment rooms, add the system message expense of wireless network, extend lock in time, in addition, consider the particularity of wireless sensor network self, when there is random disturbances or bursty interference in transmission channel, synchronizing information is easily caused to lose, as long as and one of them dropout of conventional method or mistake, namely clock synchronous failure can directly be caused, wait is needed to resend next synchronizing information, this will cause the further prolongation of lock in time, increase the message transmission overhead of Radio Network System further, affect clock synchronization accuracy.
Summary of the invention
Uncertain for existing time synchronization in wireless sensor networks synchronization delayed time, the problems such as system message expense is large, it is little that the object of the embodiment of the present invention is to provide a kind of synchronization delayed time, the clock synchronous of what synchronization message expense was little be applied to wireless sensor network simplifies information interacting method, in conjunction with IEEE1588 accurate clock synchronization protocol and IEEE802.15.4 wireless sensor network protocols, at least omit 2 information each time in time synchronization process to send and receiving cycle, can be applicable to intelligent grid distributed equipment room, the synchronised clock of distributed monitoring and control system is set up with punctual.
In order to achieve the above object, the embodiment of the present invention provides following technical scheme:
The clock synchronous being applied to wireless sensor network simplifies an information interacting method, it is characterized in that, comprises the following steps:
Q1: the clock of bunch head side is master clock, has the effect of reference clock, the main control unit of bunch head side determines the node ID that will carry out clock synchronous, and sends sync message signal to this node side, and the timestamp t1 sent by FPGA recording synchronism message signals;
Q2: node side clock needs to carry out clock alignment with a bunch head side, and the main control unit of node side receives sync message signal, and is recorded the timestamp t2 receiving sync message signal by FPGA;
Meanwhile, according to IEEE802.15.4 protocol specification, node, after successfully receiving message signals, to a bunch head side transmission and reception confirmation message signal, and stabs t3 by the transmitting time of FPGA registration confirmed message signals;
Q3: bunch head side joint receives the confirmation of receipt message signals from node side, and the time of reception stamp t4 being recorded this message signals by FPGA;
Q4: the main control unit of bunch head side is combined into packet by the transmitting time of recorded sync message signal stamp t1 with from the time of reception stamp t4 of the confirmation message signals of node side, is sent to node side;
Q5: the main control unit of node side receives packet, send confirmation message signal to a bunch head side, simultaneously according to the time of reception stamp t2 of the sync message signal of node sidelights record and the transmitting time stamp t3 of confirmation message signal, and t1 and t4 parsed from packet, the path delay of time between direct compute cluster head side and node side and the clock jitter Offset between leader cluster node, carry out local clock calibration, its concrete computational methods are:
t
2-t
1＝Delay+Offset
t
4-t
3＝Delay-Offset
Delay＝(t
2-t
1)+(t
4-t
3)/2
Offset＝(t
2-t
1)-(t
4-t
3)/2
Q6: the complete useful signal of a time synchronized is often carried out in bunch head side, node side form according to step Q1-Q5 is: long pulse, pulse duration are T1, pulse spacing, width are T2, short pulse, pulse duration are the form of T3, wherein the value of T1, T3 remains unchanged in synchronizing process, to meet IEEE802.15.4 protocol specification;
Q7: in above-mentioned steps Q1-Q4 process, wireless senser radio circuit provides the signal designation of transmitting and receiving data, can use as transmission and reception timestamp index signal, the FPGA be connected with radio circuit index signal is whenever signal rising edge being detected, namely in register R1, record clock value corresponding to first rising edge, in register R2, record the clock value of second rising edge subsequently;
Q8: in above-mentioned steps Q1-Q4 process, the acquisition methods of timestamp is: the FPGA fixed signal be connected with synchronous or confirmation message signal and timestamp index signal carry out associative operation, and concrete operations are carried out according to following formula:
R(n)=（1/N）∑[x(m)y(m+n)]，
Wherein m changes from 0 to N-1; R (n) is correlation, x(m), m=0-N-1, represents local preset signals; Y(m) index signal waveform;
Setting coherent detection threshold value RTH, when the R (n) calculating gained is more than or equal to set threshold value RTH,
The clock value recorded in register R1 and R2 in Q7 is corresponding timestamp, and for a bunch head side, what store in R1 is that to store in t1, R2 is t4; For node side, what store in R1 is that to store in t2, R2 is t3;
Q9: node side main control unit utilizes the clock jitter Offset calculated in step Q5, can carry out real-time knot modification local clock, concrete method of adjustment is: Clock is new=former+offset of clock.
A kind of clock synchronous being applied to wireless sensor network that the embodiment of the present invention provides simplifies information interacting method, method is simple, greatly reduce synchronization message expense, decrease the possibility of makeing mistakes, and simplified computing cycle, while being convenient to realize, in conjunction with IEEE1588 accurate clock synchronization protocol and IEEE802.15.4 wireless sensor network protocols, at least omit 2 synchronization messages each time in time synchronization process to send and receive, reliability is high, improves operating efficiency.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the mutual schematic diagram of synchronizing information within a synchronizing cycle of IEEE1588 accurate clock synchronization protocol in prior art.
Fig. 2 is the mutual schematic diagram of synchronizing information within a synchronizing cycle of IEEE802.15.4 wireless sensor network standards method in prior art.
Fig. 3 simplifies the mutual schematic diagram of synchronizing information within a synchronizing cycle of information interacting method for a kind of clock synchronous being applied to wireless sensor network that the embodiment of the present invention 1 provides.
Fig. 4 simplifies the system configuration schematic diagram of information interacting method for a kind of clock synchronous being applied to wireless sensor network that the embodiment of the present invention 1 provides.
Fig. 5 simplifies the mutual schematic diagram of the synchronizing information when carrying out multiple node side of information interacting method for a kind of clock synchronous being applied to wireless sensor network that the embodiment of the present invention 2 provides.
Fig. 6 simplifies the complete useful signal of a time synchronized often to be carried out in bunch head side of information interacting method, node side curve synoptic diagram according to step Q1-Q5 for a kind of clock synchronous being applied to wireless sensor network that the embodiment of the present invention provides.
Fig. 7 is the schematic diagram data that a kind of clock synchronous being applied to wireless sensor network simplifies that the final result of synchro system test is carried out in bunch head side of the experiment of information interacting method and node side.
Embodiment
Below in conjunction with accompanying drawing of the present invention, be clearly and completely described technical scheme of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Fig. 1 is the mutual schematic diagram of synchronizing information within a synchronizing cycle of IEEE1588 accurate clock synchronization protocol, Fig. 2 is the mutual schematic diagram of synchronizing information within a synchronizing cycle of IEEE802.15.4 wireless sensor network standards method, the mutual schematic diagram of synchronizing information within a synchronizing cycle that Fig. 3, Fig. 5 provide for the embodiment of the present invention, can be found out by figure contrast, the synchronizing information exchange method that the embodiment of the present invention provides is more simple and practical, and reliability is also described in detail at Ben Chu.
Embodiment 1
In present specification, a bunch head side is master clock, has the effect of reference clock, node side can have multiple, the synchronizing information exchange method that Fig. 3 is 1 node to be synchronized, Fig. 5 is multiple node to be synchronized, node side clock stability is poor, needs to carry out clock alignment with a bunch head side.In practical application, normally clock synchronous will be carried out with multiple node in a bunch of head side, and bunch head is a clock synchronous time period of each peer distribution, complete in section at this moment one synchronizing cycle task.
As shown in Figure 3-4, it is how to complete complete work period that lower mask body sets forth summary of the invention that the application mentions, a bunch of head side and the synchronous method flow of a nodal clock, the Clock Synchronization Procedure within a synchronizing cycle is that example is described, and the method comprises:
Step one: the main control unit of bunch head side determines the node ID carrying out clock synchronous calibration, and send sync message signal to it;
Step 2: node side successfully receives the sync message signal that bunch head side is sent, and feeding back confirmation message gives bunch head side (ACK message);
Step 3: in step one and step 2 process, the FPGA module of bunch head side, detects the transmission and reception index signal of bunch head radio circuit, record rising edge time of advent, and will be recorded to the time in shift register R1 and R2;
Step 4: in step one and step 2 two steps, the radio circuit transmission and reception index signal waveform that the FPGA module of bunch head side will detect, contrasts with preset signals waveform, and calculates wave-form similarity;
The method of coherent detection is selected in control methods, carries out according to the following equation, and obtains correlation:
R(n)=（1/N）∑[x(m)y(m+n)]
Wherein m changes from 0 to N-1
R (n) is correlation, x(m), m=0-N-1, represents local preset signals; Y(m) index signal waveform;
Step 5: the similarity that step 4 calculates by bunch head side and pre-determined threshold G contrast, when similarity is greater than thresholding G, then regards as and there occurs the such synchronizing process of step one, step 2; If similarity is less than thresholding, then thinks and do not carry out synchronously;
Step 6: bunch head side according to step 5 identification there occurs successful bunch of head and synchronisation of nodes information transmit time, the time value in register R1 and R2 in step 3 is stored in register R3, R4 by FPGA, corresponding t1 and t4;
Step 7: in step one and step 2, gusset plate FPGA module detects the transmission and reception index signal of bunch head radio circuit, and records rising edge time of advent, and will be recorded to the time in shift register R5 and R6;
Step 8: in step one and step 2 two steps, the radio circuit transmission and reception index signal waveform that the FPGA of node side will detect, contrasts with preset signals waveform, and calculates wave-form similarity according to method same in step 4;
Step 9: the similarity calculated in step 8 and pre-determined threshold G contrast by node side, when similarity is greater than thresholding G, then regards as and there occurs the such synchronizing process of step one, step 2; If similarity is less than thresholding, then thinks and do not carry out synchronously;
Step 10: node side according to step 5 identification there occurs successful bunch of head and synchronisation of nodes information transmit time, the time value in register R5 and R6 in step 7 is stored in register R7, R8 by FPGA, corresponding t2 and t3;
Step 11: timestamp t1 and t4 obtained is formed packet by bunch head side, sends to node side;
Step 12: node side joint receives a bunch head side data bag, and parses t1 and t4, in conjunction with local t2 and t3, utilizes the clock jitter Offset between following formulae discovery node and bunch head:
Offset＝(t
2-t
1)-(t
4-t
3)/2
Step 13: according to the following equation, the clock that adjustment is local, is synchronized with a bunch head clock to node:
Clock is new=former+offset of clock
Step 14: terminate.
Embodiment 2
Preferred as technique scheme, this method can also be applied to corresponding multiple node side, a bunch of head side and carry out putting into practice in scene of clock alignment.
As shown in Figure 5, the clock synchronous being applied to wireless sensor network simplify information interacting method when the synchronizing information exchange method carried out is applied to multiple node, workload obviously obtains great simplification, and operating efficiency significantly promotes.
Fig. 6 simplifies the complete useful signal of a time synchronized often to be carried out in bunch head side of information interacting method, node side curve synoptic diagram according to step Q1-Q5 for a kind of clock synchronous being applied to wireless sensor network that the embodiment of the present invention provides, top curve is a bunch head side radio circuit transmission and reception signal designation curve, first broad pulse is the signal designation that when sending sync message, radio circuit exports, and short pulse is the Received signal strength instruction of bunch head radio circuit when receiving the confirmation message from node; Lower curve is the transmission and reception signal designation curve that node side radio circuit exports, and first broad pulse is the node signal designation that radio circuit exports when receiving sync message, and short pulse is the node signal designation that radio circuit exports when sending confirmation message.
Signal form is long pulse, pulse duration is T1, pulse spacing, width is T2, short pulse, pulse duration are the form of T3, and wherein the value of T1, T3 remains unchanged in synchronizing process, according to the definition mode for information frame in wireless sensor network IEEE802.15.4 agreement, there is following features: when send data message length one timing, hardware cell send experience time be identical; Under permission feedback working mode, after bunch head or node receive signal, the message length of the ACK message of feedback is a fixed value; T2 is relevant with path-length, but considers the coverage of wireless sensor network, and T2 change is very little.
Fig. 7 is the schematic diagram data that a kind of clock synchronous being applied to wireless sensor network simplifies that the final result of synchro system test is carried out in bunch head side of the experiment of information interacting method and node side, wherein abscissa represents bunch head side and node side clock jitter value, and unit is microsecond; The longitudinal axis represents the deviation frequency of repeatedly observation clock jitter gained bunch between head and node, and namely experiment have chosen 700 experiment samples, and the longitudinal axis represents the number of times that a certain deviate occurs in all samples.
Test data statistics is: average is 0, and variance is 0.3 μ s.(under node adopts 40-50ppm crystal oscillator condition)
Can obviously find out from above-mentioned chart, the method carries out calibration clock, and the deviation obtained is very little.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should described be as the criterion with the protection range of claim.
Claims (3)
1. the Precision Clock Synchronization being applied to wireless sensor network simplifies an information interacting method, it is characterized in that, comprises the following steps:
Q1: the clock of bunch head side is master clock, has the effect of reference clock, the main control unit of bunch head side determines the node ID that will carry out clock synchronous, and sends sync message signal to this node side, and the timestamp t1 sent by FPGA recording synchronism message signals;
Q2: node side clock needs to carry out clock alignment with a bunch head side, and the main control unit of node side receives sync message signal, and is recorded the timestamp t2 receiving sync message signal by FPGA;
Meanwhile, according to IEEE802.15.4 protocol specification, node, after successfully receiving message signals, to a bunch head side transmission and reception confirmation message signal, and stabs t3 by the transmitting time of FPGA registration confirmed message signals;
Q3: bunch head side joint receives the confirmation of receipt message signals from node side, and the time of reception stamp t4 being recorded this message signals by FPGA;
Q4: the main control unit of bunch head side is combined into packet by the transmitting time of recorded sync message signal stamp t1 with from the time of reception stamp t4 of the confirmation message signals of node side, is sent to node side;
Q5: the main control unit of node side receives packet, send confirmation message signal to a bunch head side, simultaneously according to the time of reception stamp t2 of the sync message signal of node sidelights record and the transmitting time stamp t3 of confirmation message signal, and t1 and t4 parsed from packet, the path delay of time between direct compute cluster head side and node side and the clock jitter Offset between leader cluster node, carry out local clock calibration, its concrete computational methods are:
t
2-t
1＝Delay+Offset
t
4-t
3＝Delay-Offset
Delay＝(t
2-t
1)+(t
4-t
3)/2
Offset＝(t
2-t
1)-(t
4-t
3)/2
Q6: the complete useful signal of a time synchronized is often carried out in bunch head side, node side form according to step Q1-Q5 is: long pulse, pulse duration are T1, pulse spacing, width are T2, short pulse, pulse duration are the form of T3, wherein the value of T1, T3 remains unchanged in synchronizing process, to meet IEEE802.15.4 protocol specification;
Q7: in above-mentioned steps Q1-Q4 process, wireless senser radio circuit provides the signal designation of transmitting and receiving data, can use as transmission and reception timestamp index signal, and the FPGA be connected with synchronous or confirmation message signal is whenever signal rising edge being detected, namely in register R1, record clock value corresponding to first rising edge, in register R2, record the clock value of second rising edge subsequently;
Q8: in above-mentioned steps Q1-Q4 process, the acquisition methods of timestamp is: the FPGA fixed signal be connected with synchronous or confirmation message signal and timestamp index signal carry out associative operation, and concrete operations are carried out according to following formula:
R(n)=（1/N）∑[x(m)y(m+n)]，
Wherein m changes from 0 to N-1; R (n) is correlation, x(m), m=0-N-1, represents local preset signals; Y(m) index signal waveform;
Setting coherent detection threshold value RTH, when the R (n) calculating gained is more than or equal to set threshold value RTH, the clock value recorded in register R1 and R2 in Q7 is corresponding timestamp, for a bunch head side, what store in R1 is that to store in t1, R2 is t4; For node side, what store in R1 is that to store in t2, R2 is t3;
Q9: node side main control unit utilizes the clock jitter Offset calculated in step Q5, can carry out real-time knot modification local clock, concrete method of adjustment is: Clock is new=former+offset of clock.
2. a kind of clock synchronous being applied to wireless sensor network according to claim 1 simplifies information interacting method, it is characterized in that, completing the method for a bunch of head side and node side aiming at all the time is comprise following steps:
Step one: the main control unit of bunch head side determines the node ID carrying out clock synchronous calibration, and send sync message signal to it;
Step 2: node side successfully receives the sync message signal that bunch head side is sent, and feeding back confirmation message gives bunch head side (ACK message);
Step 3: in step one and step 2 process, the FPGA module of bunch head side, detects the transmission and reception index signal of bunch head radio circuit, record rising edge time of advent, and will be recorded to the time in shift register R1 and R2;
Step 4: in step one and step 2 two steps, the radio circuit transmission and reception index signal waveform that the FPGA module of bunch head side will detect, contrasts with preset signals waveform, and calculates wave-form similarity;
The method of coherent detection is selected in control methods, carries out according to the following equation, and obtains correlation:
R(n)=（1/N）∑[x(m)y(m+n)]
Wherein m changes from 0 to N-1
R (n) is correlation, x(m), m=0-N-1, represents local preset signals; Y(m) index signal waveform;
Step 5: the similarity that step 4 calculates by bunch head side and pre-determined threshold G contrast, when similarity is greater than thresholding G, then regards as and there occurs the such synchronizing process of step one, step 2; If similarity is less than thresholding, then thinks and do not carry out synchronously;
Step 6: bunch head side according to step 5 identification there occurs successful bunch of head and synchronisation of nodes information transmit time, the time value in register R1 and R2 in step 3 is stored in register R3, R4 by FPGA, corresponding t1 and t4;
Step 7: in step one and step 2, node side FPGA module detects the transmission and reception index signal of bunch head radio circuit, and records rising edge time of advent, and will be recorded to the time in shift register R5 and R6;
Step 8: in step one and step 2 two steps, the radio circuit transmission and reception index signal waveform that the FPGA of node side will detect, contrasts with preset signals waveform, and calculates wave-form similarity according to method same in step 4;
Step 9: the similarity calculated in step 8 and pre-determined threshold G contrast by node side, when similarity is greater than thresholding G, then regards as and there occurs the such synchronizing process of step one, step 2; If similarity is less than thresholding, then thinks and do not carry out synchronously;
Step 10: node side according to step 5 identification there occurs successful bunch of head and synchronisation of nodes information transmit time, the time value in register R5 and R6 in step 7 is stored in register R7, R8 by FPGA, corresponding t2 and t3;
Step 11: timestamp t1 and t4 obtained is formed packet by bunch head side, sends to node side;
Step 12: node side joint receives a bunch head side data bag, and parses t1 and t4, in conjunction with local t2 and t3, utilizes the clock jitter Offset between following formulae discovery node and bunch head:
Offset＝(t
2-t
1)-(t
4-t
3)/2
Step 13: according to the following equation, the clock that adjustment is local, is synchronized with a bunch head clock in node side:
Clock is new=former+offset of clock
Step 14: terminate.
3. a kind of clock synchronous being applied to wireless sensor network according to claim 1 and 2 simplifies information interacting method, it is characterized in that, this method can also be applied to corresponding multiple node side, a bunch of head side and carry out putting into practice in scene of clock alignment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410093804.0A CN104918319B (en) | 2014-03-13 | 2014-03-13 | Clock synchronization simplified information interaction method applied to wireless sensor network |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410093804.0A CN104918319B (en) | 2014-03-13 | 2014-03-13 | Clock synchronization simplified information interaction method applied to wireless sensor network |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104918319A true CN104918319A (en) | 2015-09-16 |
| CN104918319B CN104918319B (en) | 2018-01-16 |
Family
ID=54086913
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410093804.0A Expired - Fee Related CN104918319B (en) | 2014-03-13 | 2014-03-13 | Clock synchronization simplified information interaction method applied to wireless sensor network |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104918319B (en) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105680976A (en) * | 2016-03-29 | 2016-06-15 | 中国电子科技集团公司第二十九研究所 | Distributed network time synchronization method |
| CN106028438A (en) * | 2016-05-18 | 2016-10-12 | 北京永安信通科技有限公司 | Method, device and system for base station time synchronization algorithm |
| CN106851817A (en) * | 2017-02-20 | 2017-06-13 | 成都物梦工场信息技术有限公司 | A kind of high-accuracy clock synchronization method between base station |
| CN107959968A (en) * | 2017-11-02 | 2018-04-24 | 中山大学 | A kind of clock synchronizing method for wireless sensor network of high accuracy, low overhead |
| WO2018177320A1 (en) * | 2017-03-29 | 2018-10-04 | 华为技术有限公司 | Clock processing method, access network device and terminal device |
| CN110337679A (en) * | 2017-02-17 | 2019-10-15 | 日本电信电话株式会社 | Sensing system and timestamp bearing calibration |
| CN110830139A (en) * | 2019-11-18 | 2020-02-21 | 广东博智林机器人有限公司 | Ultra-bandwidth positioning system and method |
| JP2020053842A (en) * | 2018-09-27 | 2020-04-02 | 沖電気工業株式会社 | Communication device aggregation device communication system and control program |
| CN111107623A (en) * | 2019-12-10 | 2020-05-05 | 陕西凌云电器集团有限公司 | System clock synchronization method |
| CN113242527A (en) * | 2021-05-17 | 2021-08-10 | 张衡 | Communication system based on wireless somatosensory inertia measurement module |
| WO2022037428A1 (en) * | 2020-08-19 | 2022-02-24 | 华为技术有限公司 | Clock synchronization method and apparatus |
| WO2022160283A1 (en) * | 2021-01-29 | 2022-08-04 | 华为技术有限公司 | Sampling method, sampling circuit, and clock synchronization method of distributed network |
| CN115225244A (en) * | 2022-07-14 | 2022-10-21 | 广东电网有限责任公司 | Low-voltage integrated reading electric energy meter clock time setting method, device, main equipment and medium |
| CN116846503A (en) * | 2023-08-02 | 2023-10-03 | 浙江海得智慧能源有限公司 | Data synchronization method, system and equipment for energy storage power station |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102196554A (en) * | 2011-06-10 | 2011-09-21 | 西安电子科技大学 | Method for realizing average clock synchronization of wireless sensor network through cluster averaging |
| CN102421187A (en) * | 2011-12-01 | 2012-04-18 | 北京航天测控技术有限公司 | High-accuracy clock synchronization method of wireless sensor network |
| CN102752844A (en) * | 2012-07-23 | 2012-10-24 | 重庆大学 | Multistage distribution method of channel resources of wireless sensor network |
| EP2675224A1 (en) * | 2012-06-13 | 2013-12-18 | Simmonds Precision Products, Inc. | System and method for synchronizing wireless devices without sending timestamp data |
-
2014
- 2014-03-13 CN CN201410093804.0A patent/CN104918319B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102196554A (en) * | 2011-06-10 | 2011-09-21 | 西安电子科技大学 | Method for realizing average clock synchronization of wireless sensor network through cluster averaging |
| CN102421187A (en) * | 2011-12-01 | 2012-04-18 | 北京航天测控技术有限公司 | High-accuracy clock synchronization method of wireless sensor network |
| EP2675224A1 (en) * | 2012-06-13 | 2013-12-18 | Simmonds Precision Products, Inc. | System and method for synchronizing wireless devices without sending timestamp data |
| CN102752844A (en) * | 2012-07-23 | 2012-10-24 | 重庆大学 | Multistage distribution method of channel resources of wireless sensor network |
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105680976B (en) * | 2016-03-29 | 2018-08-14 | 中国电子科技集团公司第二十九研究所 | A kind of distributed network method for synchronizing time |
| CN105680976A (en) * | 2016-03-29 | 2016-06-15 | 中国电子科技集团公司第二十九研究所 | Distributed network time synchronization method |
| CN106028438A (en) * | 2016-05-18 | 2016-10-12 | 北京永安信通科技有限公司 | Method, device and system for base station time synchronization algorithm |
| CN110337679A (en) * | 2017-02-17 | 2019-10-15 | 日本电信电话株式会社 | Sensing system and timestamp bearing calibration |
| CN110337679B (en) * | 2017-02-17 | 2021-12-31 | 日本电信电话株式会社 | Sensing system and timestamp correction method |
| CN106851817A (en) * | 2017-02-20 | 2017-06-13 | 成都物梦工场信息技术有限公司 | A kind of high-accuracy clock synchronization method between base station |
| WO2018177320A1 (en) * | 2017-03-29 | 2018-10-04 | 华为技术有限公司 | Clock processing method, access network device and terminal device |
| CN108667543A (en) * | 2017-03-29 | 2018-10-16 | 华为技术有限公司 | A kind of clock processing method, access network equipment and terminal device |
| CN107959968B (en) * | 2017-11-02 | 2021-02-02 | 中山大学 | High-precision low-overhead wireless sensor network clock synchronization method |
| CN107959968A (en) * | 2017-11-02 | 2018-04-24 | 中山大学 | A kind of clock synchronizing method for wireless sensor network of high accuracy, low overhead |
| JP7070290B2 (en) | 2018-09-27 | 2022-05-18 | 沖電気工業株式会社 | Communication equipment, aggregation equipment, communication systems and control programs |
| JP2020053842A (en) * | 2018-09-27 | 2020-04-02 | 沖電気工業株式会社 | Communication device aggregation device communication system and control program |
| CN110830139A (en) * | 2019-11-18 | 2020-02-21 | 广东博智林机器人有限公司 | Ultra-bandwidth positioning system and method |
| CN111107623A (en) * | 2019-12-10 | 2020-05-05 | 陕西凌云电器集团有限公司 | System clock synchronization method |
| WO2022037428A1 (en) * | 2020-08-19 | 2022-02-24 | 华为技术有限公司 | Clock synchronization method and apparatus |
| WO2022160283A1 (en) * | 2021-01-29 | 2022-08-04 | 华为技术有限公司 | Sampling method, sampling circuit, and clock synchronization method of distributed network |
| CN113242527A (en) * | 2021-05-17 | 2021-08-10 | 张衡 | Communication system based on wireless somatosensory inertia measurement module |
| CN115225244A (en) * | 2022-07-14 | 2022-10-21 | 广东电网有限责任公司 | Low-voltage integrated reading electric energy meter clock time setting method, device, main equipment and medium |
| CN115225244B (en) * | 2022-07-14 | 2023-08-18 | 广东电网有限责任公司 | Clock time setting method and device for low-voltage meter reading, main equipment and medium |
| CN116846503A (en) * | 2023-08-02 | 2023-10-03 | 浙江海得智慧能源有限公司 | Data synchronization method, system and equipment for energy storage power station |
| CN116846503B (en) * | 2023-08-02 | 2024-05-17 | 浙江海得智慧能源有限公司 | Data synchronization method, system and equipment for energy storage power station |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104918319B (en) | 2018-01-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104918319A (en) | Clock synchronization simplified information exchange method applied to wireless sensor network | |
| Mahmood et al. | Time synchronization in 5G wireless edge: Requirements and solutions for critical-MTC | |
| CN106488550B (en) | Determine the method and apparatus of terminal Yu base station clock time deviation | |
| CN108650051B (en) | The clock synchronization apparatus and method of general devices at full hardware single step 1588 | |
| CN106921456B (en) | Multi-hop wireless backhaul network time synchronization error compensation method based on PTP protocol | |
| US10284359B2 (en) | Clock synchronization frequency offset estimation method adapted to WIA-PA network | |
| CN104507156B (en) | For the time synchronization improved method based on IEEE 1588PTP mechanism of wireless network | |
| CN102869087B (en) | The hardware time synchronization implementation method of industry Internet of Things chip | |
| CN102111258A (en) | Clock synchronization method, equipment and system | |
| CN102013931B (en) | Time synchronization method and system, salve timing device and main timing device | |
| CN101778405B (en) | Method and system for synchronous acquisition of wireless sensor network for structural health monitoring | |
| KR101988274B1 (en) | Data transmission method, communication device, and communication system | |
| CN102244603B (en) | Method, equipment and system for transmitting message bearing time | |
| CN108880727B (en) | A kind of precision clock synchronization realizing method based on PTPd2 agreement | |
| WO2017101528A1 (en) | Method and device for clock link switching and base station | |
| CN103109501A (en) | Network time delay measuring method, device and system | |
| CN105577349A (en) | Airborne network IEEE1588 protocol master-slave clock port synchronization method | |
| CN102006157A (en) | Time synchronization method and system | |
| CN104243079A (en) | Microsecond clock synchronization method for real-time Ethernet | |
| CN106712885A (en) | Clock synchronization method, network device and network system | |
| CN1199493C (en) | Wireless network with user time synchronization | |
| CN104579623A (en) | Network time-setting system and method for secondary equipment of electric power system | |
| CN104993897B (en) | A kind of pre-filled timestamp synchronous method suitable for WIA PA networks | |
| CN108183762B (en) | The method for synchronizing time of RapidIO network system and RapidIO network system | |
| WO2010102565A1 (en) | Method, apparatus and system for time synchronization |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20170517 Address after: 100041 Beijing City, Shijingshan District Jin Yuan Zhuang Road No. 5 Applicant after: Beifang Polytechnic Univ. Applicant after: Harvest Technology (Beijing) Co., Ltd. Address before: 100000 Beijing city Shijingshan District Jinyuan Road No. 5 Applicant before: Beifang Polytechnic Univ. |
|
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20171213 Address after: 100041 Beijing City, Shijingshan District Jin Yuan Zhuang Road No. 5 Applicant after: Beifang Polytechnic Univ. Address before: 100041 Beijing City, Shijingshan District Jin Yuan Zhuang Road No. 5 Applicant before: Beifang Polytechnic Univ. Applicant before: Harvest Technology (Beijing) Co., Ltd. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180116 Termination date: 20210313 |