CN104918319B - Clock synchronization simplified information interaction method applied to wireless sensor network - Google Patents
Clock synchronization simplified information interaction method applied to wireless sensor network Download PDFInfo
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- CN104918319B CN104918319B CN201410093804.0A CN201410093804A CN104918319B CN 104918319 B CN104918319 B CN 104918319B CN 201410093804 A CN201410093804 A CN 201410093804A CN 104918319 B CN104918319 B CN 104918319B
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Abstract
The invention provides a clock synchronization simplified information interaction method applied to a wireless sensor network, which comprises the following steps: the cluster head side sends a message and records a timestamp t1, and the node side receives the message and records a timestamp t 2; sending feedback by the node side and recording a timestamp t 3; the cluster head side receives the feedback message and records a time stamp t 4; the cluster head side combines the time stamps t1 and t4 into a data packet and sends the data packet to the node side; the node side calculates the clock Offset according to the time stamps t2 and t3 and t1 and t4 analyzed from the data packet, and performs local clock calibration, the method is simple, the synchronization time is greatly reduced, the realization is convenient, and meanwhile, the IEEE1588 precise clock synchronization protocol and the IEEE802.15.4 wireless sensor network protocol are combined, at least 2 message sending and receiving times are omitted in each time synchronization process, the reliability is high, and the working efficiency is improved.
Description
Technical field
It is more particularly to a kind of to be applied to wireless pass the present invention relates to the Clock Synchronization Technology field in wireless sensor network
The clock of sensor network synchronously simplifies information interacting method.
Background technology
Precision clock simultaneous techniques is widely used in intelligent grid distributed equipment room, distributed monitoring and control
In the increasing technical field such as system, turn into the focus of people's concern and research.
Current Clock Synchronization Technology, it is generally divided into wired and wireless two kinds.When cable clock simultaneous techniques is traditional
Clock simultaneous techniques, using IEEE1588 accurate clock synchronization protocols, as shown in figure 1, accuracy is good, calculation formula is simple, but because
It is just gradually wireless under many application scenarios to be limited by track laying, the difficult in maintenance, factor such as dumb of layouting
Technology is substituted.
Time synchronization in wireless sensor networks at present, generally use are direct by IEEE1588 accurate clock synchronization protocols
Applied to the protocol stack under IEEE802.15.4 wireless sensor network standards, utilized between reference clock terminal and synchronous terminal
The sending/receiving formula of existing protocol stack synchronizes information transmission, as shown in Fig. 2 still this method is sufficiently complex, it is necessary to connect
Multiple information are received and sent to realize the calculating in the path delay of time of synchronous two equipment rooms of clock and clock jitter, are added wireless
The system message expense of network, extends lock in time, furthermore, it is contemplated that the particularity of wireless sensor network itself, is being passed
When random disturbances or bursty interference in defeated channel be present, easily cause synchronizing information loss, as long as and conventional method wherein
One dropout or mistake, i.e., it can directly result in clock synchronization failure and resend next synchronizing information, it is necessary to wait,
This will cause the further extension of lock in time, further increases the message transmission overhead of Radio Network System, influences clock
Synchronization accuracy.
The content of the invention
Asked for existing time synchronization in wireless sensor networks synchronization delayed time is uncertain, system message expense is big etc.
Topic, the purpose of the embodiment of the present invention are to provide that a kind of synchronization delayed time is small, synchronization message expense is small is applied to wireless sensor network
The clock of network synchronously simplifies information interacting method, is wirelessly passed with reference to IEEE1588 accurate clock synchronization protocols and IEEE802.15.4
Sensor procotol, 2 information are at least omitted in time synchronization process each time and send and receive the cycle, can be applied to intelligent electricity
The synchronised clock of net distributed equipment room, distributed monitoring and control system is established and kept time.
In order to achieve the above object, the embodiment of the present invention provides following technical scheme：
A kind of clock applied to wireless sensor network synchronously simplifies information interacting method, it is characterised in that including with
Lower step：
Q1：The clock of cluster head side is master clock, has the function that reference clock, and the main control unit of cluster head side determines to carry out
The synchronous node ID of clock, and sync message signal is sent to the node side, and sent by FPGA recording synchronisms message signals
Timestamp t1；
Q2：Node side clock needs to carry out clock alignment with cluster head side, and the main control unit of node side receives sync message
Signal, and the timestamp t2 for receiving sync message signal is recorded by FPGA；
Meanwhile according to IEEE802.15.4 protocol specifications, node sends to cluster head side and connect after message signals are properly received
Confirmation message signal is received, and by the transmission timestamp t3 of FPGA registration confirmed message signals；
Q3：Cluster head side joint receives the reception confirmation message signal from node side, and records the message signals by FPGA
Receive timestamp t4；
Q4：The main control unit of cluster head side is by the transmission timestamp t1 of the sync message signal recorded and from node side
The reception timestamp t4 of confirmation message signal is combined into packet, is sent to node side；
Q5：The main control unit of node side receives packet, sends confirmation message signal and gives cluster head side, while according to node
The reception timestamp t2 of sync message signal and the transmission timestamp t3 of confirmation message signal of sidelights record, and from packet
The t1 and t4 parsed, directly calculate the path delay of time between cluster head side and node side and the clock jitter between leader cluster node
Offset, carries out local clock calibration, and its specific computational methods is：
t2-t1=Delay+Offset
t4-t3=Delay-Offset
Delay=(t2-t1)+(t4-t3)/2
Offset=(t2-t1)-(t4-t3)/2
Q6：Cluster head side, node side often carry out the form of the complete useful signal of a time synchronized according to step Q1-Q5
For：Long pulse, pulse width T1, pulse spacing, width T2, short pulse, the wherein form that pulse width is T3, T1, T3
Value keep constant in synchronizing process, to meet IEEE802.15.4 protocol specifications；
Q7：During above-mentioned steps Q1-Q4, the signal that wireless senser radio circuit provides transmitting and receiving data refers to
Show, transmission can be used as to receive timestamp indication signal and used, the FPGA being connected with radio circuit indication signal is whenever detection
To signal rising edge, i.e., clock value corresponding to first rising edge is recorded in register R1, recorded in register R2 subsequent
Second rising edge clock value；
Q8：During above-mentioned steps Q1-Q4, the acquisition methods of timestamp are：It is connected with synchronous or confirmation message signal
The FPGA connect carries out associative operation with fixed signal and timestamp indication signal, and concrete operations are carried out according to equation below：
R(n)=（1/N）∑ [x (m) y (m+n)],
Wherein m changes from 0 to N-1；R (n) is correlation, x（m）, m=0-N-1, represent local preset signals；y（m）Instruction
Signal waveform；
Coherent detection threshold value RTH is set, when the R (n) for calculating gained is more than or equal to set threshold value RTH,
The clock value recorded in Q7 in register R1 and R2 is corresponding timestamp, for cluster head side, is stored in R1
It is t1, that stored in R2 is t4；For node side, that stored in R1 is t2, and that stored in R2 is t3；
Q9：Node side main control unit utilizes the clock jitter Offset calculated in step Q5, can carry out adjustment section in real time
Point local clock, specific method of adjustment are：Clock is new=clock originals+offset.
A kind of clock applied to wireless sensor network provided in an embodiment of the present invention synchronously simplifies information interacting method,
Method is simple, greatly reduces synchronization message expense, reduces the possibility of error, and has simplified calculating cycle, is easy to
It is each with reference to IEEE1588 accurate clock synchronization protocols and IEEE802.15.4 wireless sensor network protocols while realization
At least omit 2 synchronization messages in secondary time synchronization process to send and receive, reliability is high, improves operating efficiency.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, without having to pay creative labor, may be used also
To obtain other accompanying drawings according to these accompanying drawings.
Fig. 1 is that the synchronizing information within a synchronizing cycle of IEEE1588 accurate clock synchronization protocols in the prior art is handed over
Mutual schematic diagram.
Fig. 2 is IEEE802.15.4 wireless sensor network standards method in the prior art within a synchronizing cycle
Synchronizing information interacts schematic diagram.
Fig. 3 is that a kind of clock applied to wireless sensor network that the embodiment of the present invention 1 provides synchronously simplifies information friendship
The interaction schematic diagram of the synchronizing information within a synchronizing cycle of mutual method.
Fig. 4 is that a kind of clock applied to wireless sensor network that the embodiment of the present invention 1 provides synchronously simplifies information friendship
The system structure diagram of mutual method.
Fig. 5 is that a kind of clock applied to wireless sensor network that the embodiment of the present invention 2 provides synchronously simplifies information friendship
The interaction schematic diagram of the synchronizing information when carrying out multiple node sides of mutual method.
Fig. 6 is that a kind of clock applied to wireless sensor network provided in an embodiment of the present invention synchronously simplifies information exchange
Cluster head side, the node side of method often carry out the curve synoptic diagram of the complete useful signal of a time synchronized according to step Q1-Q5.
Fig. 7 is a kind of cluster head side for the experiment that clock applied to wireless sensor network synchronously simplifies information interacting method
The schematic diagram data of the final result of system test is synchronized with node side.
Embodiment
Below in conjunction with the accompanying drawing of the present invention, technical scheme is clearly and completely described, it is clear that institute
The embodiment of description is only part of the embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention,
The every other embodiment that those of ordinary skill in the art are obtained under the premise of creative work is not made, belongs to this hair
The scope of bright protection.
Fig. 1 is that the synchronizing information within a synchronizing cycle of IEEE1588 accurate clock synchronization protocols interacts schematic diagram,
Fig. 2 is the interaction signal of the synchronizing information within a synchronizing cycle of IEEE802.15.4 wireless sensor network standards methods
Figure, Fig. 3, Fig. 5 are that the synchronizing information provided in an embodiment of the present invention within a synchronizing cycle interacts schematic diagram, can by figure contrast
Find out, synchronizing information exchange method provided in an embodiment of the present invention is more simple and practical, and reliability is also explained in detail at this place
State.
Embodiment 1
In present specification, cluster head side is master clock, has the function that reference clock, and node side can have multiple, and Fig. 3 is
1 node to be synchronized, the synchronizing information exchange method that Fig. 5 is multiple nodes to be synchronized, node side clock stability difference, it is necessary to
Cluster head side carries out clock alignment.In practical application, a typically cluster head side will enter row clock synchronization with multiple nodes, and cluster head is
One clock lock in time section of each node distribution, within the time period complete one synchronizing cycle task.
As shown in Figure 3-4, it is specifically described the content of the invention that the application refers to is how to complete a complete job below
Cycle, the method flow of a cluster head side and a nodal clock synchronization, the Clock Synchronization Procedure within a synchronizing cycle
Exemplified by illustrate, this method includes：
Step 1：The main control unit of cluster head side determines the node ID into row clock synchronous calibration, and is sent to synchronization
Message signals；
Step 2：Node side is successfully received the sync message signal sent cluster head side, and feeding back confirmation message is to cluster head
Side（ACK message）；
Step 3：During step 1 and step 2, the FPGA module of cluster head side, the transmission of cluster head radio circuit is detected
Indication signal is received, records rising edge arrival time, and will recorded the time in shift register R1 and R2；
Step 4：In two steps of step 1 and step 2, radio circuit that the FPGA module of cluster head side will detect
Send and receive indication signal waveform, contrasted with preset signals waveform, and calculate wave-form similarity；
The method that coherent detection is selected in control methods, is carried out, and obtain correlation according to the following equation：
R(n)=（1/N）∑[x(m)y(m+n)]
Wherein m changes from 0 to N-1
R (n) is correlation, x（m）, m=0-N-1, represent local preset signals；y（m）Indication signal waveform；
Step 5：Cluster head side is contrasted the similarity that step 4 calculates and pre-determined threshold G, when similarity is more than thresholding
G, then regard as that there occurs Step 1: synchronizing process as step 2；If similarity is less than thresholding, then it is assumed that does not carry out same
Step；
Step 6：When cluster head side is transmitted according to step 5 identification there occurs successful cluster head and node synchronizing information, FPGA
Time value in register R1 and R2 in step 3 is stored into register R3, R4, corresponding t1 and t4；
Step 7：In step 1 and step 2, the transmission of gusset plate FPGA module detection cluster head radio circuit, which receives, to be referred to
Show signal, and record rising edge arrival time, and will recorded the time in shift register R5 and R6；
Step 8：In two steps of step 1 and step 2, the FPGA of node side sends the radio circuit detected
Indication signal waveform is received, is contrasted with preset signals waveform, and it is similar according to method calculating waveform same in step 4
Degree；
Step 9：Node side is contrasted the similarity calculated in step 8 and pre-determined threshold G, when similarity is more than door
G is limited, then regards as that there occurs Step 1: synchronizing process as step 2；If similarity is less than thresholding, then it is assumed that does not carry out
It is synchronous；
Step 10：When node side is transmitted according to step 5 identification there occurs successful cluster head and node synchronizing information, FPGA
Time value in register R5 and R6 in step 7 is stored into register R7, R8, corresponding t2 and t3；
Step 11：Timestamp t1 and t4 the composition data bag of acquisition is sent to node side by cluster head side；
Step 12：Node side joint receives cluster head side data bag, and parses t1 and t4, with reference to the t2 and t3 of local, profit
With the clock jitter Offset between following formula calculate nodes and cluster head：
Offset=(t2-t1)-(t4-t3)/2
Step 13：Node according to the following equation, adjusts local clock, is synchronized with cluster head clock：
Clock is new=clock originals+offset
Step 14：Terminate.
Embodiment 2
As the preferred of above-mentioned technical proposal, this method can also correspond to multiple node sides applied to a cluster head side and carry out
Clock alignment is put into practice in scene.
As shown in figure 5, the clock applied to wireless sensor network synchronously simplifies the same when what is carried out of information interacting method
When step information interacting method is applied to multiple nodes, workload has substantially obtained great simplification, and operating efficiency is substantially improved.
Fig. 6 is that a kind of clock applied to wireless sensor network provided in an embodiment of the present invention synchronously simplifies information exchange
Cluster head side, the node side of method often carry out the curve synoptic diagram of the complete useful signal of a time synchronized according to step Q1-Q5,
Top curve is that cluster head side radio circuit sends reception signal indicative curve, radio frequency when first broad pulse is sends sync message
The signal designation of circuit output, short pulse are that the reception signal of cluster head radio circuit when receiving the confirmation message from node refers to
Show；Lower curve is the transmission reception signal indicative curve of node side radio circuit output, and first broad pulse receives for node
The signal designation exported to radio circuit during sync message, short pulse are the letter of radio circuit output when node sends confirmation message
Number instruction.
Signal form is long pulse, and pulse width T1, in the pulse spacing, width T2, short pulse, pulse width are T3's
The value of form, wherein T1, T3 keeps constant in synchronizing process, according to pin in wireless sensor network IEEE802.15.4 agreements
To the definition mode of information frame, following features be present：When the timing of message length one for sending data, hardware cell, which is sent, to be undergone
Time be identical；In the case where allowing feedback working mode, after cluster head or node receive signal, the ACK messages of feedback
Message length be a fixed value；T2 is relevant with path-length, but in view of the coverage of wireless sensor network, T2
Change is very small.
Fig. 7 is a kind of cluster head side for the experiment that clock applied to wireless sensor network synchronously simplifies information interacting method
The schematic diagram data of the final result of system test is synchronized with node side, when wherein abscissa represents cluster head side with node side
Clock deviation, unit are microsecond；The longitudinal axis represents the repeatedly deviation frequency between observation cluster head and node obtained by clock jitter, that is, tests
700 experiment samples are have chosen, the longitudinal axis represents the number that a certain deviation occurs in all samples.
Test data statistical result is：Average is 0, and variance is 0.3 μ s.（Under the conditions of node uses 40-50ppm crystal oscillators）
It will be evident that this method carries out calibration clock from above-mentioned chart, obtained deviation is very small.
The foregoing is only a specific embodiment of the invention, but protection scope of the present invention is not limited thereto, any
Those familiar with the art the invention discloses technical scope in, change or replacement can be readily occurred in, should all be contained
Cover within protection scope of the present invention.Therefore, protection scope of the present invention described should be defined by scope of the claims.
Claims (2)
1. a kind of precision clock applied to wireless sensor network synchronously simplifies information interacting method, it is characterised in that including
Following steps：
Q1：The clock of cluster head side is master clock, has the function that reference clock, and the main control unit of cluster head side determines to enter row clock
Synchronous node ID, and sync message signal is sent to the node side, and by FPGA recording synchronisms message signals send when
Between stab t1；
Q2：Node side clock needs to carry out clock alignment with cluster head side, and the main control unit of node side receives sync message signal,
And the timestamp t2 for receiving sync message signal is recorded by FPGA；
Meanwhile according to IEEE802.15.4 protocol specifications, node sends to cluster head side and received really after message signals are properly received
Recognize message signals, and by the transmission timestamp t3 of FPGA registration confirmed message signals；
Q3：Cluster head side joint receives the reception confirmation message signal from node side, and the reception of the message signals is recorded by FPGA
Timestamp t4；
Q4：The main control unit of cluster head side is by the transmission timestamp t1 of the sync message signal recorded and confirmation from node side
The reception timestamp t4 of message signals is combined into packet, is sent to node side；
Q5：The main control unit of node side receives packet, sends confirmation message signal and gives cluster head side, while according to node sidelights
The reception timestamp t2 of the sync message signal of the record and transmission timestamp t3 of confirmation message signal, and parsed from packet
The t1 and t4 gone out, directly calculate the clock jitter between the path delay of time Delay and leader cluster node between cluster head side and node side
Offset, carries out local clock calibration, and its specific computational methods is：
T2-t1=Delay+Offset
T4-t3=Delay-Offset
Delay=(t2-t1)+(t4-t3)/2
Offset=(t2-t1)-(t4-t3)/2
Q6：The form that cluster head side, node side often carry out the complete useful signal of a time synchronized according to step Q1-Q5 is：It is long
Pulse, pulse width T1, pulse spacing, width T2, short pulse, the form that pulse width is T3, wherein T1, T3 value exist
Keep constant in synchronizing process, to meet IEEE802.15.4 protocol specifications；
Q7：During above-mentioned steps Q1-Q4, the wireless senser radio circuit of cluster head side provides the letter of transmitting and receiving data
Number instruction, can be used as to send and receive timestamp indication signal and use, and the FPGA being connected with synchronous or confirmation message signal
Whenever the signal rising edge for detecting synchronization or confirmation message signal, i.e., recorded in register R1 corresponding to first rising edge
Clock value, the clock value of second subsequent rising edge is recorded in register R2；
Q8：During above-mentioned steps Q1-Q4, the acquisition methods of timestamp are：It is connected with synchronous or confirmation message signal
FPGA carries out associative operation with fixed signal and timestamp indication signal, and concrete operations are carried out according to equation below：
R (n)=(1/N) Σ [x (m) y (m+n)],
Wherein m changes from 0 to N-1；R (n) is correlation, x (m), m=0-N-1, represents fixed signal；Y (m) refers to for timestamp
Show signal；
Coherent detection threshold value RTH is set, when the R (n) for calculating gained is more than or equal to set threshold value RTH, is deposited in Q7
The clock value recorded in device R1 and R2 is corresponding timestamp, and for cluster head side, that stored in R1 is t1, and what is stored in R2 is
t4；For node side, that stored in R1 is t2, and that stored in R2 is t3；
Q9：Node side main control unit utilizes the clock jitter Offset calculated in step Q5, can carry out adjusting node sheet in real time
Ground clock, specific method of adjustment are：Clock is new=clock originals+offset.
2. a kind of clock applied to wireless sensor network according to claim 1 synchronously simplifies information exchange side
Method, it is characterised in that this method can also be applied to a cluster head side and correspond to the practice field that multiple node sides carry out clock alignment
Jing Zhong.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105680976B (en) * | 2016-03-29 | 2018-08-14 | 中国电子科技集团公司第二十九研究所 | A kind of distributed network method for synchronizing time |
| CN106028438B (en) * | 2016-05-18 | 2018-11-13 | 北京永安信通科技股份有限公司 | The methods, devices and systems of base station time synchronism algorithm |
| JP6649517B2 (en) * | 2017-02-17 | 2020-02-19 | 日本電信電話株式会社 | Sensing system and time stamp correction method |
| CN106851817A (en) * | 2017-02-20 | 2017-06-13 | 成都物梦工场信息技术有限公司 | A kind of high-accuracy clock synchronization method between base station |
| CN108667543B (en) * | 2017-03-29 | 2019-12-13 | 华为技术有限公司 | Clock processing method, access network equipment and terminal equipment |
| CN107959968B (en) * | 2017-11-02 | 2021-02-02 | 中山大学 | High-precision low-overhead wireless sensor network clock synchronization method |
| JP7070290B2 (en) * | 2018-09-27 | 2022-05-18 | 沖電気工業株式会社 | Communication equipment, aggregation equipment, communication systems and control programs |
| CN113411151B (en) * | 2019-11-18 | 2022-07-12 | 广东博智林机器人有限公司 | Ultra-bandwidth positioning system |
| CN111107623A (en) * | 2019-12-10 | 2020-05-05 | 陕西凌云电器集团有限公司 | System clock synchronization method |
| CN114079525A (en) * | 2020-08-19 | 2022-02-22 | 华为技术有限公司 | Clock synchronization method and device |
| CN116671193A (en) * | 2021-01-29 | 2023-08-29 | 华为技术有限公司 | Sampling method, sampling circuit and clock synchronization method of distributed network |
| CN113242527B (en) * | 2021-05-17 | 2023-06-16 | 张衡 | Communication system based on wireless somatosensory inertial measurement module |
| CN115225244B (en) * | 2022-07-14 | 2023-08-18 | 广东电网有限责任公司 | Clock time setting method and device for low-voltage meter reading, main equipment and medium |
| CN116846503A (en) * | 2023-08-02 | 2023-10-03 | 浙江海得智慧能源有限公司 | Data synchronization method, system and equipment for energy storage power station |
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