CN104916593A - 封装件和制造封装件的方法 - Google Patents
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Abstract
提供了一种封装件和制造封装件的方法。所述封装件包括:基底,具有第一表面和背对第一表面的第二表面,基底中设置有多个焊盘;第一结合件和第二结合件,设置在基底上,第二结合件位于第一结合件的周围;芯片,设置在第一结合件上并通过引线电连接到所述多个焊盘;阻挡件,设置在第二结合件上;包封构件,设置在阻挡件的内侧以包封芯片第一结合件和引线。
Description
技术领域
本发明涉及封装领域,具体涉及一种封装件和制造封装件的方法。
背景技术
现有封装技术通常采用点胶或者模塑成型的方法来对芯片提供保护,防止芯片受到环境影响及外力影响而失效。
图1示出了相关技术的一种点胶封装件的示意性剖视图,其中芯片102通过包括结合剂的粘结层A设置在结合件101a上,利用引线W将芯片102与设置在基底100上的焊盘(未示出)电连接,然后采用点胶的方法利用包封构件103进行包封。点胶封装不易控制封装件的尺寸精度。此外,该种封装还具有机械强度低的缺点,使得不能满足高强度的机械测试要求。
图2示出了相关技术的一种模塑封装件的示意性剖视图,其中芯片202通过包括结合剂的粘结层A设置在结合件201a上,利用引线W将芯片202与设置在基底200上的焊盘(未示出)电连接,然后采用模塑的方法利用包封构件203进行包封。该种封装件虽然能够易于控制封装件的尺寸精度,但模塑料与基底的焊点部位结合力较弱,容易产生分层,从而导致失效。
发明内容
本发明的一个目的在于提供一种能够容易精确控制封装尺寸的封装件和制造该封装件的方法。
本发明的另一目的在于提供一种可以改善整体机械性能的封装件和制造该封装件的方法。
根据本发明的一方面,提供了一种封装件,所述封装件包括:基底,具有第一表面和背对第一表面的第二表面,基底中设置有多个焊盘;第一结合件和第二结合件,设置在基底的第二表面上,第二结合件位于第一结合件的周围;芯片,设置在第一结合件上,并通过引线电连接到所述多个焊盘;阻挡件,设置在第二结合件上;包封构件,设置在阻挡件的内侧以包封芯片、第一结合件和引线。
根据本发明的示例性实施例,阻挡件可以包括预置挡坝和/或焊锡筑坝。
根据本发明的示例性实施例,阻挡件可以为环形,此时,芯片可以设置在阻挡件的环形中心。
根据本发明的示例性实施例,阻挡件可以包括陶瓷、塑料、金属和焊料中的至少一种。
根据本发明的示例性实施例,阻挡件可以与结合件之间设置有金属图案层。
根据本发明的另一方面,提供了一种制造封装件的方法,所述方法包括:设置基底,基底具有第一表面和背对第一表面的第二表面,基底中设置有多个焊盘;在基底的第二表面上设置第一结合件和第二结合件,其中,第二结合件位于第一结合件的周围;在第一结合件上设置芯片,并在第二结合件上设置阻挡件;通过引线将芯片与焊盘电连接;将包封构件设置在阻挡件的内侧,以包封芯片、第一结合件和引线。
根据本发明的示例性实施例,阻挡件可以包括预置挡坝。
根据本发明的示例性实施例,可以将阻挡件的数量设置为一个并可以设置为具有环形结构,可以将芯片设置在阻挡件的环形结构的中心。
根据本发明的示例性实施例,可以将阻挡件的数量设置为多个,其中,所述多个阻挡件组合在一起可以具有环形结构。
根据本发明的示例性实施例,阻挡件可以包括陶瓷、塑料、金属和焊料中的至少一种。
根据本发明的示例性实施例,阻挡件可以包括焊锡筑坝。
根据本发明的示例性实施例,设置阻挡层的步骤可以包括:在第二结合件上设置金属图案层,然后在金属图案层上设置阻挡件以覆盖金属图案层。
根据本发明的示例性实施例,金属图案层可以包括铜。
根据本发明的封装件及其制造方法,通过在第二结合件上设置诸如预置挡坝或焊锡筑坝的环状阻挡件,能够容易地控制封装件的尺寸。此外,根据本发明的封装件仍采用点胶封装,因此避免了模塑封装容易分层的弱点。
附图说明
通过结合附图的示例性实施例的以下描述,本发明的各方面将变得更加容易理解,在附图中:
图1是示出相关技术的一种点胶结构的封装件的示意性剖视图;
图2是示出相关技术的一种模塑结构的封装件的示意性剖视图;
图3A是示出根据本发明的一个示例性实施例的封装件的示意性剖视图;
图3B是示出图3A的封装件的示意性俯视图;
图3C是示出根据本发明的另一示例性实施例的封装件的示意性剖视图;
图4是示出根据本发明的另一示例性实施例的封装件的示意性剖视图;
图5A至图5C是示出根据本发明的一个示例性实施例的制造封装件的方法的示意性剖视图;
图6A至图6C是示出根据本发明的另一示例性实施例的制造封装件的示意性剖视图。
具体实施方式
在下文中,将通过参考附图对示例性实施例进行解释来详细描述本发明构思。然而,本发明构思可以按照多种不同形式具体实施,而不应当解释为限制为本文所阐述的各实施例;相反,提供这些实施例是为了使得本公开是清楚且完整的,并且将向本领域普通技术人员充分地传达本发明构思。在附图中,相同的附图标记表示相同的元件。此外,各个元件和区域是示意性示出的。因而,本发明构思不限于图中所示出的相对尺寸或距离。将要理解的是,尽管在这里会使用术语第一、第二、第三等来描述各个元件、部件、区域、层和/或部分,但这些元件、部件、区域、层和/或部分不应当被这些术语限制。这些术语仅仅用于将一个元件、部件、区域、层或部分与另一个元件、部件、区域、层或部分区分开。因此,下面讨论的第一元件、第一部件、第一区域、第一层或第一部分可以被称为第二元件、第二部件、第二区域、第二层或第二部分,而没有背离本发明构思的教导。
这里使用的术语是出于描述具体实施例的目的,而不意图限制本发明构思。如这里所使用的,单数形式的“一个”、“一种”、“该”、“所述”也意图包括复数形式,除非在上下文中清楚地另外指出。还将要理解的是,术语“包括”和/或“包括……的”当用在本说明书中时,说明存在所陈述的特征、整体、步骤、操作、元件和/或组件,但是不排除存在或添加一个或更多个其它特征、整体、步骤、操作、元件、组件和/或它们的组。
为了便于描述,这里可以使用空间相对术语来描述图中所示出的一个元件或特征与其它元件或特征的关系,诸如“在……之下”、“在…….下方”、“下面的”、“在……上方”和“上面的”等。将理解的是,这些空间术语意图涵盖使用中或操作中的器件的在图中所示的方位之外的不同方位。例如,如果附图中的器件被翻转,则描述为在其它元件或特征“之下”或“下方”的元件将被定位为在其它元件或特征“上方”。因此,示例性术语“在……下方”可以涵盖“下方”和“上方”两种方位。器件可以被另外地定位(旋转90度或者在其它方位),并相应地解释在这里使用的空间相对描述语。
参照作为示例性实施例的理想实施例(以及中间结构)的示意图的剖视图来描述示例性实施例。如此,例如由制造技术和/或公差所导致的图示形状的变化是可预期的。因此,不应当将示例性实施例解释为局限于在这里所示出的区域的特定形状,而是包括了例如由制造导致的形状方面的偏差。
除非另外限定,否则在本说明书中使用的术语(包括技术术语和科学术语)具有与本领域普通技术人员所通常理解的含义相同的含义。在通用词典中定义的术语应当被解释为具有与相关技术背景下的含义相同的含义,并且除非在本说明书中进行了限定,否则不应以理想化的或过于形式化的意思来解释它们。
如这里所使用的,术语“和/或”包括一个或更多个相关所列项的任意和全部组合。
以下,将结合图附图来详细描述根据本发明的示例性实施例的封装件。
图3A是示出根据本发明的一个示例性实施例的封装件的示意性剖视图,图3B是示出图3的封装件的示意性俯视图,图3C是示出根据本发明的另一示例性实施例的封装件的示意性剖视图。以下,将结合图3A至图3C来描述根据本发明的示例性实施例的两种封装件。贯穿整个说明书,同样的附图标记始终指示为同样的元件。
参照图3A,根据本发明的示例性实施例的封装件包括:基底300,具有第一表面和背对第一表面的第二表面,基底300中设置有多个焊盘(未示出);第一结合件301a和第二结合件301b,设置在基底300的第二表面上,第二结合件301b位于第一结合件301a的周围;芯片302,设置在第一结合件301a上,并通过引线W与设置在基底300中的焊盘电连接;阻挡件304a,设置在第二结合件301b上;包封构件303,设置在阻挡件304a的内侧以包封芯片302、第一结合件301a和引线W。
根据本发明的示例性实施例,芯片302可以通过包括结合剂的粘结层A固定在第一结合件301a上,从而固定在基底300的第二表面上,但本发明不限于此。可以省略第一结合件301a。更具体地,可以使用诸如结合剂的粘结层A来将芯片302固定到基底300上,即,芯片302通过结合剂直接设置在基底300上,其中,由结合剂形成的粘结层A可以直接用作为第一结合件301a。
根据本发明的示例性实施例,阻挡件304a可以通过诸如结合剂的粘结层A固定在第二结合件301b上,从而固定在基底300上,但本发明不限于此。可以省略第二结合件301b。更具体地,可以使用诸如结合剂的粘结层A来将阻挡件304a固定到基底300上,即,阻挡件304a通过包括结合剂的粘结层A直接设置在基底300上,其中,结合剂形成的粘结层A可以直接用作为第二结合件301b。
根据本发明的示例性实施例,第二结合件301b具有面对基底的第一表面和背对基底的第二表面。第二表面可以具有平坦的形状,然而,根据工艺需要,第二表面也可以设置为具有凹凸不平的结构,或者可以设置为具有能够容纳或部分容纳金属图案层304的结构,这将在后面来具体描述。
根据封装件的需要,阻挡件304a可以具有预定的形状,以将芯片302包围在其中。根据本发明的示例性实施例,如图3B中所示,阻挡件304a可以具有环形的形状,且当阻挡件304a为环形形状时,芯片302可以设置在阻挡件304a的环形形状的中心。此外,第二结合件301b可以具有与阻挡件304a相配合的形状。具体地,阻挡件304a可以设置成环形形状,芯片302可以设置在环形形状的中心。此时,第二结合件301b可以具有与阻挡件304a相配合的环形形状,以使阻挡件304a可以设置在其上,但本发明不限于此。在俯视图中,第二结合件301b可以具有能够使阻挡件304a设置在其上的任意形状。
根据本发明的示例性实施例,阻挡件304a可以设置成一体,即,阻挡件304a可以具有预置成一体的环形结构,但本发明并不限于此。阻挡件304a可以包括多个阻挡构件以组成环形结构,例如,阻挡件304a可以包括两个或两个以上的多个阻挡构件,所述多个阻挡构件可以彼此首尾连接以形成诸如环形或其它形状的阻挡件304a,以提供容纳包封构件303的空间。
根据本发明的示例性实施例,阻挡件的截面可以具有任意的形状。如图3A中示出的根据本发明的一个示例性实施例的封装件中的阻挡件304a具有类似长方形的截面,然而在图3C中示出的根据本发明的另一示例性实施例的封装件中,阻挡件304b具有类似子弹形状的截面,但本发明不限于此。
根据本发明的示例性实施例,阻挡件304a可以设置成环形预制挡坝,以使它能够容纳将要填充在其中的诸如封装胶水的包封构件303。因此,为了精确控制根据本发明的示例性实施例的封装件的尺寸,可以根据需要来控制诸如预置挡坝的阻挡件304a的高度,但本发明不限于此。
根据本发明的示例性实施例,构成阻挡件304a的材料可以包括陶瓷、塑料、金属或焊料。
根据本发明的示例性实施例,诸如封装胶水的包封构件303可以设置在阻挡件304a中,从而包封芯片302、第一结合件301a和引线W。
图4是示出根据本发明的另一示例性实施例的封装件的示意性剖视图。以下,将参照图4来描述根据本发明的另一示例性实施例的封装件。图4中示出的封装件与图3A和图3C中示出的封装件除了阻挡件以及阻挡件与第二结合件之间的连接件以外具有相同或相似的结构,因此,下面将结合图4来主要描述与图3A和图3C中示出的封装件的不同。贯穿整个说明书,同样的附图标记始终指示为同样的元件。
参照图4,根据本发明的示例性实施例的封装件包括:基底400,具有第一表面和背对第一表面的第二表面,基底400中设置有多个焊盘(未示出);第一结合件401a和第二结合件401b,设置在基底400的第二表面上,第二结合件401b位于第一结合件401a的周围;芯片402,设置在第一结合件401a上,并通过引线W与设置在基底400中的焊盘(未示出)电连接;阻挡件404,设置在第二结合件401b上;包封构件403,设置在阻挡件404的内侧,以包封芯片402、第一结合件401a和引线W。
根据本发明的示例性实施例,诸如挡坝的阻挡件404的材料可以包括例如焊锡的焊料。在这种情况下,为了使阻挡件404固定在第二结合件401b上,金属图案层405可以设置在阻挡件404与第二结合件401b之间,以将阻挡件404与第二结合件402b结合,但本发明不限于此。
根据本发明的示例性实施例,金属图案层405可以包括铜,但不限于此。也就是说,金属图案层可以包括能够将第二结合件401b和阻挡件404结合的任何一种金属和/或它们的合金。根据本发明的示例性实施例,当省略第二结合件401b时,金属图案层405可以通过由诸如结合剂构成的粘结层A设置在基底400上,在这种情况下,由诸如结合剂构成的粘结层A可以等同于第二结合件401b。
根据本发明的示例性实施例,阻挡件404可以设置为一体,即,通过焊料和回流工艺形成的阻挡件404可以连续地形成为诸如环形的一体形状,但本发明不限于此。也就是说,如图3A和图3C中分别示出的诸如预置挡坝的阻挡件304a和304b与图4中示出的诸如焊锡筑坝的阻挡件404可以组合在一起来形成阻挡件。具体地讲,例如,诸如预置挡坝的阻挡件304a可以设置为半圆环,并且诸如筑坝焊锡的阻挡件404可以设置为半圆环,使得阻挡件304a和阻挡件404可以组合在一起,从而获得容纳包封构件403四周封闭的空间。然而,根据工艺的需要,阻挡件304a与404的周长比例可以根据实际情况来确定。此外,根据阻挡件304a与404的具体尺寸,可以对第二结合件301b和401b以及金属图案层405的具体尺寸做适当调节。
根据本发明的示例性实施例,第二结合件401b可以具有面对基底400的第一表面和背对第一表面的第二表面。当金属图案层405设置在第二结合件401b和阻挡件404之间时,第二结合件401b的第二表面可以具有平坦的形状,以使金属图案层405设置在平坦的第二表面上,但本发明不限于此。第二结合件401b的第二表面可以具有凹凸的形状,更具体地,第二表面可以具有凹坑,该凹坑可以容纳或部分容纳金属图案层405。此外,当阻挡件包括如图3中所示的诸如预置挡坝的阻挡件304a和/或304b以及如图4中所示的诸如焊锡筑坝的阻挡件404时,第二结合件401b与阻挡件304a和/或304b对应的部分可以具有不同的结构,即,与诸如预置挡坝的阻挡件304a和/或304b对应的第二结合件401b的第二表面可以具有平坦的表面,且与诸如焊锡筑坝的阻挡件404对应的第二结合件401b的第二表面可以具有可以容纳金属图案层405的具有凹坑的表面,但本发明不限于此。
以上,结合图3A至图3C以及图4详细地描述了根据本发明的示例性实施例的封装件的具体示例,通过在第二结合件301b和401b上设置阻挡件304a、304b和404提供了容纳包封构件303和403的空间,从而在保证封装件的尺寸精度的前提下有效地改善了封装件的机械强度。此外,由于采用点胶的方法来包封,因此避免了采用模塑方法的包封过程中由于模塑料与基底的焊点部位结合力较弱而容易产生分层的现象的发生。
下面,将结合图5A至图5C以及图6A至图6C来描述根据本发明的示例性实施例的制造封装件的方法。贯穿整个说明书,同样的附图标记始终指示为同样的元件。
图5A至图5C是示出根据本发明的一个示例性实施例的制造封装件的方法的示意性剖视图。
首先,参照图5A,设置基底300,并且在基底300上设置芯片302。
具体地,可以利用诸如结合剂的粘结层将芯片302固定在设置在基底300上的第一结合件301a上,从而使芯片302固定在基底300上,但本发明并不限于此。可以省略第一结合件301a。更具体地,第一结合件301a可以为粘结层A,即,可以通过作为第一结合件301a的粘结层A直接将芯片302固定在基底300上。
其次,参照图5B,设置阻挡件304a。
具体地,可以通过诸如结合剂的粘结层A来将阻挡件304a固定在第一结合件301b上,从而使其固定在基底300上。在这种情况下,设置阻挡件304a的步骤可以包括在第二结合件301b上设置(例如,涂覆)结合剂以形成粘结层A;将阻挡件304a设置在粘结层A上,并进行固化处理,从而使第二结合件301b固定在基底300上。但本发明不限于此,可以省略第二结合件301b,即,可以将结合剂直接设置(例如,涂覆)在基底300上以形成粘结层A,然后将阻挡件设置在粘结层A上,并进行固化处理,从而使第二结合件301b通过粘结层A直接固定在基底300上。
根据本发明的示例性实施例,第二结合件301b具有面对基底的第一表面和背对基底300的第二表面。第二表面可以具有平坦的形状,然而,根据工艺需要,可以将第二表面设置为具有凹凸不平的结构,或者可以将第二表面设置为具有能够容纳或部分容纳金属图案层305的凹坑结构。
根据封装件的需要,可以将阻挡件304a设置为具有预定的形状,以将芯片302包围在其中。根据本发明的示例性实施例,可以将阻挡件304a设置为具有环形的形状。当将阻挡件304a设置为具有环形形状时,可以将芯片302设置在阻挡件304a的环形形状的中心,并且可以将第二结合件301b设置为具有与阻挡件304a相配合的形状。具体地,如图3B中所示,可以将阻挡件304A设置成环形形状,此时,可以将芯片302设置在环形形状的中心,并且可以将第二结合件301b设置成具有与阻挡件304a相配合的环形形状,以使阻挡件304A可以设置在其上,但本发明不限于此。可以将第二结合件301b设置为具有任何能够使阻挡件304a设置在其上的形状。
根据本发明的示例性实施例,阻挡件304a可以设置成一体,即,阻挡件304a可以具有预置成一体的环形结构,但本发明并不限于此。阻挡件304a可以包括多个阻挡构件以组成环形结构,例如,阻挡件304a可以包括两个或两个以上的多个阻挡构件,所述多个阻挡构件可以彼此首尾接触以形成容纳包封构件303的诸如环形或其它形状的阻挡件。
根据本发明的示例性实施例,可以使用陶瓷、塑料、金属和/或焊料等来构成阻挡件304a。
然后,参照图5C,通过引线W将芯片302和设置在基底300上的焊盘(未示出)电连接,并设置包封构件303以包封芯片302第一结合件301a和引线W。
根据本发明的示例性实施例,可以采用引线键合技术利用引线W将芯片302与设置在基底300上的焊盘(未示出)电连接,但本发明不限于此。
根据本发明的示例性实施例,可以使用诸如封装胶水等封装构件将芯片302、第一结合件301a和引线W包封,但本发明不限于此。
图6A至图6C是示出根据本发明的另一示例性实施例的制造封装件的示意性剖视图。
首先,参照图6A,设置基底400,在基底上设置芯片402和金属图案层405。
具体地,可以通过诸如结合剂等将芯片402固定在设置于基底400上的第一结合件401a上,从而使芯片402固定在基底400上,但本发明不限于此。可以省略第一结合件401a,即,可以使用诸如结合剂的粘结层A来替换第一结合件401a,在这种情况下,可以通过作为第一结合件401a的粘结层A直接将芯片402固定在基底300上。可以在设置于基底400上的第二结合件401b上设置金属图案层405。根据本发明的示例性实施例,可以采用现有技术来使金属图案层405附于第二结合件401b的表面。作为金属图案层405的材料可以包括诸如铜等的能够将焊料固定在第二结合件401b上的金属。
根据本发明的示例性实施例,第二结合件401b可以具有面对基底400的第一表面和背对第一表面的第二表面。当将金属图案层405设置在第二结合件401b和阻挡件404之间时,第二结合件401b的第二表面可以具有平坦的形状,以使金属图案层405设置在平坦的第二表面上,但本发明不限于此。第二结合件401b的第二表面可以具有凹凸的形状,更具体地,第二表面可以具有凹坑,该凹坑可以容纳或部分容纳金属图案层405。
其次,参照图6B,设置阻挡件404。
具体地,可以将诸如焊料等涂覆在具有金属图案层405的第二结合件401b上,以覆盖金属图案层405;然后对焊料执行回流,从而使焊料形成具有预定高度的诸如筑坝的阻挡件304B。根据本发明的示例性实施例,焊料可以为本领域所普遍使用的金属焊料或金属合金焊料等。
根据本发明的示例性实施例,可以在第二结合件401b上设置两部分阻挡件,即具有诸如预置挡坝结构的阻挡件和诸如焊锡筑坝结构的阻挡件,以使所述两部分阻挡件能够结合在一起,从而获得能够容纳包封构件403的空间。
根据本发明的示例性实施例,当阻挡件包括诸如预置挡坝的阻挡件(如图6B和图6C所示)和诸如焊锡筑坝的阻挡件(如图6B和图6C所示)时,可以根据以上描述的不同阻挡件的不同特征来来对应地设置第二结合件401b。例如,在第二结合件401b中,与图5B和图5C中的阻挡件对应的部分第二结合件401b可以设置为平坦的形状,与图6B和图6C中的阻挡件对应的另一部分第二结合件401b可以设置为具有容纳金属图案层405的凹槽。
根据本发明的示例性实施例,根据工艺需要,可以控制焊料的种类以及焊料的高度,使得在执行回流后获得预期高度的阻挡件404,从而能够精确控制封装件的尺寸。
然后,参照图6C,通过引线W将芯片402与焊盘(未示出)电连接,然后执行包封。
具体地,可以采用引线键合技术使用引线W将芯片402与设置在基底400上的焊盘(未示出)电连接,但本发明不限于此。然后采用诸如封装胶水等包封构件403填充到由阻挡件404构成的空间中,从而使包封构件403容纳在阻挡件404构成的空间中,并将芯片402、引线W和第一结合件401a包封。
因为根据本发明的示例性实施例的封装件采用点胶的方法来包封,从而避免了模塑封装容易分层的缺点。此外,采用环形预置坝或采用焊锡筑坝的方式在基底上设置阻挡件,使得封装件的尺寸易于精确控制,并且也提升了封装件的整体机械性能。
虽然参照本发明的示例性实施例具体示出并描述了本发明,但是本领域技术人员应该理解,在不脱离本发明的精神和范围的情况下,可做出形式上和细节上的各种改变。
Claims (10)
1.一种封装件,其特征在于,所述封装件包括:
基底,具有第一表面和背对第一表面的第二表面,基底中设置有多个焊盘;
第一结合件和第二结合件,设置在基底的第二表面上,第二结合件位于第一结合件的周围;
芯片,设置在第一结合件上,并通过引线电连接到所述多个焊盘;
阻挡件,设置在第二结合件上;
包封构件,设置在阻挡件的内侧,以包封芯片、第一结合件和引线。
2.如权利要求1所述的封装件,其特征在于,阻挡件为环形,芯片设置在第二结合件的环形中心。
3.如权利要求1所述的封装构件,其特征在于,阻挡件包括陶瓷、塑料和金属中的至少一种。
4.如权利要求1所述的封装件,其特征在于,阻挡件包括焊料。
5.如权利要求4所述的封装件,其特征在于,阻挡件与结合件之间设置有金属图案层。
6.一种制造封装件的方法,其特征在于,所述方法包括以下步骤:
设置基底,基底具有第一表面和背对第一表面的第二表面,基底中设置有多个焊盘;
在基底的第二表面上设置第一结合件和第二结合件,其中,第二结合件位于第一结合件的周围;
在第一结合件上设置芯片,并在第二结合件上设置阻挡件;
通过引线将芯片与焊盘电连接;
将包封构件设置在阻挡件的内侧,以包封芯片、第一结合件和引线。
7.如权利要求6所述的方法,其特征在于,将阻挡件的数量设置为一个并设置为具有环形结构,将芯片设置在阻挡件的环形结构的中心。
8.如权利要求6所述的方法,其特征在于,阻挡件包括陶瓷、塑料和金属中的至少一种。
9.如权利要求6所述的方法,其特征在于,阻挡件包括焊料。
10.如权利要求9所述的方法,其特征在于,设置阻挡层的步骤包括:
在第二结合件上设置金属图案层,然后在金属图案层上设置阻挡件以覆盖金属图案层。
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110275177A1 (en) * | 2008-09-29 | 2011-11-10 | Choong-Bin Yim | Semiconductor package having ink-jet type dam and method of manufacturing the same |
CN203521408U (zh) * | 2013-11-06 | 2014-04-02 | 广州硅能照明有限公司 | 基于镀银铝基板的led光源 |
CN103762200A (zh) * | 2013-12-31 | 2014-04-30 | 三星半导体(中国)研究开发有限公司 | 芯片封装件及其封装方法 |
US20140175502A1 (en) * | 2012-12-21 | 2014-06-26 | Lite-On Technology Corporation | Led package structure, dam structure thereof, and method of manufacturing led package thereof |
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US9368422B2 (en) * | 2012-12-20 | 2016-06-14 | Nvidia Corporation | Absorbing excess under-fill flow with a solder trench |
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US20140175502A1 (en) * | 2012-12-21 | 2014-06-26 | Lite-On Technology Corporation | Led package structure, dam structure thereof, and method of manufacturing led package thereof |
CN203521408U (zh) * | 2013-11-06 | 2014-04-02 | 广州硅能照明有限公司 | 基于镀银铝基板的led光源 |
CN103762200A (zh) * | 2013-12-31 | 2014-04-30 | 三星半导体(中国)研究开发有限公司 | 芯片封装件及其封装方法 |
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