CN104900688A - 定向磊晶的异质接面双极性晶体管结构 - Google Patents

定向磊晶的异质接面双极性晶体管结构 Download PDF

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CN104900688A
CN104900688A CN201410469535.3A CN201410469535A CN104900688A CN 104900688 A CN104900688 A CN 104900688A CN 201410469535 A CN201410469535 A CN 201410469535A CN 104900688 A CN104900688 A CN 104900688A
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金宇中
黄朝兴
曾敏男
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Visual Photonics Epitaxy Co Ltd
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Abstract

一种定向磊晶的异质接面双极性晶体管结构，是直接或间接成长在(100)朝向(111)B面倾斜的砷化镓基板上，包含在基板上由下而上依序堆栈的次集极层、集极层、基极层、射极层，射极盖层及欧姆接触层，其中射极层为N型能隙大于基极层的III-V族半导体。此外，还可进一步包含夹在集极层及基极层之间的穿隧集极层，是由磷化铟镓(InGaP)或砷磷化铟镓(InGaAsP)形成。本发明是在(100)朝向(111)B面倾斜的砷化镓基板上成长，倾斜的角度为0.6°～25°，皆能在一般制程范围内轻易达成，使铟与镓在111方向上达到很有序的排列，缩小基极-射极接面与基极-穿隧集极接面导电带的不连续，增进整体电气特性。

Description

定向磊晶的异质接面双极性晶体管结构
技术领域
本发明有关一种定向磊晶的异质接面双极性晶体管(HeterojunctionBipolar Transistor，HBT)结构，尤其是在GaAs的基板上依据特定的磊晶方向形成InGaP的穿隧集极层或/及射极层。
背景技术
异质接面双极性晶体管(HBT)是利用不同半导体材料构成射极及基极，并在射极及基极的接面处形成异质接面，其好处在于基极流向射极的电洞流因为较难跨越基极与射极之间的价电带(valance band)位障(ΔEV)，使得射极注入效率(Emitter Injection Efficiency)提高，进而在较高基极参杂下提高电流增益。当HBT作为功率放大器用于手持式装置时，功率放大器的效率显得格外重要，在HBT组件上影响效率的参数主要为膝电压与导通电压，因此降低膝电压与导通电压是一门重要的课题。
现有技术是在(100)面或(100)朝(110)面倾斜2°的GaAs基板上，成长异质接面双极性晶体管，基极最常用的半导体材料砷化镓(GaAs)而射极及穿隧集极最常用的半导体材料为磷化铟镓(InGaP)。由于磷化铟镓成长于(100)或(100)朝(110)倾斜2°的GaAs基板上无法使铟与镓在<111>方向上达到很有序的排列，造成磷化铟镓(InGaP)的电子亲和力(electron affinity)始终小于或远远小于砷化镓(GaAs)的电子亲和力，因此形成基极-射极接面与基极-穿隧集极接面导电带的不连续，造成HBT有较高的导通电压，也同时造成集极电流阻挡效应，增加膝电压(knee voltage)，不利于HBT PA的效率(PAE)。
因此，需要一种成长于不同倾斜面的异质接面双极性晶体管结构，当磷化铟镓或砷磷化铟镓用于射极层或/及穿隧集极层时具有较大的电子亲和力或较小的能隙进而降低基极-射极接面或/及基极-穿隧集极接面导电带的不连续，以降低异质接面双极性晶体管的导通电压与补偏电压(offset voltage)，也同时改善集极电流阻挡效应，降低膝电压(knee voltage)，增加HBT PA的效率(PAE)，增进整体电气特性。
发明内容
本发明的主要目的在提供一种定向磊晶的异质接面双极性晶体管结构，尤其是一种成长于(100)朝向(111)B面GaAs基板上的异质接面双极性晶体管结构，主要是在(100)朝向(111)B(即(1-11)或(11-1))面的GaAs基板上直接或间接成长III-V族半导体所构成的异质接面双极性晶体管(HBT)，包括依序堆栈的次集极层(Sub-collector)、集极层(Collector)、穿隧集极层(TunnelingCollector)、基极层(Base)、射极层(Emitter)，射极盖层(Emitter Cap)以及欧姆接触层。
具体而言，穿隧集极层为磷化铟镓或砷磷化铟镓，射极层为N型能隙大于基极层的III-V族半导体。由于磊晶是在(100)朝向(111)B的基板上进行，因而磷化铟镓(InGaP)或砷磷化铟镓(InGaAsP)中的铟与镓在<111>方向上有序成长(ordering effect)，使得磷化铟镓或砷磷化铟镓用于射极层或/及穿隧集极层具有较大的电子亲和力(electron affinity)或较小的能隙，进而降低基极-射极接面或/及基极-穿隧集极接面导电带(conduction band)的不连续，可降低异质接面双极性晶体管的导通电压(turn-on voltage)与补偏电压(offset voltage，VOS)，也同时能改善集极电流阻挡效应(current blocking effect)，降低膝电压(knee voltage，VKEE)，增加HBT功率放大器(PA)的效率(PAE)，增进整体电气特性。
附图说明
图1为本发明第一实施例定向磊晶的异质接面双极性晶体管结构的示意图。
图2为本发明第二实施例定向磊晶的异质接面双极性晶体管结构的示意图。
图3为本发明第三实施例定向磊晶的异质接面双极性晶体管结构的示意图。
图4为本发明第四实施例定向磊晶的异质接面双极性晶体管结构的示意图。
图5(a)为本发明中的异质接面双极性晶体管能带示意图。
图5(b)为现有技术中异质接面双极性晶体管的能带示意图。
图6(a)为本发明与现有技术的异质接面双极性晶体管的I-V电气特性图。
图6(b)为本发明与现有技术的异质接面双极性晶体管的Ic-Vce电气特性图。
其中，附图标记说明如下：
10   基板
15   中间复合层
20   次集极层
30   集极层
35   穿隧集极层
40   基极层
50   射极层
60   射极盖层
70   欧姆接触层
具体实施方式
以下配合附图及附图标记对本发明的实施方式做更详细的说明，使熟习本领域的技术人员在研读本说明书后能据以实施。
参考图1，本发明第一实施例定向磊晶的异质接面双极性晶体管(HBT)结构的示意图。如图1所示，本发明的定向磊晶的异质接面双极性晶体管结构包括在基板10上由下而上依序堆栈的次集极层20、集极层30、基极层40、射极层50、射极盖层(Emitter Cap)60以及欧姆接触层70，其中次集极层20是由N型III-V族半导体形成，并堆栈在基板10上，尤其是，基板10是由砷化镓(GaAs)形成，且是由(100)朝向(111)B面方向倾斜，而倾斜的角度为0.6°～25°。此外，集极层30是堆栈在次集极层20上，并由N型III-V族半导体形成；基极层40是堆栈在集极层30上，并由P型III-V族半导体形成；射极层50是堆栈在基极层40上，并由N型InGaP或InGaAsP形成；射极盖层60是堆栈在射极层50上，并由N型III-V族半导体形成，而欧姆接触层70是堆栈在射极盖层60上，并由N型III-V族半导体形成。
具体而言，集极层30可为N型砷化镓(GaAs)、砷化铝镓(AlGaAs)、砷化铟镓(InGaAs)、磷化铟镓(InGaP)及砷磷化铟镓(InGaAsP)的至少其中之一形成，基极层40是由P型GaAs、砷化铟镓(InGaAs)、氮砷化铟镓(InGaAsN)及砷锑化镓(GaAsSb)的至少其中之一形成，射极盖层60可为N型GaAs、InGaP、InGaAsP及AlGaAs的至少其中之一形成，而欧姆接触层70可为N型GaAs及InGaAs的至少其中之一形成。
由于基板10是由(100)朝向(111)B面方向倾斜，因此可改善上述磊晶层的晶格结构，形成更加规则的晶格排列，减少晶格缺陷，并降低导电带(Conduction Band)及提高价电带(Valence Band)，进而缩小能隙(Band Gap)。
此外，可进一步包括至少一薄层(图中未显示)，并位于射极层50及基极层40之间，且可由III-V族半导体形成，尤其是，薄层的导电带等于及/或低于射极层50的导电带，且薄层的总厚度是介于1埃(1埃＝1×10-10m)～1000埃之间。更加具体而言，薄层可由AlGaAs、InGaP、InGaAsP、GaAs、GaAsP、InGaAs、GaAsSb及InGaAsN的至少其中之一形成。
进一步参考图2，本发明第二实施例定向磊晶的异质接面双极性晶体管结构的示意图，其中第二实施例的定向磊晶的异质接面双极性晶体管结构包括在基板10上由下而上依序堆栈的次集极层20、集极层30、穿隧集极层35、基极层40、射极层50、射极盖层(Emitter Cap)60以及欧姆接触层70，其中次集极层20是由N型III-V族半导体形成，并堆栈在基板10上，尤其是，基板10是由砷化镓(GaAs)形成，且是由(100)朝向(111)B面方向倾斜，而倾斜的角度为0.6°～25°。
要注意的是，图2的第二实施例是类似于图1的第一实施例，其主要的差异点在于，第二实施例额外包含穿隧集极层35，且设置于集极层30及基极层40之间，而且穿隧集极层35由InGaP或InGaAsP形成，此外，可进一步包括至少一薄层(图中未显示)，并位于穿隧集极层35及基极层40之间，且可由III-V族半导体形成，尤其是，薄层的导电带等于及/或低于穿隧集极层35的导电带，且薄层的总厚度是介于1埃～1000埃之间。更加具体而言，薄层可由AlGaAs、InGaP、InGaAsP、GaAs、GaAsP、InGaAs、GaAsSb及InGaAsN的至少其中之一形成。同时，堆栈在基极层40上的射极层50可由N型能隙大于基极层40的III-V族半导体形成。第二实施例的其余组件是相同于第一实施例，在此不再赘述。
请参考图3，本发明第三实施例定向磊晶的异质接面双极性晶体管结构的示意图。如图3所示，第三实施例的定向磊晶的异质接面双极性晶体管结构包括在基板10上由下而上依序堆栈的中间复合层15、次集极层20、集极层30、基极层40、射极层50、射极盖层(Emitter Cap)60以及欧姆接触层70，而中间复合层15是由半导体材料形成，并堆栈在基板10上，尤其是，基板10是由砷化镓(GaAs)形成，且是由(100)朝向(111)B面方向倾斜，而倾斜的角度为0.6°～25°。
要注意的是，图3的第三实施例是类似于图1的第一实施例，其主要的差异点在于，第三实施例额外包含中间复合层15，且设置于基板10及次集极层20之间，而第三实施例的其余组件是相同于第一实施例，在此不再赘述。
具体而言，中间复合层15可包括至少一缓冲层(图中未显示)，且缓冲层是由III-V族半导体形成。或者，中间复合层15可包括一场效晶体管(Fieldeffect transistor)。
此外，中间复合层15也可包括一假性高电子迁移率晶体管(pHEMT)，且假性高电子迁移率晶体管包含在基板10上由下到上依序堆栈的至少一缓冲层、第一掺杂层、第一间隔层、通道层、第二间隔层、第二掺杂层、萧特基层、蚀刻终止层以及用于欧姆接触的顶盖层(图中未显示)。尤其是，缓冲层是由III-V族半导体形成，第一掺杂层及该第二掺杂层为掺杂硅的砷化镓、掺杂硅的砷化铝镓、掺杂硅的磷化铟铝镓、掺杂硅的磷化铟镓以及掺杂硅的磷砷化铟镓的至少其中之一所形成，该第一间隔层及该第二间隔层由砷化镓、砷化铝镓、磷化铟铝镓、磷化铟镓以及磷砷化铟镓的至少其中之一所形成，该通道层是由砷化镓、砷化铟镓、砷化铝镓、磷化铟铝镓、磷化铟镓以及磷砷化铟镓的至少其中之一所形成，该萧特基层是由砷化镓、砷化铝镓、磷化铟铝镓、磷化铟镓以及磷砷化铟镓的至少其中之一所形成，该蚀刻终止层是由砷化镓、砷化铝镓、磷化铟铝镓、磷砷化铟镓、磷化铟镓以及砷化铝的至少其中之一所形成，而顶盖层是由N型III-V族半导体形成。
请参考图4，本发明第四实施例定向磊晶的异质接面双极性晶体管结构的示意图。如图4所示，第四实施例的定向磊晶的异质接面双极性晶体管结构包括在基板10上由下而上依序堆栈的中间复合层15、次集极层20、集极层30、穿隧集极层35、基极层40、射极层50、射极盖层(Emitter Cap)60以及欧姆接触层70，而如同图3的第三实施例，中间复合层15是由半导体材料形成，并堆栈在基板10上，尤其是，基板10是由砷化镓(GaAs)形成，且是由(100)朝向(111)B面方向倾斜，而倾斜的角度为0.6°～25°。
要注意的是，图4的第四实施例是类似于图2的第二实施例，其主要的差异点在于，第四实施例额外包含如第三实施例所示的中间复合层15，且设置于基板10及次集极层20之间，此外，穿隧集极层35是堆栈在集极层30上，并由InGaP或InGaAsP形成，而射极层50是堆栈在基极层40上，并由N型能隙大于基极层40的III-V族半导体形成。第四实施例的其余组件是相同于第二实施例，在此不再赘述。
此外，如同上述的第一实施例，本发明的第二实施例、第三实施例及第四实施例的HBT也可进一步包括至少一薄层(图中未显示)，并位于射极层50及基极层40之间，且可由III-V族半导体形成，尤其是，薄层的导电带等于及/或低于射极层50的导电带，且薄层的总厚度是介于1埃～1000埃之间。更加具体而言，薄层可由AlGaAs、InGaP、InGaAsP、GaAs、GaAsP、InGaAs、GaAsSb及InGaAsN的至少其中之一形成。
参考图5(a)，显示InGaP作为射极层50以及穿隧集极层35成长于(100)朝向(111)B面倾斜的砷化镓基板10上的能带示意图。由于InGaP成长于此倾斜方向的砷化镓基板10，因而造成铟与镓在<111>方向上达到很有序的排列(相对于InGaP或InGaAsP成长于(100)朝向(110)面倾斜的砷化镓基板10而言)，可减少甚至消除其与GaAs基极层40的导电带的不连续，降低异质接面双极性晶体管的导通电压与改善甚至消除集极电流阻挡效应，降低膝电压(knee voltage)。此外，图5(b)则显示现有技术中以InGaP作为射极层以及穿隧集极层的异质接面双极性晶体管是成长于(100)朝向(110)面倾斜的砷化镓基板上的能带示意图，其中可由能带图看出，在基极-射极接面与基极-穿隧集极接面有明显的导电带的不连续，而此导电带的不连续(ΔEC)会增加导通电压与集极电流阻挡效应，使得膝电压上升，不利于电气性能。因此，本发明确实具有较佳的电气操作性能。
参考图6(a)，本发明的HBT基极-射极接面I-V电气特性图，其中虚线表示现有技术中成长在(100)朝向(110)面倾斜2°，而实线表示本发明成长在(100)朝向(111)B面倾斜6°下形成时的I-V电气特性。从图6(a)可看出，本发明可降低导通电压。再进一步参考图6(b)，其中显示分别为现有技术成长在(100)朝向(110)面倾斜2°及本发明成长在(100)朝向(111)B面倾斜6°下形成时的HBT的Ic-Vce电气特性，同时显示现有技术中不含穿隧集极层的单异质接面双极性晶体管SHBT的Ic-Vce电气特性。显而易见的是，与现有技术比较，本发明不只可降低补偏电压(Offset Voltage)，还可同时降低膝电压，其中补偏电压是指集极电流Ic为零时的集射极电压VCE，而膝电压是指饱合区与作用区交界的电压。因而，本发明能确实解决现有技术的问题，改善整体电气操作性能。
以上所述内容仅为用以解释本发明的较佳实施例，并非企图据以对本发明做任何形式上的限制，因此，凡有在相同的发明精神下所作有关本发明的任何修饰或变更，皆仍应包括在本发明意图保护的范畴。

Claims (22)

1.一种定向磊晶的异质接面双极性晶体管结构，其特征在于，包括：
一次集极层，是由N型III-V族半导体形成，并堆栈在一基板上，其中该基板为砷化镓，且是由(100)朝向(111)B面方向倾斜，而倾斜的角度为0.6°～25°；
一集极层，是堆栈在该次集极层上，并由N型III-V族半导体形成；
一基极层，是堆栈在该集极层上，并由P型III-V族半导体形成；
一射极层，是堆栈在该基极层上，并由N型InGaP或InGaAsP形成；
一射极盖层，是堆栈在该射极层上，并由N型III-V族半导体形成；以及
一欧姆接触层，是堆栈在该射极盖层上，并由N型III-V族半导体形成。
2.依据权利要求1所述的异质接面双极性晶体管结构，其特征在于，该集极层为N型GaAs、AlGaAs、InGaAs、InGaP及InGaAsP的至少其中之一形成，该基极层是由P型GaAs、InGaAs、InGaAsN及GaAsSb的至少其中之一形成，该射极盖层为N型GaAs、InGaP、InGaAsP及AlGaAs的至少其中之一形成，该欧姆接触层为N型GaAs及InGaAs的至少其中之一形成。
3.依据权利要求1所述的异质接面双极性晶体管结构，其特征在于，进一步包括至少一薄层，且该薄层的导电带等于及/或低于该射极层的导电带，并位于该射极层及该基极层之间，其中该薄层由III-V族半导体形成，且该薄层的总厚度介于1埃～1000埃之间。
4.依据权利要求3所述的异质接面双极性晶体管结构，其特征在于，该薄层由AlGaAs、InGaP、InGaAsP、GaAs、GaAsP、InGaAs、GaAsSb及InGaAsN的至少其中之一形成。
5.一种定向磊晶的异质接面双极性晶体管结构，其特征在于，包括：
一次集极层，是由N型III-V族半导体形成，并堆栈在一基板上，其中该基板为砷化镓，且是由(100)朝向(111)B面方向倾斜，而倾斜的角度为0.6°～25°；
一集极层，是堆栈在该次集极层上，并由N型III-V族半导体形成；
一穿隧集极层，是堆栈在该集极层上，并由InGaP或InGaAsP形成；
一基极层，是堆栈在该穿隧集极层上，并由P型III-V族半导体形成；
一射极层，是堆栈在该基极层上，并由N型能隙大于基极层的III-V族半导体形成；
一射极盖层，是堆栈在该射极层上，并由N型III-V族半导体形成；以及
一欧姆接触层，是堆栈在该射极盖层上，并由N型III-V族半导体形成。
6.依据权利要求5所述的异质接面双极性晶体管结构，其特征在于，该集极层为N型GaAs、AlGaAs、InGaAs、InGaP及InGaAsP的至少其中之一形成，该基极层是由P型GaAs、InGaAs、InGaAsN及GaAsSb的至少其中之一形成，该射极层为N型InGaP、InGaAsP及AlGaAs的至少其中之一形成，且该穿隧集极层的厚度为1nm～30nm，而该射极盖层为N型GaAs、InGaP、InGaAsP及AlGaAs的至少其中之一形成，该欧姆接触层为N型GaAs及InGaAs的至少其中之一形成。
7.依据权利要求5所述的异质接面双极性晶体管结构，其特征在于，进一步包括至少一薄层，位于该穿隧集极层及该基极层之间，由III-V族半导体形成，其导电带等于及/或低于该穿隧集极层的导电带，且该薄层的总厚度介于1埃～1000埃之间，及/或包括至少一薄层，位于该射极层与该基极层之间，由III-V族半导体形成，其导电带等于及/或低于该射极层的导电带，且该薄层的总厚度介于1埃～1000埃之间。
8.依据权利要求7所述的异质接面双极性晶体管结构，其特征在于，该薄层由AlGaAs、InGaP、InGaAsP、GaAs、GaAsP、InGaAs、GaAsSb及InGaAsN的至少其中之一形成。
9.一种定向磊晶的异质接面双极性晶体管结构，其特征在于，包括：
一中间复合层，是由半导体材料形成，并堆栈在一基板上，其中该基板为砷化镓，且是由(100)朝向(111)B面方向倾斜，而倾斜的角度为0.6°～25°；
一次集极层，是由N型III-V族半导体形成，并堆栈在该中间复合层上；
一集极层，是堆栈在该次集极层上，并由N型III-V族半导体形成；
一基极层，是堆栈在该集极层上，并由P型III-V族半导体形成；
一射极层，是堆栈在该基极层上，并由N型InGaP或InGaAsP形成；
一射极盖层，是堆栈在该射极层上，并由N型III-V族半导体形成；以及
一欧姆接触层，是堆栈在该射极盖层上，并由N型III-V族半导体形成。
10.依据权利要求9所述的异质接面双极性晶体管结构，其特征在于，该中间复合层包括至少一缓冲层，且该缓冲层是由III-V族半导体形成。
11.依据权利要求9所述的异质接面双极性晶体管结构，其特征在于，该中间复合层包括一场效晶体管。
12.依据权利要求9所述的异质接面双极性晶体管结构，其特征在于，该中间复合层包括一假性高电子迁移率晶体管，且该假性高电子迁移率晶体管包含在该基板上由下到上依序堆栈的至少一缓冲层、一第一掺杂层、一第一间隔层、一通道层、一第二间隔层、一第二掺杂层、一萧特基层、一蚀刻终止层，以及一用于欧姆接触的顶盖层，且该缓冲层是由III-V族半导体形成，第一掺杂层及该第二掺杂层为掺杂硅的砷化镓、掺杂硅的砷化铝镓、掺杂硅的磷化铟铝镓、掺杂硅的磷化铟镓以及掺杂硅的磷砷化铟镓的至少其中之一所形成，该第一间隔层及该第二间隔层由砷化镓、砷化铝镓、磷化铟铝镓、磷化铟镓以及磷砷化铟镓的至少其中之一所形成，该通道层是由砷化镓、砷化铟镓、砷化铝镓、磷化铟铝镓、磷化铟镓以及磷砷化铟镓的至少其中之一所形成，该萧特基层是由砷化镓、砷化铝镓、磷化铟铝镓、磷化铟镓以及磷砷化铟镓的至少其中之一所形成，该蚀刻终止层是由砷化镓、砷化铝镓、磷化铟铝镓、磷砷化铟镓、磷化铟镓以及砷化铝的至少其中之一所形成，而顶盖层是由N型III-V族半导体形成。
13.依据权利要求9所述的异质接面双极性晶体管结构，其特征在于，该集极层为N型GaAs、AlGaAs、InGaAs、InGaP及InGaAsP的至少其中之一形成，该基极层是由P型GaAs、InGaAs、InGaAsN及GaAsSb的至少其中之一形成，而该射极盖层为N型GaAs、InGaP、InGaAsP及AlGaAs的至少其中之一形成，该欧姆接触层为N型GaAs及InGaAs的至少其中之一形成。
14.依据权利要求9所述的异质接面双极性晶体管结构，其特征在于，进一步包括至少一薄层，且该薄层的导电带等于及/或低于该射极层的导电带，并位于该射极层及该基极层之间，其中该薄层由III-V族半导体形成，且该薄层的总厚度介于1埃～1000埃之间。
15.依据权利要求14所述的异质接面双极性晶体管结构，其特征在于，该薄层由AlGaAs、InGaP、InGaAsP、GaAs、GaAsP、InGaAs、GaAsSb及InGaAsN的至少其中之一形成。
16.一种定向磊晶的异质接面双极性晶体管结构，其特征在于，包括：
一中间复合层，是由半导体材料形成，并堆栈在一基板上，其中该基板为砷化镓，且是由(100)朝向(111)B面方向倾斜，而倾斜的角度为0.6°～25°；
一次集极层，是由N型III-V族半导体形成，并堆栈在该中间复合层上；
一集极层，是堆栈在该次集极层上，并由N型III-V族半导体形成；
一穿隧集极层，是堆栈在该集极层上，并由InGaP或InGaAsP形成；
一基极层，是堆栈在该穿隧集极层上，并由P型III-V族半导体形成；
一射极层，是堆栈在该基极层上，并由N型能隙大于基极层的III-V族半导体形成；
一射极盖层，是堆栈在该射极层上，并由N型III-V族半导体形成；以及
一欧姆接触层，是堆栈在该射极盖层上，并由N型III-V族半导体形成。
17.依据权利要求16所述的异质接面双极性晶体管结构，其特征在于，该中间复合层包括至少一缓冲层，且该缓冲层是由III-V族半导体形成。
18.依据权利要求16所述的异质接面双极性晶体管结构，其特征在于，该中间复合层包括一场效晶体管。
19.依据权利要求16所述的异质接面双极性晶体管结构，其特征在于，该中间复合层包括一假性高电子迁移率晶体管，且该假性高电子迁移率晶体管包含在该基板上且由下到上依序堆栈的至少一缓冲层、一第一掺杂层、一第一间隔层、一通道层、一第二间隔层、一第二掺杂层、一萧特基层、一蚀刻终止层，以及一用于欧姆接触的顶盖层，且该缓冲层是由III-V族半导体形成，该第一掺杂层及该第二掺杂层为掺杂硅的砷化镓、掺杂硅的砷化铝镓、掺杂硅的磷化铟铝镓、掺杂硅的磷化铟镓以及掺杂硅的磷砷化铟镓的至少其中之一所形成，该第一间隔层及该第二间隔层由砷化镓、砷化铝镓、磷化铟铝镓、磷化铟镓以及磷砷化铟镓的至少其中之一所形成，该通道层是由砷化镓、砷化铟镓、砷化铝镓、磷化铟铝镓、磷化铟镓以及磷砷化铟镓的至少其中之一所形成，该萧特基层是由砷化镓、砷化铝镓、磷化铟铝镓、磷化铟镓以及磷砷化铟镓的至少其中之一所形成，该蚀刻终止层是由砷化镓、砷化铝镓、磷化铟铝镓、磷砷化铟镓、磷化铟镓以及砷化铝的至少其中之一所形成，而顶盖层是由N型III-V族半导体形成。
20.依据权利要求16所述的异质接面双极性晶体管结构，其特征在于，该集极层为N型GaAs、AlGaAs、InGaAs、InGaP及InGaAsP的至少其中之一形成，该基极层是由P型GaAs、InGaAs、InGaAsN及GaAsSb的至少其中之一形成，该射极层为N型InGaP、InGaAsP及AlGaAs的至少其中之一形成，而该射极盖层为N型GaAs、InGaP、InGaAsP及AlGaAs的至少其中之一形成，该欧姆接触层为N型GaAs及InGaAs的至少其中之一形成。
21.依据权利要求16所述的异质接面双极性晶体管结构，其特征在于，进一步包括至少一薄层，位于该穿隧集极层及该基极层之间，由III-V族半导体形成，其导电带等于及/或低于该穿隧集极层的导电带，且该薄层的总厚度介于1埃～1000埃之间，及/或包括至少一薄层，位于该射极层与该基极层之间，由III-V族半导体形成，其导电带等于及/或低于该射极层的导电带，且该薄层的总厚度介于1埃～1000埃之间。
22.依据权利要求21所述的异质接面双极性晶体管结构，其特征在于，该薄层由AlGaAs、InGaP、InGaAsP、GaAs、GaAsP、InGaAs、GaAsSb及InGaAsN的至少其中之一形成。
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