CN104900212A - Wiring structure of array substrate row driving circuit - Google Patents

Wiring structure of array substrate row driving circuit Download PDF

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Publication number
CN104900212A
CN104900212A CN201510377541.0A CN201510377541A CN104900212A CN 104900212 A CN104900212 A CN 104900212A CN 201510377541 A CN201510377541 A CN 201510377541A CN 104900212 A CN104900212 A CN 104900212A
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line
resistor
repair line
tested
repair
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王遵淯
郑美俊
游腾亮
杨哲豪
王嘉驹
黄怡平
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AUO Corp
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AU Optronics Corp
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Abstract

The invention provides a routing structure of a GOA circuit, which comprises: a scanning line to be tested is positioned in the GOA circuit; and a repair line located in the GOA circuit. The scanning line to be detected and the repair line are at least partially overlapped, and the repair line and the scanning line to be detected are electrically coupled in a welding mode, so that the multiplexing function of the repair line is realized. Compared with the prior art, the scanning circuit to be detected is electrically coupled to the repair line in a welding mode, so that the virtual grid routing and the repair line in the liquid crystal box are shared, the number of the virtual grid routing in the GOA circuit is reduced, and high-frequency signal interference caused by multiple circuits is reduced. In addition, the invention utilizes simple circuit design, and achieves the multiplexing function of the repair line through the switching matching between the first resistor and the second resistor additionally arranged on the test circuit board, thereby not only reducing the number of routing lines in the GOA circuit, but also freely changing and selecting the position of the scanning line to be tested, and further improving the flexibility of measurement.

Description

一种阵列基板行驱动电路的走线结构A routing structure of an array substrate row drive circuit

技术领域technical field

本发明涉及一种液晶显示装置的栅极驱动电路,尤其涉及一种阵列基板行驱动电路的走线结构。The invention relates to a gate drive circuit of a liquid crystal display device, in particular to a wiring structure of a row drive circuit of an array substrate.

背景技术Background technique

阵列基板行驱动(Gate Driver on Array,GOA)技术是直接将栅极驱动电路(Gate Driver ICs)制作在阵列基板(Array Substrate)上,以代替由外接硅晶片制作的栅极驱动晶片的一种技术。通常来说,在薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display,TFT-LCD)运用了GOA技术的液晶面板叫GOA液晶。与传统的TFT-LCD相比,GOA液晶不仅可节省成本,由于省去了栅极方向的绑定工艺,从而对提升产能较为有利。Array substrate row drive (Gate Driver on Array, GOA) technology is to directly make the gate driver circuit (Gate Driver ICs) on the array substrate (Array Substrate) to replace the gate driver chip made of external silicon wafer. technology. Generally speaking, the LCD panel using GOA technology in Thin Film Transistor Liquid Crystal Display (TFT-LCD) is called GOA LCD. Compared with traditional TFT-LCDs, GOA liquid crystals can not only save costs, but also help increase production capacity because the bonding process in the direction of the gate is omitted.

在GOA电路的制造过程中,因GOA栅极出现短路或断路、源极出现短路或断路、液晶盒(cell)里面混入了灰尘等原因,往往使面板出现不良现象,诸如短接、断线、亮点、灰度不均或灭点等。现有技术中,GOA电路内部的走线通常包含修补线(rescue line)、阵列基板的共通电极线(arraycom)、阵列基板的共通电极反馈线(array com FB)、高频时钟信号线(HC)、虚拟栅极(dummy gate)等多条线路,而线路繁多容易造成高频讯号干扰,影响GOA电路的信号传输。During the manufacturing process of the GOA circuit, due to the short circuit or open circuit of the GOA gate, the short circuit or open circuit of the source, and the dust mixed in the liquid crystal box (cell), etc., the panel often has bad phenomena, such as short circuit, disconnection, Bright spots, uneven gray scale or vanishing points, etc. In the prior art, the wiring inside the GOA circuit usually includes a repair line (rescue line), a common electrode line (arraycom) of the array substrate, a common electrode feedback line (array com FB) of the array substrate, and a high-frequency clock signal line (HC ), dummy gate and other lines, and many lines are likely to cause high-frequency signal interference and affect the signal transmission of the GOA circuit.

有鉴于此,如何设计一种阵列基板行驱动电路的走线结构,以消除现有技术中的上述缺陷或不足,是业内相关技术人员亟待解决的一项课题。In view of this, how to design a routing structure of the row driving circuit of the array substrate to eliminate the above-mentioned defects or deficiencies in the prior art is an urgent task to be solved by relevant technical personnel in the industry.

发明内容Contents of the invention

针对现有技术中的GOA电路因走线繁多容易形成高频讯号干扰的缺陷,本发明提供了一种新颖的GOA电路的走线结构。Aiming at the defect that the GOA circuit in the prior art is prone to high-frequency signal interference due to numerous traces, the present invention provides a novel trace structure of the GOA circuit.

依据本发明的一个方面,提供了一种GOA电路的走线结构,包括:According to one aspect of the present invention, a wiring structure of a GOA circuit is provided, including:

一待测扫描线路,位于一GOA电路内;以及a scan line to be tested, located within a GOA circuit; and

一修补线,位于所述GOA电路内,其中,所述待测扫描线路与所述修补线至少部分重叠,藉由焊接(welding)方式电性耦接所述修补线与所述待测扫描线路,从而实现所述修补线的复用功能。A repair line, located in the GOA circuit, wherein the scan line to be tested overlaps with the repair line at least partially, and the repair line and the scan line to be tested are electrically coupled by welding , so as to realize the multiplexing function of the repair line.

在其中的一实施例,所述GOA电路位于液晶盒的内部,且所述液晶盒的外部设有一测试电路板,其包括:一第一电阻和一第二电阻,透过所述第一电阻和所述第二电阻的投切配合以实现所述修补线的复用功能。In one of the embodiments, the GOA circuit is located inside the liquid crystal cell, and a test circuit board is provided outside the liquid crystal cell, which includes: a first resistor and a second resistor, through which the first resistor Cooperating with the switching of the second resistor to realize the multiplexing function of the repair line.

在其中的一实施例,当所述修补线维持正常的修线功能时,所述第一电阻与所述修补线电性接通,所述第二电阻与所述修补线电性断开,且所述待测扫描线路与所述修补线电性断开。In one embodiment, when the repairing wire maintains a normal repairing function, the first resistor is electrically connected to the repairing wire, and the second resistor is electrically disconnected from the repairing wire, And the scan line to be tested is electrically disconnected from the repair line.

在其中的一实施例,当所述待测扫描线路需进行测量操作时,所述第二电阻与所述修补线电性接通,所述第一电阻与所述修补线电性断开,且所述待测扫描线路与所述修补线藉由焊接方式电性耦接。In one embodiment, when the scanning line to be tested needs to perform a measurement operation, the second resistor is electrically connected to the repairing wire, and the first resistor is electrically disconnected from the repairing wire, And the scanning line to be tested is electrically coupled with the repairing line by welding.

在其中的一实施例,位于焊接区域下方的所述修补线的一部分被切断。In one embodiment, a portion of the repair line below the welding area is severed.

在其中的一实施例,所述第一电阻为零欧姆电阻。In one embodiment, the first resistor is a zero-ohm resistor.

在其中的一实施例,所述第二电阻为零欧姆电阻。In one embodiment, the second resistor is a zero-ohm resistor.

采用本发明的GOA电路的走线结构,其包括一待测扫描线路和一修补线,并且待测扫描线路与修补线至少部分重叠,该走线结构藉由焊接方式将待测扫描线路电性耦接至修补线,从而使液晶盒内的虚拟栅极走线与修补线实现共享,进而减少GOA电路中的虚拟栅极走线的数目,降低因线路繁多所引起的高频讯号干扰。相比于现有技术,本发明利用简易电路设计,透过测试电路板增设的第一电阻和第二电阻之间的投切配合来达到修补线的复用功能,当修补线维持正常的修线功能时,第一电阻与修补线电性接通而第二电阻与修补线电性断开;而待测扫描线路需进行测量操作时,第二电阻与修补线电性接通而第一电阻与修补线电性断开,且待测扫描线路与修补线藉由焊接方式电性耦接,不仅减少了GOA电路内的走线数目,还可自由变更和选择待测扫描线路的位置,进而提升测量的灵活性。The routing structure of the GOA circuit of the present invention includes a scanning line to be tested and a repairing line, and the scanning line to be tested and the repairing line are at least partially overlapped, and the routing structure is electrically connected to the scanning line to be tested by welding. Coupling to the repair line, so that the virtual gate line in the liquid crystal cell and the repair line are shared, thereby reducing the number of virtual gate lines in the GOA circuit, and reducing the high-frequency signal interference caused by a large number of lines. Compared with the prior art, the present invention uses a simple circuit design to achieve the multiplexing function of the repair line through the switching cooperation between the first resistor and the second resistor added on the test circuit board. When the repair line maintains normal repair When the line function is used, the first resistor is electrically connected to the repairing wire and the second resistor is electrically disconnected from the repairing wire; when the scanning line to be tested needs to be measured, the second resistor is electrically connected to the repairing wire and the first resistor is electrically connected to the repairing wire. The resistor is electrically disconnected from the repair line, and the scanning line to be tested and the repair line are electrically coupled by welding, which not only reduces the number of traces in the GOA circuit, but also freely changes and selects the position of the scanning line to be tested. This increases the flexibility of measurement.

附图说明Description of drawings

读者在参照附图阅读了本发明的具体实施方式以后,将会更清楚地了解本发明的各个方面。其中,Readers will have a clearer understanding of various aspects of the present invention after reading the detailed description of the present invention with reference to the accompanying drawings. in,

图1示出现有技术中的一种GOA电路的驱动原理示意图;FIG. 1 shows a schematic diagram of a driving principle of a GOA circuit in the prior art;

图2示出在图1的GOA电路中,采用多个虚拟栅极来测量相应的扫描线路的波形的示意图;FIG. 2 shows a schematic diagram of using multiple dummy gates to measure waveforms of corresponding scanning lines in the GOA circuit of FIG. 1;

图3(a)示出依据本发明的一实施方式,可降低GOA电路中的线路数目的走线结构的示意图;Figure 3(a) shows a schematic diagram of a wiring structure that can reduce the number of lines in a GOA circuit according to an embodiment of the present invention;

图3(b)示出图3(a)的走线结构中,待测扫描线路与修补线至少部分重叠的状态示意图;FIG. 3(b) shows a schematic diagram of a state in which the scanning line to be tested and the repairing line at least partially overlap in the wiring structure of FIG. 3(a);

图4示出图3(a)的走线结构中,修补线作为正常修线功能时的第一电阻与第二电阻投切示意图;Fig. 4 shows a schematic diagram of switching between the first resistor and the second resistor when the repair line is used as a normal line repair function in the wiring structure of Fig. 3(a);

图5(a)示出图3(a)的走线结构中,修补线复用为虚拟栅极在GOA电路内的走线时的第一电阻与第二电阻投切示意图;以及Figure 5(a) shows a schematic diagram of switching between the first resistor and the second resistor when the repair line is multiplexed as a virtual gate in the GOA circuit in the wiring structure of Figure 3(a); and

图5(b)示出图5(a)的走线结构中,待测扫描线路与修补线藉由焊接方式进行电性耦接的状态示意图。FIG. 5( b ) is a schematic diagram showing a state in which the scanning line to be tested and the repairing line are electrically coupled by soldering in the wiring structure of FIG. 5( a ).

具体实施方式Detailed ways

为了使本申请所揭示的技术内容更加详尽与完备,可参照附图以及本发明的下述各种具体实施例,附图中相同的标记代表相同或相似的组件。然而,本领域的普通技术人员应当理解,下文中所提供的实施例并非用来限制本发明所涵盖的范围。此外,附图仅仅用于示意性地加以说明,并未依照其原尺寸进行绘制。In order to make the technical content disclosed in this application more detailed and complete, reference may be made to the drawings and the following various specific embodiments of the present invention, and the same symbols in the drawings represent the same or similar components. However, those skilled in the art should understand that the examples provided below are not intended to limit the scope of the present invention. In addition, the drawings are only for schematic illustration and are not drawn according to their original scale.

下面参照附图,对本发明各个方面的具体实施方式作进一步的详细描述。The specific implementation manners of various aspects of the present invention will be further described in detail below with reference to the accompanying drawings.

图1示出现有技术中的一种GOA电路的驱动原理示意图。参照图1,该GOA电路包括多级扫描线路Scan 1、Scan 2、…、Scan6,其中,高频时钟信号HC1输入至扫描线路Scan 1,高频时钟信号HC2输入至扫描线路Scan 2,高频时钟信号HC3输入至扫描线路Scan 3,高频时钟信号HC4输入至扫描线路Scan 4,之后,高频时钟信号HC1输入至扫描线路Scan 5,高频时钟信号HC2输入至扫描线路Scan 6。也就是说,高频时钟信号HC1同时输入至扫描线路Scan 1和Scan 5,而高频时钟信号HC2同时输入至扫描线路Scan 2和Scan 6。FIG. 1 shows a schematic diagram of a driving principle of a GOA circuit in the prior art. Referring to Figure 1, the GOA circuit includes multi-level scanning lines Scan 1, Scan 2,..., Scan6, wherein the high-frequency clock signal HC1 is input to the scanning line Scan 1, the high-frequency clock signal HC2 is input to the scanning line Scan 2, and the high-frequency clock signal HC2 is input to the scanning line Scan 2. The clock signal HC3 is input to the scanning line Scan 3, the high-frequency clock signal HC4 is input to the scanning line Scan 4, and then the high-frequency clock signal HC1 is input to the scanning line Scan 5, and the high-frequency clock signal HC2 is input to the scanning line Scan 6. That is to say, the high-frequency clock signal HC1 is input to the scanning lines Scan 1 and Scan 5 at the same time, and the high-frequency clock signal HC2 is input to the scanning lines Scan 2 and Scan 6 at the same time.

此外,前级扫描线路与后级扫描线路在控制时序上密切关联。具体而言,后级扫描线路Scan 2输出的控制信号turn off1用来关闭前级扫描线路Scan 1,后级扫描线路Scan 3输出的控制信号turn off2用来关闭前级扫描线路Scan 2。类似地,后级扫描线路Scan 4输出的控制信号turn off3用来关闭前级扫描线路Scan 3,后级扫描线路Scan 5输出的控制信号turn off4用来关闭前级扫描线路Scan 4。In addition, the scanning lines of the previous stage and the scanning lines of the subsequent stage are closely related in terms of control timing. Specifically, the control signal turn off1 output by the subsequent scan line Scan 2 is used to turn off the previous scan line Scan 1, and the control signal turn off2 output by the subsequent scan line Scan 3 is used to close the previous scan line Scan 2. Similarly, the control signal turn off3 output by the subsequent scan line Scan 4 is used to turn off the previous scan line Scan 3, and the control signal turn off4 output by the subsequent scan line Scan 5 is used to close the previous scan line Scan 4.

图2示出在图1的GOA电路中,采用多个虚拟栅极来测量相应的扫描线路的波形的示意图。FIG. 2 shows a schematic diagram of using multiple dummy gates to measure waveforms of corresponding scanning lines in the GOA circuit of FIG. 1 .

参照图2,数字标记100表示液晶盒(cell),102表示液晶盒100的GOA电路,200表示测试电路板(也可称为P板)。测试电路板200包括虚拟栅极202和虚拟栅极204,其中,虚拟栅极202电性耦接至GOA电路102中的对应的待测扫描线路从而测量其波形,虚拟栅极204电性耦接至GOA电路102中的对应的待测扫描线路从而测量其波形。Referring to FIG. 2, numeral 100 denotes a liquid crystal cell (cell), 102 denotes a GOA circuit of the liquid crystal cell 100, and 200 denotes a test circuit board (also called a P board). The test circuit board 200 includes a dummy gate 202 and a dummy gate 204, wherein the dummy gate 202 is electrically coupled to the corresponding scan line to be tested in the GOA circuit 102 to measure its waveform, and the dummy gate 204 is electrically coupled to to the corresponding scan line to be tested in the GOA circuit 102 to measure its waveform.

如前文所述,目前GOA电路内部通常包含多种类型的走线,诸如修补线(rescue line)、阵列基板的共通电极线(array com)、阵列基板的共通电极反馈线(array com FB)、高频时钟信号线(HC)、虚拟栅极(dummy gate)等多条线路,而线路繁多容易造成高频讯号干扰,影响GOA电路的信号传输。此外,虚拟栅极与待测扫描线路之间的线路连接一一对应,其测量方式比较死板,无法灵活测量不同扫描线路上的波形。As mentioned above, the current GOA circuit usually contains various types of wiring, such as the rescue line, the common electrode line of the array substrate (array com), the common electrode feedback line of the array substrate (array com FB), There are many lines such as high-frequency clock signal line (HC), dummy gate (dummy gate), and many lines are likely to cause high-frequency signal interference and affect the signal transmission of the GOA circuit. In addition, there is a one-to-one correspondence between the virtual gate and the line connection between the scanning lines to be tested, and the measurement method is relatively rigid, and it is impossible to flexibly measure waveforms on different scanning lines.

为了解决现有技术中的上述问题,本发明提供了一种新颖的GOA电路的走线结构。图3(a)示出依据本发明的一实施方式,可降低GOA电路中的线路数目的走线结构的示意图。图3(b)示出图3(a)的走线结构中,待测扫描线路与修补线至少部分重叠的状态示意图。In order to solve the above-mentioned problems in the prior art, the present invention provides a novel wiring structure of a GOA circuit. FIG. 3( a ) shows a schematic diagram of a routing structure that can reduce the number of lines in a GOA circuit according to an embodiment of the present invention. FIG. 3( b ) is a schematic diagram showing a state where the scanning line to be tested and the repairing line overlap at least partially in the wiring structure of FIG. 3( a ).

参照图3(a),在该实施方式中,本发明的走线结构包括一待测扫描线路104和一修补线106,均位于GOA电路内。需要说明的是,待测扫描线路104与修补线106至少部分重叠,如图3(b)所示。如此一来,本发明可藉由焊接(welding)方式将待测扫描线路104电性耦接至修补线106,使得GOA电路内的修补线106用作为虚拟栅极202在电路内的走线,进而实现修补线的复用与共享功能。Referring to FIG. 3( a ), in this embodiment, the wiring structure of the present invention includes a scan line 104 to be tested and a repair line 106 , both of which are located in the GOA circuit. It should be noted that the scanning line 104 to be tested overlaps with the repairing line 106 at least partially, as shown in FIG. 3( b ). In this way, the present invention can electrically couple the scanning line 104 to be tested to the repairing line 106 by welding, so that the repairing line 106 in the GOA circuit is used as the routing of the dummy gate 202 in the circuit, Then realize the multiplexing and sharing function of the repair line.

在一具体实施例,GOA电路位于液晶盒100的内部,且液晶盒100的外部设有一测试电路板200。测试电路板200包括一第一电阻R1和一第二电阻R2,本发明透过第一电阻R1和第二电阻R2的投切配合以实现修补线的复用功能。在此,投切配合主要是指第一电阻R1与修补线106电性耦接或断开,第二电阻R2与修补线106电性耦接或断开。In a specific embodiment, the GOA circuit is located inside the liquid crystal cell 100 , and a test circuit board 200 is provided outside the liquid crystal cell 100 . The test circuit board 200 includes a first resistor R1 and a second resistor R2. The present invention realizes the multiplexing function of the repair line through the switching cooperation of the first resistor R1 and the second resistor R2. Here, the switch fit mainly means that the first resistor R1 is electrically coupled or disconnected from the repair wire 106 , and the second resistor R2 is electrically coupled or disconnected from the repair wire 106 .

在一具体实施例,第一电阻R1为零欧姆电阻。或者,第二电阻R2为零欧姆电阻。这里,零欧姆电阻又称为跨接电阻器,是一种特殊用途的电阻,0欧姆电阻并非真正的阻值为零,它实际是电阻值很小的电阻。例如,当电路板设计中的两点不能用印刷电路连接时,往往在正面用跨线连接,而为了让自动贴片机和自动插件机正常工作,可使用零欧姆电阻代替跨线。从某种意义上来说,零欧姆电阻仅使用在电路板上为了调试方便或兼容设计等。In a specific embodiment, the first resistor R1 is a zero-ohm resistor. Alternatively, the second resistor R2 is a zero-ohm resistor. Here, the zero-ohm resistor is also called a jumper resistor, which is a special-purpose resistor. The zero-ohm resistor does not have a real resistance value of zero, but is actually a resistor with a very small resistance value. For example, when two points in the circuit board design cannot be connected by a printed circuit, they are often connected with a jumper on the front side, and in order for the automatic placement machine and automatic plug-in machine to work normally, a zero-ohm resistor can be used instead of the jumper. In a sense, zero-ohm resistors are only used on circuit boards for debugging convenience or compatible designs, etc.

图4示出图3(a)的走线结构中,修补线作为正常修线功能时的第一电阻与第二电阻投切示意图。FIG. 4 shows a schematic diagram of switching between the first resistor and the second resistor when the repair line serves as a normal line repair function in the wiring structure of FIG. 3( a ).

参照图4,在该实施例中,修补线106用作正常的修线功能。具体地,当修补线106维持正常的修线功能时,第一电阻R1与修补线106电性接通,第二电阻R2与修补线106电性断开。此时,待测扫描线路104与修补线106虽部分重叠,但并未施加焊接操作,因而待测扫描线路104与修补线106之间并未电性接通。Referring to FIG. 4 , in this embodiment, the repair wire 106 serves a normal wire repair function. Specifically, when the repairing wire 106 maintains a normal repairing function, the first resistor R1 is electrically connected to the repairing wire 106 , and the second resistor R2 is electrically disconnected from the repairing wire 106 . At this time, although the scan line 104 to be tested partially overlaps with the repair line 106 , no welding operation is applied, so the scan line 104 to be tested and the repair line 106 are not electrically connected.

图5(a)示出图3(a)的走线结构中,修补线复用为虚拟栅极在GOA电路内的走线时的第一电阻与第二电阻投切示意图。图5(b)示出图5(a)的走线结构中,待测扫描线路与修补线藉由焊接方式进行电性耦接的状态示意图。FIG. 5( a ) shows a schematic diagram of switching between the first resistor and the second resistor when the repair line is multiplexed as the routing of the dummy gate in the GOA circuit in the routing structure of FIG. 3( a ). FIG. 5( b ) is a schematic diagram showing a state in which the scanning line to be tested and the repairing line are electrically coupled by soldering in the wiring structure of FIG. 5( a ).

参照图5(a)和图5(b),在该实施例中,修补线106复用为虚拟栅极202在GOA电路内部的走线,以测量待测扫描线路104的波形。详细而言,当待测扫描线路104需进行测量操作时,第二电阻R2与修补线106电性接通,第一电阻R1与修补线106电性断开,且待测扫描线路104与修补线106藉由焊接方式电性耦接,如图5(b)所示。较佳地,在此情形下,还可将位于焊接区域下方的修补线104的一部分被切断。应当理解,GOA电路内的待测扫描线路104可根据实际测量需求而更换为不同的扫描线路,由于这些扫描线路与修补线104至少部分重叠,因此总是能够利用焊接操作来测量这些扫描线路中的任意一条扫描线路上的波形,进而提高了测量的灵活度。Referring to FIG. 5( a ) and FIG. 5( b ), in this embodiment, the repair line 106 is multiplexed as the routing of the dummy gate 202 inside the GOA circuit to measure the waveform of the scanning line 104 to be tested. In detail, when the scan line 104 to be tested needs to perform a measurement operation, the second resistor R2 is electrically connected to the repair line 106, the first resistor R1 is electrically disconnected from the repair line 106, and the scan line 104 to be tested is electrically connected to the repair line 106. The wires 106 are electrically coupled by welding, as shown in FIG. 5( b ). Preferably, in this case, a part of the repair line 104 located below the welding area can also be cut off. It should be understood that the scanning lines 104 to be tested in the GOA circuit can be replaced with different scanning lines according to actual measurement requirements. Since these scanning lines overlap with the repairing line 104 at least partially, it is always possible to measure the The waveform on any one of the scanning lines, thus improving the flexibility of measurement.

采用本发明的GOA电路的走线结构,其包括一待测扫描线路和一修补线,并且待测扫描线路与修补线至少部分重叠,该走线结构藉由焊接方式将待测扫描线路电性耦接至修补线,从而使液晶盒内的虚拟栅极走线与修补线实现共享,进而减少GOA电路中的虚拟栅极走线的数目,降低因线路繁多所引起的高频讯号干扰。相比于现有技术,本发明利用简易电路设计,透过测试电路板增设的第一电阻和第二电阻之间的投切配合来达到修补线的复用功能,当修补线维持正常的修线功能时,第一电阻与修补线电性接通而第二电阻与修补线电性断开;而待测扫描线路需进行测量操作时,第二电阻与修补线电性接通而第一电阻与修补线电性断开,且待测扫描线路与修补线藉由焊接方式电性耦接,不仅减少了GOA电路内的走线数目,还可自由变更和选择待测扫描线路的位置,进而提升测量的灵活性。The routing structure of the GOA circuit of the present invention includes a scanning line to be tested and a repairing line, and the scanning line to be tested and the repairing line are at least partially overlapped, and the routing structure is electrically connected to the scanning line to be tested by welding. Coupling to the repair line, so that the virtual gate line in the liquid crystal cell and the repair line are shared, thereby reducing the number of virtual gate lines in the GOA circuit, and reducing the high-frequency signal interference caused by a large number of lines. Compared with the prior art, the present invention uses a simple circuit design to achieve the multiplexing function of the repair line through the switching cooperation between the first resistor and the second resistor added on the test circuit board. When the repair line maintains normal repair When the line function is used, the first resistor is electrically connected to the repairing wire and the second resistor is electrically disconnected from the repairing wire; when the scanning line to be tested needs to be measured, the second resistor is electrically connected to the repairing wire and the first resistor is electrically connected to the repairing wire. The resistor is electrically disconnected from the repair line, and the scanning line to be tested and the repair line are electrically coupled by welding, which not only reduces the number of traces in the GOA circuit, but also freely changes and selects the position of the scanning line to be tested. This increases the flexibility of measurement.

上文中,参照附图描述了本发明的具体实施方式。但是,本领域中的普通技术人员能够理解,在不偏离本发明的精神和范围的情况下,还可以对本发明的具体实施方式作各种变更和替换。这些变更和替换都落在本发明权利要求书所限定的范围内。Hereinbefore, specific embodiments of the present invention have been described with reference to the accompanying drawings. However, those skilled in the art can understand that without departing from the spirit and scope of the present invention, various changes and substitutions can be made to the specific embodiments of the present invention. These changes and substitutions all fall within the scope defined by the claims of the present invention.

Claims (7)

1.一种阵列基板行驱动(Gate driver On Array,GOA)电路的走线结构,其特征在于,该走线结构包括:1. A routing structure of an array substrate row driver (Gate driver On Array, GOA) circuit, characterized in that, the routing structure comprises: 一待测扫描线路,位于一GOA电路内;以及a scan line to be tested, located within a GOA circuit; and 一修补线,位于所述GOA电路内,其中,所述待测扫描线路与所述修补线至少部分重叠,藉由焊接(welding)方式电性耦接所述修补线与所述待测扫描线路,从而实现所述修补线的复用功能。A repair line, located in the GOA circuit, wherein the scan line to be tested overlaps with the repair line at least partially, and the repair line and the scan line to be tested are electrically coupled by welding , so as to realize the multiplexing function of the repair line. 2.根据权利要求1所述的走线结构,其特征在于,所述GOA电路位于液晶盒的内部,且所述液晶盒的外部设有一测试电路板,其包括:2. The wiring structure according to claim 1, wherein the GOA circuit is located inside the liquid crystal box, and a test circuit board is provided outside the liquid crystal box, which includes: 一第一电阻和一第二电阻,透过所述第一电阻和所述第二电阻的投切配合以实现所述修补线的复用功能。A first resistor and a second resistor, through switching cooperation of the first resistor and the second resistor, the multiplexing function of the repair line is realized. 3.根据权利要求2所述的走线结构,其特征在于,当所述修补线维持正常的修线功能时,所述第一电阻与所述修补线电性接通,所述第二电阻与所述修补线电性断开,且所述待测扫描线路与所述修补线电性断开。3. The wiring structure according to claim 2, wherein when the repairing wire maintains a normal repairing function, the first resistor is electrically connected to the repairing wire, and the second resistor It is electrically disconnected from the repairing wire, and the scanning line under test is electrically disconnected from the repairing wire. 4.根据权利要求2所述的走线结构,其特征在于,当所述待测扫描线路需进行测量操作时,所述第二电阻与所述修补线电性接通,所述第一电阻与所述修补线电性断开,且所述待测扫描线路与所述修补线藉由焊接方式电性耦接。4. The wiring structure according to claim 2, wherein when the scanning line to be tested needs to perform a measurement operation, the second resistor is electrically connected to the repair line, and the first resistor It is electrically disconnected from the repairing line, and the scanning line under test is electrically coupled to the repairing line by welding. 5.根据权利要求4所述的走线结构,其特征在于,位于焊接区域下方的所述修补线的一部分被切断。5 . The wiring structure according to claim 4 , wherein a part of the repair line located below the soldering area is cut off. 5 . 6.根据权利要求2至5任意一项所述的走线结构,其特征在于,所述第一电阻为零欧姆电阻。6. The wiring structure according to any one of claims 2 to 5, wherein the first resistor is a zero-ohm resistor. 7.根据权利要求2至5任意一项所述的走线结构,其特征在于,所述第二电阻为零欧姆电阻。7. The wiring structure according to any one of claims 2 to 5, wherein the second resistor is a zero-ohm resistor.
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109445212A (en) * 2018-12-12 2019-03-08 惠科股份有限公司 Display device, repairing method thereof and display
CN109683413A (en) * 2019-02-13 2019-04-26 深圳市华星光电半导体显示技术有限公司 A kind of array substrate and its broken wire repair method
CN110471812A (en) * 2019-07-23 2019-11-19 广东以诺通讯有限公司 A kind of method of USB and AccessPort multiplexing
CN111770629A (en) * 2020-07-10 2020-10-13 福建升腾资讯有限公司 Method for multiplexing on PCB
CN112290222A (en) * 2020-09-27 2021-01-29 南京大学 Programmable anisotropic coded super surface
WO2023115549A1 (en) * 2021-12-21 2023-06-29 Tcl华星光电技术有限公司 Display panel and display apparatus

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109445212A (en) * 2018-12-12 2019-03-08 惠科股份有限公司 Display device, repairing method thereof and display
CN109683413A (en) * 2019-02-13 2019-04-26 深圳市华星光电半导体显示技术有限公司 A kind of array substrate and its broken wire repair method
CN110471812A (en) * 2019-07-23 2019-11-19 广东以诺通讯有限公司 A kind of method of USB and AccessPort multiplexing
CN111770629A (en) * 2020-07-10 2020-10-13 福建升腾资讯有限公司 Method for multiplexing on PCB
CN111770629B (en) * 2020-07-10 2022-01-07 福建升腾资讯有限公司 Method for multiplexing on PCB
CN112290222A (en) * 2020-09-27 2021-01-29 南京大学 Programmable anisotropic coded super surface
CN112290222B (en) * 2020-09-27 2021-10-08 南京大学 A Programmable Anisotropically Encoded Metasurface
WO2023115549A1 (en) * 2021-12-21 2023-06-29 Tcl华星光电技术有限公司 Display panel and display apparatus

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Application publication date: 20150909