CN104900212A - Wiring structure of array substrate row driving circuit - Google Patents

Abstract

The invention provides a routing structure of a GOA circuit, which comprises: a scanning line to be tested is positioned in the GOA circuit; and a repair line located in the GOA circuit. The scanning line to be detected and the repair line are at least partially overlapped, and the repair line and the scanning line to be detected are electrically coupled in a welding mode, so that the multiplexing function of the repair line is realized. Compared with the prior art, the scanning circuit to be detected is electrically coupled to the repair line in a welding mode, so that the virtual grid routing and the repair line in the liquid crystal box are shared, the number of the virtual grid routing in the GOA circuit is reduced, and high-frequency signal interference caused by multiple circuits is reduced. In addition, the invention utilizes simple circuit design, and achieves the multiplexing function of the repair line through the switching matching between the first resistor and the second resistor additionally arranged on the test circuit board, thereby not only reducing the number of routing lines in the GOA circuit, but also freely changing and selecting the position of the scanning line to be tested, and further improving the flexibility of measurement.

Description

A routing structure of an array substrate row drive circuit

technical field

The invention relates to a gate drive circuit of a liquid crystal display device, in particular to a wiring structure of a row drive circuit of an array substrate.

Background technique

Array substrate row drive (Gate Driver on Array, GOA) technology is to directly make the gate driver circuit (Gate Driver ICs) on the array substrate (Array Substrate) to replace the gate driver chip made of external silicon wafer. technology. Generally speaking, the LCD panel using GOA technology in Thin Film Transistor Liquid Crystal Display (TFT-LCD) is called GOA LCD. Compared with traditional TFT-LCDs, GOA liquid crystals can not only save costs, but also help increase production capacity because the bonding process in the direction of the gate is omitted.

During the manufacturing process of the GOA circuit, due to the short circuit or open circuit of the GOA gate, the short circuit or open circuit of the source, and the dust mixed in the liquid crystal box (cell), etc., the panel often has bad phenomena, such as short circuit, disconnection, Bright spots, uneven gray scale or vanishing points, etc. In the prior art, the wiring inside the GOA circuit usually includes a repair line (rescue line), a common electrode line (arraycom) of the array substrate, a common electrode feedback line (array com FB) of the array substrate, and a high-frequency clock signal line (HC ), dummy gate and other lines, and many lines are likely to cause high-frequency signal interference and affect the signal transmission of the GOA circuit.

In view of this, how to design a routing structure of the row driving circuit of the array substrate to eliminate the above-mentioned defects or deficiencies in the prior art is an urgent task to be solved by relevant technical personnel in the industry.

Contents of the invention

Aiming at the defect that the GOA circuit in the prior art is prone to high-frequency signal interference due to numerous traces, the present invention provides a novel trace structure of the GOA circuit.

According to one aspect of the present invention, a wiring structure of a GOA circuit is provided, including:

a scan line to be tested, located within a GOA circuit; and

A repair line, located in the GOA circuit, wherein the scan line to be tested overlaps with the repair line at least partially, and the repair line and the scan line to be tested are electrically coupled by welding , so as to realize the multiplexing function of the repair line.

In one of the embodiments, the GOA circuit is located inside the liquid crystal cell, and a test circuit board is provided outside the liquid crystal cell, which includes: a first resistor and a second resistor, through which the first resistor Cooperating with the switching of the second resistor to realize the multiplexing function of the repair line.

In one embodiment, when the repairing wire maintains a normal repairing function, the first resistor is electrically connected to the repairing wire, and the second resistor is electrically disconnected from the repairing wire, And the scan line to be tested is electrically disconnected from the repair line.

In one embodiment, when the scanning line to be tested needs to perform a measurement operation, the second resistor is electrically connected to the repairing wire, and the first resistor is electrically disconnected from the repairing wire, And the scanning line to be tested is electrically coupled with the repairing line by welding.

In one embodiment, a portion of the repair line below the welding area is severed.

In one embodiment, the first resistor is a zero-ohm resistor.

In one embodiment, the second resistor is a zero-ohm resistor.

The routing structure of the GOA circuit of the present invention includes a scanning line to be tested and a repairing line, and the scanning line to be tested and the repairing line are at least partially overlapped, and the routing structure is electrically connected to the scanning line to be tested by welding. Coupling to the repair line, so that the virtual gate line in the liquid crystal cell and the repair line are shared, thereby reducing the number of virtual gate lines in the GOA circuit, and reducing the high-frequency signal interference caused by a large number of lines. Compared with the prior art, the present invention uses a simple circuit design to achieve the multiplexing function of the repair line through the switching cooperation between the first resistor and the second resistor added on the test circuit board. When the repair line maintains normal repair When the line function is used, the first resistor is electrically connected to the repairing wire and the second resistor is electrically disconnected from the repairing wire; when the scanning line to be tested needs to be measured, the second resistor is electrically connected to the repairing wire and the first resistor is electrically connected to the repairing wire. The resistor is electrically disconnected from the repair line, and the scanning line to be tested and the repair line are electrically coupled by welding, which not only reduces the number of traces in the GOA circuit, but also freely changes and selects the position of the scanning line to be tested. This increases the flexibility of measurement.

Description of drawings

Readers will have a clearer understanding of various aspects of the present invention after reading the detailed description of the present invention with reference to the accompanying drawings. in,

FIG. 1 shows a schematic diagram of a driving principle of a GOA circuit in the prior art;

FIG. 2 shows a schematic diagram of using multiple dummy gates to measure waveforms of corresponding scanning lines in the GOA circuit of FIG. 1;

Figure 3(a) shows a schematic diagram of a wiring structure that can reduce the number of lines in a GOA circuit according to an embodiment of the present invention;

FIG. 3(b) shows a schematic diagram of a state in which the scanning line to be tested and the repairing line at least partially overlap in the wiring structure of FIG. 3(a);

Fig. 4 shows a schematic diagram of switching between the first resistor and the second resistor when the repair line is used as a normal line repair function in the wiring structure of Fig. 3(a);

Figure 5(a) shows a schematic diagram of switching between the first resistor and the second resistor when the repair line is multiplexed as a virtual gate in the GOA circuit in the wiring structure of Figure 3(a); and

FIG. 5( b ) is a schematic diagram showing a state in which the scanning line to be tested and the repairing line are electrically coupled by soldering in the wiring structure of FIG. 5( a ).

Detailed ways

In order to make the technical content disclosed in this application more detailed and complete, reference may be made to the drawings and the following various specific embodiments of the present invention, and the same symbols in the drawings represent the same or similar components. However, those skilled in the art should understand that the examples provided below are not intended to limit the scope of the present invention. In addition, the drawings are only for schematic illustration and are not drawn according to their original scale.

The specific implementation manners of various aspects of the present invention will be further described in detail below with reference to the accompanying drawings.

FIG. 1 shows a schematic diagram of a driving principle of a GOA circuit in the prior art. Referring to Figure 1, the GOA circuit includes multi-level scanning lines Scan 1, Scan 2,..., Scan6, wherein the high-frequency clock signal HC1 is input to the scanning line Scan 1, the high-frequency clock signal HC2 is input to the scanning line Scan 2, and the high-frequency clock signal HC2 is input to the scanning line Scan 2. The clock signal HC3 is input to the scanning line Scan 3, the high-frequency clock signal HC4 is input to the scanning line Scan 4, and then the high-frequency clock signal HC1 is input to the scanning line Scan 5, and the high-frequency clock signal HC2 is input to the scanning line Scan 6. That is to say, the high-frequency clock signal HC1 is input to the scanning lines Scan 1 and Scan 5 at the same time, and the high-frequency clock signal HC2 is input to the scanning lines Scan 2 and Scan 6 at the same time.

In addition, the scanning lines of the previous stage and the scanning lines of the subsequent stage are closely related in terms of control timing. Specifically, the control signal turn off1 output by the subsequent scan line Scan 2 is used to turn off the previous scan line Scan 1, and the control signal turn off2 output by the subsequent scan line Scan 3 is used to close the previous scan line Scan 2. Similarly, the control signal turn off3 output by the subsequent scan line Scan 4 is used to turn off the previous scan line Scan 3, and the control signal turn off4 output by the subsequent scan line Scan 5 is used to close the previous scan line Scan 4.

FIG. 2 shows a schematic diagram of using multiple dummy gates to measure waveforms of corresponding scanning lines in the GOA circuit of FIG. 1 .

Referring to FIG. 2, numeral 100 denotes a liquid crystal cell (cell), 102 denotes a GOA circuit of the liquid crystal cell 100, and 200 denotes a test circuit board (also called a P board). The test circuit board 200 includes a dummy gate 202 and a dummy gate 204, wherein the dummy gate 202 is electrically coupled to the corresponding scan line to be tested in the GOA circuit 102 to measure its waveform, and the dummy gate 204 is electrically coupled to to the corresponding scan line to be tested in the GOA circuit 102 to measure its waveform.

As mentioned above, the current GOA circuit usually contains various types of wiring, such as the rescue line, the common electrode line of the array substrate (array com), the common electrode feedback line of the array substrate (array com FB), There are many lines such as high-frequency clock signal line (HC), dummy gate (dummy gate), and many lines are likely to cause high-frequency signal interference and affect the signal transmission of the GOA circuit. In addition, there is a one-to-one correspondence between the virtual gate and the line connection between the scanning lines to be tested, and the measurement method is relatively rigid, and it is impossible to flexibly measure waveforms on different scanning lines.

In order to solve the above-mentioned problems in the prior art, the present invention provides a novel wiring structure of a GOA circuit. FIG. 3( a ) shows a schematic diagram of a routing structure that can reduce the number of lines in a GOA circuit according to an embodiment of the present invention. FIG. 3( b ) is a schematic diagram showing a state where the scanning line to be tested and the repairing line overlap at least partially in the wiring structure of FIG. 3( a ).

Referring to FIG. 3( a ), in this embodiment, the wiring structure of the present invention includes a scan line 104 to be tested and a repair line 106 , both of which are located in the GOA circuit. It should be noted that the scanning line 104 to be tested overlaps with the repairing line 106 at least partially, as shown in FIG. 3( b ). In this way, the present invention can electrically couple the scanning line 104 to be tested to the repairing line 106 by welding, so that the repairing line 106 in the GOA circuit is used as the routing of the dummy gate 202 in the circuit, Then realize the multiplexing and sharing function of the repair line.

In a specific embodiment, the GOA circuit is located inside the liquid crystal cell 100 , and a test circuit board 200 is provided outside the liquid crystal cell 100 . The test circuit board 200 includes a first resistor R1 and a second resistor R2. The present invention realizes the multiplexing function of the repair line through the switching cooperation of the first resistor R1 and the second resistor R2. Here, the switch fit mainly means that the first resistor R1 is electrically coupled or disconnected from the repair wire 106 , and the second resistor R2 is electrically coupled or disconnected from the repair wire 106 .

In a specific embodiment, the first resistor R1 is a zero-ohm resistor. Alternatively, the second resistor R2 is a zero-ohm resistor. Here, the zero-ohm resistor is also called a jumper resistor, which is a special-purpose resistor. The zero-ohm resistor does not have a real resistance value of zero, but is actually a resistor with a very small resistance value. For example, when two points in the circuit board design cannot be connected by a printed circuit, they are often connected with a jumper on the front side, and in order for the automatic placement machine and automatic plug-in machine to work normally, a zero-ohm resistor can be used instead of the jumper. In a sense, zero-ohm resistors are only used on circuit boards for debugging convenience or compatible designs, etc.

FIG. 4 shows a schematic diagram of switching between the first resistor and the second resistor when the repair line serves as a normal line repair function in the wiring structure of FIG. 3( a ).

Referring to FIG. 4 , in this embodiment, the repair wire 106 serves a normal wire repair function. Specifically, when the repairing wire 106 maintains a normal repairing function, the first resistor R1 is electrically connected to the repairing wire 106 , and the second resistor R2 is electrically disconnected from the repairing wire 106 . At this time, although the scan line 104 to be tested partially overlaps with the repair line 106 , no welding operation is applied, so the scan line 104 to be tested and the repair line 106 are not electrically connected.

FIG. 5( a ) shows a schematic diagram of switching between the first resistor and the second resistor when the repair line is multiplexed as the routing of the dummy gate in the GOA circuit in the routing structure of FIG. 3( a ). FIG. 5( b ) is a schematic diagram showing a state in which the scanning line to be tested and the repairing line are electrically coupled by soldering in the wiring structure of FIG. 5( a ).

Referring to FIG. 5( a ) and FIG. 5( b ), in this embodiment, the repair line 106 is multiplexed as the routing of the dummy gate 202 inside the GOA circuit to measure the waveform of the scanning line 104 to be tested. In detail, when the scan line 104 to be tested needs to perform a measurement operation, the second resistor R2 is electrically connected to the repair line 106, the first resistor R1 is electrically disconnected from the repair line 106, and the scan line 104 to be tested is electrically connected to the repair line 106. The wires 106 are electrically coupled by welding, as shown in FIG. 5( b ). Preferably, in this case, a part of the repair line 104 located below the welding area can also be cut off. It should be understood that the scanning lines 104 to be tested in the GOA circuit can be replaced with different scanning lines according to actual measurement requirements. Since these scanning lines overlap with the repairing line 104 at least partially, it is always possible to measure the The waveform on any one of the scanning lines, thus improving the flexibility of measurement.

The routing structure of the GOA circuit of the present invention includes a scanning line to be tested and a repairing line, and the scanning line to be tested and the repairing line are at least partially overlapped, and the routing structure is electrically connected to the scanning line to be tested by welding. Coupling to the repair line, so that the virtual gate line in the liquid crystal cell and the repair line are shared, thereby reducing the number of virtual gate lines in the GOA circuit, and reducing the high-frequency signal interference caused by a large number of lines. Compared with the prior art, the present invention uses a simple circuit design to achieve the multiplexing function of the repair line through the switching cooperation between the first resistor and the second resistor added on the test circuit board. When the repair line maintains normal repair When the line function is used, the first resistor is electrically connected to the repairing wire and the second resistor is electrically disconnected from the repairing wire; when the scanning line to be tested needs to be measured, the second resistor is electrically connected to the repairing wire and the first resistor is electrically connected to the repairing wire. The resistor is electrically disconnected from the repair line, and the scanning line to be tested and the repair line are electrically coupled by welding, which not only reduces the number of traces in the GOA circuit, but also freely changes and selects the position of the scanning line to be tested. This increases the flexibility of measurement.

Hereinbefore, specific embodiments of the present invention have been described with reference to the accompanying drawings. However, those skilled in the art can understand that without departing from the spirit and scope of the present invention, various changes and substitutions can be made to the specific embodiments of the present invention. These changes and substitutions all fall within the scope defined by the claims of the present invention.

Claims (7)

1. A routing structure of an array substrate row driver (Gate driver On Array, GOA) circuit, characterized in that, the routing structure comprises: a scan line to be tested, located within a GOA circuit; and A repair line, located in the GOA circuit, wherein the scan line to be tested overlaps with the repair line at least partially, and the repair line and the scan line to be tested are electrically coupled by welding , so as to realize the multiplexing function of the repair line. 2. The wiring structure according to claim 1, wherein the GOA circuit is located inside the liquid crystal box, and a test circuit board is provided outside the liquid crystal box, which includes: A first resistor and a second resistor, through switching cooperation of the first resistor and the second resistor, the multiplexing function of the repair line is realized. 3. The wiring structure according to claim 2, wherein when the repairing wire maintains a normal repairing function, the first resistor is electrically connected to the repairing wire, and the second resistor It is electrically disconnected from the repairing wire, and the scanning line under test is electrically disconnected from the repairing wire. 4. The wiring structure according to claim 2, wherein when the scanning line to be tested needs to perform a measurement operation, the second resistor is electrically connected to the repair line, and the first resistor It is electrically disconnected from the repairing line, and the scanning line under test is electrically coupled to the repairing line by welding. 5 . The wiring structure according to claim 4 , wherein a part of the repair line located below the soldering area is cut off. 5 . 6. The wiring structure according to any one of claims 2 to 5, wherein the first resistor is a zero-ohm resistor. 7. The wiring structure according to any one of claims 2 to 5, wherein the second resistor is a zero-ohm resistor.