CN104900212A - Wiring structure for GOA (Gate driver On Array) circuit - Google Patents
Wiring structure for GOA (Gate driver On Array) circuit Download PDFInfo
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- CN104900212A CN104900212A CN201510377541.0A CN201510377541A CN104900212A CN 104900212 A CN104900212 A CN 104900212A CN 201510377541 A CN201510377541 A CN 201510377541A CN 104900212 A CN104900212 A CN 104900212A
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- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 17
- 238000003466 welding Methods 0.000 claims abstract description 16
- 238000012360 testing method Methods 0.000 claims abstract description 12
- 210000002858 crystal cell Anatomy 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 238000005476 soldering Methods 0.000 claims description 3
- 238000013461 design Methods 0.000 abstract description 6
- 238000005259 measurement Methods 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 14
- 208000032005 Spinocerebellar ataxia with axonal neuropathy type 2 Diseases 0.000 description 5
- 208000033361 autosomal recessive with axonal neuropathy 2 spinocerebellar ataxia Diseases 0.000 description 5
- 210000004027 cell Anatomy 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides a wiring structure for a GOA (Gate driver On Array) circuit. The wiring structure comprises a scan line to be measured and a rescue line, wherein the scan line to be measured is located in the GOA circuit, and the rescue line is located in the GOA circuit. The scan line to be measured and the rescue line are at least partially overlapped and are electrically coupled in a welding manner, so as to achieve the function of multiplexing the rescue line. Compared with the prior art, the wiring structure has the advantages that the scan line to be measured is electrically coupled to the rescue line in the welding manner, so that the sharing between dummy gate wires in a liquid crystal cell and the rescue line is realized, then, the number of the dummy gate wires in the GOA circuit is reduced, and high-frequency signal interference caused by line variety is lowered. In addition, a simple circuit design is utilized, and the function of multiplexing the rescue line is achieved through testing switching cooperation between a first resistor and a second resistor which are additionally arranged on a circuit board, so that the number of wires in the GOA circuit is reduced, the location of the scan line to be measured can be freely changed and selected, and then, the flexibility of measurement is improved.
Description
Technical Field
The present invention relates to a gate driving circuit of a liquid crystal display device, and more particularly, to a routing structure of a row driving circuit of an array substrate.
Background
The Gate Driver on Array (GOA) technology is a technology for directly fabricating Gate Driver circuits (Gate drivers ICs) on an Array Substrate (Array Substrate) instead of a Gate Driver chip fabricated from an external silicon wafer. Generally, a Liquid Crystal panel using the GOA technology in a Thin Film Transistor Liquid Crystal Display (TFT-LCD) is called a GOA Liquid Crystal. Compared with the traditional TFT-LCD, the GOA liquid crystal can save cost, and is favorable for improving the productivity due to the fact that the binding process in the grid direction is omitted.
In the manufacturing process of the GOA circuit, the panel is often defective due to short circuit or open circuit of the gate of the GOA, short circuit or open circuit of the source, dust mixed in the liquid crystal cell (cell), and the like, such as short circuit, broken line, bright spot, uneven gray scale or dead spot. In the prior art, the routing inside the GOA circuit usually includes a repair line (repair line), a common electrode line (array com) of the array substrate, a common electrode feedback line (array com FB) of the array substrate, a high-frequency clock signal line (HC), a dummy gate (dummy gate), and other multiple lines, and the multiple lines are prone to cause high-frequency signal interference, which affects signal transmission of the GOA circuit.
In view of the above, a problem to be solved by those skilled in the art is how to design a routing structure of a column driving circuit of an array substrate to eliminate the above-mentioned defects or shortcomings in the prior art.
Disclosure of Invention
Aiming at the defect that the GOA circuit in the prior art is easy to form high-frequency signal interference due to various routing, the invention provides a novel routing structure of the GOA circuit.
According to an aspect of the present invention, there is provided a routing structure of a GOA circuit, including:
a scanning line to be tested is positioned in a GOA circuit; and
and the repair line is positioned in the GOA circuit, wherein the scanning line to be detected and the repair line are at least partially overlapped, and the repair line and the scanning line to be detected are electrically coupled in a welding (welding) mode, so that the multiplexing function of the repair line is realized.
In one embodiment, the GOA circuit is located inside a liquid crystal cell, and a test circuit board is disposed outside the liquid crystal cell, and the test circuit board includes: and the first resistor and the second resistor are matched with each other through switching of the first resistor and the second resistor to realize the multiplexing function of the repair line.
In one embodiment, when the repair line maintains a normal repair function, the first resistor is electrically connected to the repair line, the second resistor is electrically disconnected from the repair line, and the scan line to be tested is electrically disconnected from the repair line.
In one embodiment, when the scan line to be tested needs to be measured, the second resistor is electrically connected to the repair line, the first resistor is electrically disconnected from the repair line, and the scan line to be tested is electrically coupled to the repair line by welding.
In one embodiment, a portion of the repair line under the bonding region is cut off.
In one embodiment, the first resistance is a zero ohm resistance.
In one embodiment, the second resistance is a zero ohm resistance.
The routing structure of the GOA circuit comprises a scanning line to be detected and a repairing line, wherein the scanning line to be detected and the repairing line are at least partially overlapped, the scanning line to be detected is electrically coupled to the repairing line by the routing structure in a welding mode, so that the virtual grid routing and the repairing line in the liquid crystal box are shared, the number of the virtual grid routing in the GOA circuit is reduced, and high-frequency signal interference caused by various lines is reduced. Compared with the prior art, the invention utilizes simple circuit design, achieves the multiplexing function of the repair line through the switching matching between the first resistor and the second resistor additionally arranged on the test circuit board, and when the repair line maintains the normal line repair function, the first resistor is electrically connected with the repair line, and the second resistor is electrically disconnected with the repair line; when the scanning line to be measured needs to be measured, the second resistor is electrically connected with the repair line, the first resistor is electrically disconnected with the repair line, and the scanning line to be measured is electrically coupled with the repair line in a welding mode, so that the number of wires in the GOA circuit is reduced, the position of the scanning line to be measured can be freely changed and selected, and the measurement flexibility is further improved.
Drawings
The various aspects of the present invention will become more apparent to the reader after reading the detailed description of the invention with reference to the attached drawings. Wherein,
fig. 1 shows a schematic diagram of a driving principle of a GOA circuit in the prior art;
fig. 2 is a schematic diagram illustrating a waveform of a corresponding scan line measured by using a plurality of dummy gates in the GOA circuit of fig. 1;
FIG. 3(a) is a schematic diagram of a trace structure for reducing the number of lines in a GOA circuit according to an embodiment of the present invention;
fig. 3(b) is a schematic diagram illustrating a state where the scan line to be tested and the repair line are at least partially overlapped in the routing structure of fig. 3 (a);
fig. 4 is a schematic diagram illustrating switching between the first resistor and the second resistor when the repair line is used as a normal repair line in the routing structure of fig. 3 (a);
fig. 5(a) shows a switching schematic diagram of the first resistor and the second resistor when the repair line is multiplexed as the routing of the virtual gate in the GOA circuit in the routing structure of fig. 3 (a); and
fig. 5(b) is a schematic diagram illustrating a state that the scan line to be tested and the repair line are electrically coupled by welding in the routing structure of fig. 5 (a).
Detailed Description
In order to make the present disclosure more complete and complete, reference is made to the accompanying drawings, in which like references indicate similar or analogous elements, and to the various embodiments of the invention described below. However, it will be understood by those of ordinary skill in the art that the examples provided below are not intended to limit the scope of the present invention. In addition, the drawings are only for illustrative purposes and are not drawn to scale.
Specific embodiments of various aspects of the present invention are described in further detail below with reference to the accompanying drawings.
Fig. 1 shows a schematic diagram of a driving principle of a GOA circuit in the prior art. Referring to fig. 1, the GOA circuit includes multiple stages of Scan lines Scan 1, Scan 2, …, and Scan6, where a high frequency clock signal HC1 is input to the Scan line Scan 1, a high frequency clock signal HC2 is input to the Scan line Scan 2, a high frequency clock signal HC3 is input to the Scan line Scan 3, a high frequency clock signal HC4 is input to the Scan line Scan 4, a high frequency clock signal HC1 is input to the Scan line Scan 5, and a high frequency clock signal HC2 is input to the Scan line Scan 6. That is, the high frequency clock signal HC1 is simultaneously input to the Scan lines Scan 1 and Scan 5, and the high frequency clock signal HC2 is simultaneously input to the Scan lines Scan 2 and Scan 6.
In addition, the preceding stage scanning line and the succeeding stage scanning line are closely related in control timing. Specifically, the control signal turn off1 output by the Scan line Scan 2 at the next stage is used to turn off the Scan line Scan 1 at the previous stage, and the control signal turn off2 output by the Scan line Scan 3 at the next stage is used to turn off the Scan line Scan 2 at the previous stage. Similarly, the control signal turn off3 output by the Scan line Scan 4 at the next stage is used to turn off the Scan line Scan 3 at the previous stage, and the control signal turn off4 output by the Scan line Scan 5 at the next stage is used to turn off the Scan line Scan 4 at the previous stage.
Fig. 2 is a schematic diagram illustrating a waveform of a corresponding scan line measured by using a plurality of dummy gates in the GOA circuit of fig. 1.
Referring to fig. 2, reference numeral 100 denotes a liquid crystal cell (cell), 102 denotes a GOA circuit of the liquid crystal cell 100, and 200 denotes a test circuit board (which may also be referred to as a P-plate). The test circuit board 200 includes a dummy gate 202 and a dummy gate 204, wherein the dummy gate 202 is electrically coupled to the corresponding scan line under test in the GOA circuit 102 to measure the waveform thereof, and the dummy gate 204 is electrically coupled to the corresponding scan line under test in the GOA circuit 102 to measure the waveform thereof.
As mentioned above, currently, the GOA circuit usually includes various types of routing lines, such as a repair line (repair line), a common electrode line (array com) of the array substrate, a common electrode feedback line (array com FB) of the array substrate, a high frequency clock signal line (HC), a dummy gate (dummy gate), and so on, and the lines are various and easily cause high frequency signal interference, which affects signal transmission of the GOA circuit. In addition, the line connections between the virtual grid and the scanning lines to be measured are in one-to-one correspondence, and the measurement mode is relatively rigid, so that the waveforms on different scanning lines cannot be flexibly measured.
In order to solve the above problems in the prior art, the present invention provides a novel routing structure of a GOA circuit. Fig. 3(a) is a schematic diagram of a trace structure for reducing the number of lines in a GOA circuit according to an embodiment of the present invention. Fig. 3(b) is a schematic diagram illustrating a state in which the scan line to be tested and the repair line are at least partially overlapped in the routing structure of fig. 3 (a).
Referring to fig. 3(a), in this embodiment, the routing structure of the present invention includes a scan line 104 to be tested and a repair line 106, both located in the GOA circuit. It should be noted that the scan line 104 to be tested and the repair line 106 at least partially overlap, as shown in fig. 3 (b). In this way, the scan line 104 to be tested can be electrically coupled to the repair line 106 by soldering (welding), so that the repair line 106 in the GOA circuit can be used as a routing of the dummy gate 202 in the circuit, thereby realizing multiplexing and sharing functions of the repair line.
In one embodiment, the GOA circuit is located inside the liquid crystal cell 100, and a test circuit board 200 is disposed outside the liquid crystal cell 100. The test circuit board 200 comprises a first resistor R1 and a second resistor R2, and the multiplexing function of the repair line is realized through the switching cooperation of the first resistor R1 and the second resistor R2. Here, the switching coordination mainly means that the first resistor R1 is electrically coupled to or disconnected from the repair line 106, and the second resistor R2 is electrically coupled to or disconnected from the repair line 106.
In one embodiment, the first resistor R1 is a zero ohm resistor. Alternatively, the second resistor R2 is a zero ohm resistor. Here, the zero ohm resistor is also called a bridge resistor, and is a special purpose resistor, and the 0 ohm resistor is not a real resistor with zero resistance value, and is actually a resistor with a very small resistance value. For example, when two points in a circuit board design cannot be connected by a printed circuit, the front surface is often connected by a jumper wire, and the jumper wire can be replaced by a zero-ohm resistor for the normal operation of the automatic chip mounter and the automatic component inserter. In a sense, zero ohm resistors are used only on the circuit board for debugging convenience or compatibility design, etc.
Fig. 4 shows a switching schematic diagram of the first resistor and the second resistor when the repair line is used as a normal repair line function in the routing structure of fig. 3 (a).
Referring to fig. 4, in this embodiment, the repair line 106 serves a normal repair function. Specifically, when the repair line 106 maintains the normal repair function, the first resistor R1 is electrically connected to the repair line 106, and the second resistor R2 is electrically disconnected from the repair line 106. At this time, the scan line 104 to be tested and the repair line 106 are partially overlapped, but no welding operation is applied, so that the scan line 104 to be tested and the repair line 106 are not electrically connected.
Fig. 5(a) shows a switching schematic diagram of the first resistor and the second resistor when the repair line is multiplexed as the routing of the virtual gate in the GOA circuit in the routing structure of fig. 3 (a). Fig. 5(b) is a schematic diagram illustrating a state that the scan line to be tested and the repair line are electrically coupled by welding in the routing structure of fig. 5 (a).
Referring to fig. 5(a) and 5(b), in this embodiment, the repair line 106 is multiplexed as a routing of the dummy gate 202 inside the GOA circuit to measure the waveform of the scan line 104 to be measured. In detail, when the scan line 104 to be tested needs to be measured, the second resistor R2 is electrically connected to the repair line 106, the first resistor R1 is electrically disconnected from the repair line 106, and the scan line 104 to be tested is electrically coupled to the repair line 106 by soldering, as shown in fig. 5 (b). Preferably, in this case, a portion of the repair line 104 located below the bonding region may also be cut. It should be understood that the scanning line 104 to be measured in the GOA circuit can be replaced by a different scanning line according to actual measurement requirements, and since the scanning lines are at least partially overlapped with the repair line 104, the waveform on any one of the scanning lines can be always measured by using the welding operation, thereby improving the measurement flexibility.
The routing structure of the GOA circuit comprises a scanning line to be detected and a repairing line, wherein the scanning line to be detected and the repairing line are at least partially overlapped, the scanning line to be detected is electrically coupled to the repairing line by the routing structure in a welding mode, so that the virtual grid routing and the repairing line in the liquid crystal box are shared, the number of the virtual grid routing in the GOA circuit is reduced, and high-frequency signal interference caused by various lines is reduced. Compared with the prior art, the invention utilizes simple circuit design, achieves the multiplexing function of the repair line through the switching matching between the first resistor and the second resistor additionally arranged on the test circuit board, and when the repair line maintains the normal line repair function, the first resistor is electrically connected with the repair line, and the second resistor is electrically disconnected with the repair line; when the scanning line to be measured needs to be measured, the second resistor is electrically connected with the repair line, the first resistor is electrically disconnected with the repair line, and the scanning line to be measured is electrically coupled with the repair line in a welding mode, so that the number of wires in the GOA circuit is reduced, the position of the scanning line to be measured can be freely changed and selected, and the measurement flexibility is further improved.
Hereinbefore, specific embodiments of the present invention are described with reference to the drawings. However, those skilled in the art will appreciate that various modifications and substitutions can be made to the specific embodiments of the present invention without departing from the spirit and scope of the invention. Such modifications and substitutions are intended to be included within the scope of the present invention as defined by the appended claims.
Claims (7)
1. The utility model provides an Array substrate line drive (GOA) circuit walk line structure, its characterized in that should walk the line structure and include:
a scanning line to be tested is positioned in a GOA circuit; and
and the repair line is positioned in the GOA circuit, wherein the scanning line to be detected and the repair line are at least partially overlapped, and the repair line and the scanning line to be detected are electrically coupled in a welding (welding) mode, so that the multiplexing function of the repair line is realized.
2. The trace structure according to claim 1, wherein the GOA circuit is located inside a liquid crystal cell, and a test circuit board is disposed outside the liquid crystal cell, and comprises:
and the first resistor and the second resistor are matched with each other through switching of the first resistor and the second resistor to realize the multiplexing function of the repair line.
3. The trace structure according to claim 2, wherein when the repair line maintains a normal repair function, the first resistor is electrically connected to the repair line, the second resistor is electrically disconnected from the repair line, and the scan line to be tested is electrically disconnected from the repair line.
4. The trace structure according to claim 2, wherein when the scan line to be tested needs to be measured, the second resistor is electrically connected to the repair line, the first resistor is electrically disconnected from the repair line, and the scan line to be tested is electrically coupled to the repair line by soldering.
5. The routing structure of claim 4, wherein a portion of the repair line under the bonding area is cut.
6. The trace structure according to any one of claims 2 to 5, wherein the first resistance is a zero ohm resistance.
7. The trace structure according to any one of claims 2 to 5, wherein the second resistance is a zero ohm resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510377541.0A CN104900212A (en) | 2015-07-01 | 2015-07-01 | Wiring structure for GOA (Gate driver On Array) circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510377541.0A CN104900212A (en) | 2015-07-01 | 2015-07-01 | Wiring structure for GOA (Gate driver On Array) circuit |
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| CN104900212A true CN104900212A (en) | 2015-09-09 |
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| CN201510377541.0A Pending CN104900212A (en) | 2015-07-01 | 2015-07-01 | Wiring structure for GOA (Gate driver On Array) circuit |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109445212A (en) * | 2018-12-12 | 2019-03-08 | 惠科股份有限公司 | Display device, repairing method thereof and display |
| CN109683413A (en) * | 2019-02-13 | 2019-04-26 | 深圳市华星光电半导体显示技术有限公司 | A kind of array substrate and its broken wire repair method |
| CN110471812A (en) * | 2019-07-23 | 2019-11-19 | 广东以诺通讯有限公司 | A kind of method of USB and AccessPort multiplexing |
| CN111770629A (en) * | 2020-07-10 | 2020-10-13 | 福建升腾资讯有限公司 | Method for multiplexing on PCB |
| CN112290222A (en) * | 2020-09-27 | 2021-01-29 | 南京大学 | Programmable anisotropic coded super surface |
| WO2023115549A1 (en) * | 2021-12-21 | 2023-06-29 | Tcl华星光电技术有限公司 | Display panel and display apparatus |
-
2015
- 2015-07-01 CN CN201510377541.0A patent/CN104900212A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109445212A (en) * | 2018-12-12 | 2019-03-08 | 惠科股份有限公司 | Display device, repairing method thereof and display |
| CN109683413A (en) * | 2019-02-13 | 2019-04-26 | 深圳市华星光电半导体显示技术有限公司 | A kind of array substrate and its broken wire repair method |
| CN110471812A (en) * | 2019-07-23 | 2019-11-19 | 广东以诺通讯有限公司 | A kind of method of USB and AccessPort multiplexing |
| CN111770629A (en) * | 2020-07-10 | 2020-10-13 | 福建升腾资讯有限公司 | Method for multiplexing on PCB |
| CN111770629B (en) * | 2020-07-10 | 2022-01-07 | 福建升腾资讯有限公司 | Method for multiplexing on PCB |
| CN112290222A (en) * | 2020-09-27 | 2021-01-29 | 南京大学 | Programmable anisotropic coded super surface |
| CN112290222B (en) * | 2020-09-27 | 2021-10-08 | 南京大学 | Programmable anisotropic coded super surface |
| WO2023115549A1 (en) * | 2021-12-21 | 2023-06-29 | Tcl华星光电技术有限公司 | Display panel and display apparatus |
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Application publication date: 20150909 |