CN104899172A - Node connection chip communication circuit and data communication method - Google Patents
Node connection chip communication circuit and data communication method Download PDFInfo
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- CN104899172A CN104899172A CN201510158279.0A CN201510158279A CN104899172A CN 104899172 A CN104899172 A CN 104899172A CN 201510158279 A CN201510158279 A CN 201510158279A CN 104899172 A CN104899172 A CN 104899172A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
Abstract
The invention discloses a node connection chip communication circuit, which comprises a first node connection chip and a second node connection chip, wherein the first node connection chip and the second connection chip are in signal connection and carry out data communication. The microcontrollers of the node connection chips are used for controlling a sending unit or a receiving unit of a data port to be effective so as to independently set the first node connection chip and the second node connection chip as a main chip and a slave chip, a data communication link is provided for a neighbor node connection chip, a data communication circuit of the node connection chips is used for transmitting the detailed information of the node connection chips, and detailed node information is quickly provided for a node network.
Description
Technical field
The present invention relates to electronic information technical field, particularly relate to a kind of node and connect chip communication circuit and data communication method.
Background technology
The existing common way of nodal test system based on meshed network is that loop circuit is placed on region to be measured, when loop circuit link is destroyed, nodal test system based on meshed network can get the information of having damaged, but loop circuit can not provide the details about damaging link.Along with the development of technology, in order to distinguish the broken segments in region to be measured, the independent loop of each partial design, but still there is very formidable shortcoming-can only identify that a part is wherein destroyed, and very limited when being applied to the damage situation of monitoring yarn fabric in textile clothes, because this technology does not allow the high density loop created.Therefore, occurred comprising the detection loop that is much connected with Local microcontroller and sent the subnet of local state information to primary processor by Local microcontroller, but subnet means that data transmission bus requirement is too wide in a large number, data processing speed is slow.
Based on this, be necessary that designing a kind of node connects chip communication circuit and data communication method, connect chip data communicating circuit by node and transmit detailed node connection chip information, for meshed network Quick is for detailed nodal information.
Summary of the invention
Fundamental purpose of the present invention is to provide a kind of node to connect chip communication circuit and data communication method, connects chip data communicating circuit transmit detailed node connection chip information, for meshed network Quick is for detailed nodal information by node.
For achieving the above object, the invention provides a kind of node and connect chip communication circuit, described node connection chip communication circuit comprises first node connection chip and is connected chip with Section Point, and described first node connection chip is connected chip signal and connects and carry out data communication with described Section Point; Described node connects the FPDP that chip comprises microprocessor and is connected with described microprocessor signals, described FPDP comprises switch unit, receiving element and transmitting element, described FPDP and described microprocessor by power input, receive data terminal, receive data ground hold, selecting side, power output end, transmission data terminal, send data end signal be connected; Described reception data terminal comprises reception data input pin and receives data output end, and described transmission data terminal comprises transmission data input pin and transmission data output end;
The selecting side of first node connection chip described in the Microprocessor S3C44B0X of described first node connection chip is connected chip power output end with described first node connects, it is master chip that described first node connects chip, and the FPDP transmitting element that described first node connects chip is effective; Described in the Microprocessor S3C44B0X of described Section Point connection chip, the selecting side of Section Point connection chip be connected the reception data of chip with described Section Point is held and is connected, it is from chip that described Section Point connects chip, and the FPDP receiving element that described Section Point connects chip is effective.
Wherein in an embodiment, described receiving element and described switch unit are connected by receiving input port and receiving output port signal, between described receiving element with described microprocessor by described power input, receive data terminal and end signal is connected with receiving data;
Described transmitting element and described switch unit are connected by sending input port and sending output port signal, between described transmitting element with described microprocessor by described power output end, send data terminal, with sending data end signal be connected;
Described switch unit is connected by selecting side signal with described microprocessor, and described processor controls described switch unit by described selecting side and is communicated with described receiving element, or controls described switch unit and be communicated with described transmitting element; Described switch unit carries out data communication by described signal input part and described signal output part and the external world.
Wherein in an embodiment, the power output end of described first node connection chip and transmission data ground arrange the first electric capacity between holding, the transmission input port of described first node connection chip and transmission data ground arrange the first resistance between holding, between the transmission data output end of described first node connection chip and transmission output port, the first phase inverter is set, between the transmission data input pin of described first node connection chip and transmission input port, the first switching tube is set; The power input of described Section Point connection chip and reception data ground arrange the second electric capacity between holding, the reception input port of described Section Point connection chip and reception data ground arrange the second resistance between holding, between the reception data output end of described Section Point connection chip and reception output port, the second phase inverter is set, between the reception data input pin of described Section Point connection chip and reception input port, second switch pipe is set.
For achieving the above object, present invention also offers a kind of node and connect the chip data means of communication, described node connects the chip data means of communication and comprises the steps:
S1: the selecting side of first node connection chip described in the Microprocessor S3C44B0X of first node connection chip is connected chip power output end with described first node connects, arranging described first node connection chip is master chip, and the transmitting element that described first node connects chip data port is effective;
S2: the selecting side of Section Point connection chip described in the Microprocessor S3C44B0X of Section Point connection chip be connected the reception data of chip with described Section Point is held and connected, arranging described Section Point connection chip is from chip, and the receiving element that described Section Point connects chip data port is effective;
S3: the FPDP of described first node connection chip is connected the dataport data communication of chip with described Section Point.
Wherein in an embodiment, described step S3 comprises:
S31: the FPDP that the FPDP that described first node connects chip connects chip to described Section Point sends data, the data that the FPDP that the FPDP that described Section Point connects chip receives described first node connection chip sends;
S32: the FPDP that the FPDP that described Section Point connects chip connects chip to described first node sends data, the data that the FPDP that the FPDP that first node connects chip receives described Section Point connection chip sends.
Wherein in an embodiment, described step S31 comprises:
S311: the microprocessor controls transmission data output end that first node connects chip is connected with transmission data ground end signal;
S312: first node connects the power output end of chip via the first electric capacity, the second electric capacity, the first resistance and the second resistance, is the first electric capacity and the second capacitor charging;
S313: after charging terminates, the data that first node connects chip are sent to through the transmitting element that first node connects chip data port the receiving element that Section Point connects chip data port;
S314: the microprocessor controls transmission data output end that first node connects chip is connected with power output end signal;
S315: the second electric capacity is by the second conductive discharge, and second switch management and control Section Point connects the receiving element Received signal strength of chip data port.
Wherein in an embodiment, described step S32 comprises:
S321: the microprocessor controls reception data output end that Section Point connects chip is connected with reception data ground end signal;
S322: Section Point connects the power input of chip via the first electric capacity, the second electric capacity, the first resistance and the second resistance, is the first electric capacity and the second capacitor charging;
S323: after charging terminates, the data that Section Point connects chip are sent to through the receiving element that Section Point connects chip data port the transmitting element that first node connects chip data port;
S324: the microprocessor controls reception data output end that Section Point connects chip is connected with power input signal;
S325: the first electric capacity is by the first conductive discharge, and the first switch controlled first node connects the transmitting element Received signal strength of chip data port.
The present invention adopts technique scheme, the technique effect brought is: the embodiment of the present invention connect the transmitting element of microprocessor controls FPDP of chip by node or receiving element effective, thus first node is connected chip and be connected chip with Section Point and be set to master chip respectively and from chip, data communication link is provided for neighbor node connects chip, connect chip data communicating circuit by node and transmit detailed node connection chip information, for meshed network Quick is for detailed nodal information.
Accompanying drawing explanation
Fig. 1 is that node of the present invention connects chip communication circuit preferred embodiment connection block diagram;
Fig. 2 is that node of the present invention connects chip first preferred embodiment electrical block diagram;
Fig. 3 is that node of the present invention connects chip communication circuit preferred embodiment syndeton schematic diagram;
Fig. 4 is that node of the present invention connects chip communication circuit preferred embodiment local circuit structural representation;
Fig. 5 is that node of the present invention connects chip data means of communication preferred embodiment schematic flow sheet.
The realization of the object of the invention, functional characteristics and advantage will in conjunction with the embodiments, are described further with reference to accompanying drawing.
Embodiment
Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
Fundamental purpose of the present invention is to provide a kind of node to connect chip communication circuit and data communication method, connects chip data communicating circuit transmit detailed node connection chip information, for meshed network Quick is for detailed nodal information by node.
For achieving the above object, the invention provides a kind of node and connect chip communication circuit.
With reference to Fig. 1, Figure 1 shows that node of the present invention connects the preferred embodiment of chip communication circuit and connects block diagram, described node connection chip communication circuit comprises first node connection chip 01 and is connected chip 02 with Section Point, and described first node connection chip 01 is connected chip 02 signal and connects and carry out data communication with described Section Point; Particularly, with reference to Fig. 2, Figure 2 shows that invention node connects chip first preferred embodiment electrical block diagram, described node connects the FPDP 2 that chip comprises microprocessor 1 and is connected with described microprocessor 1 signal, described FPDP 2 comprises switch unit 21, receiving element 22 and transmitting element 23, described FPDP 2 and described microprocessor 1 by power input, receive data terminal, receive data ground hold, selecting side, power output end, transmission data terminal, send data end signal be connected; Described reception data terminal comprises reception data input pin and receives data output end, and described transmission data terminal comprises transmission data input pin and transmission data output end;
Described microprocessor 1 for having the microprocessing unit of data processing and memory function, described microprocessor 1 for the treatment of with store the data that send by described FPDP 2 and receive.Described FPDP 2 is for receiving the extraneous data sent and the data sending the transmission of described node connection chip needs.Described FPDP 2 comprises switch unit 21, receiving element 22 and transmitting element 23, described switch unit 21 under the control of described microprocessor 1, control described receiving element 22 and described transmitting element 23 effective, namely in different situations, described FPDP 2 is for receiving the extraneous data sent or the data connecting the transmission of chip needs for sending described node.In embodiments of the present invention, the so-called external world refers to and carries out data communication between first node connection chip 01 and Section Point connection chip 02.
With reference to Fig. 3, Figure 3 shows that node of the present invention connects chip communication circuit preferred embodiment syndeton schematic diagram.The selecting side of first node connection chip 01 described in the Microprocessor S3C44B0X of described first node connection chip 01 is connected chip 01 power output end with described first node connects, it is master chip that described first node connects chip 01, and the FPDP transmitting element that described first node connects chip 01 is effective; Described in the Microprocessor S3C44B0X of described Section Point connection chip 02, the selecting side of Section Point connection chip 02 be connected the reception data of chip 02 with described Section Point is held and is connected, it is from chip that described Section Point connects chip 02, and the FPDP receiving element that described Section Point connects chip 02 is effective.Be necessary to illustrate, also first node can be connected chip by same mode and be set to from chip, Section Point is connected chip be set to master chip.
The embodiment of the present invention connect the transmitting element of microprocessor controls FPDP of chip by node or receiving element effective, thus first node is connected chip and be connected chip with Section Point and be set to master chip respectively and from chip, data communication link is provided for neighbor node connects chip, connect chip data communicating circuit by node and transmit detailed node connection chip information, for meshed network Quick is for detailed nodal information.
Be connected chip 02 with Section Point with reference to first node connection chip 01 in Fig. 3, Fig. 3 and embody node of the present invention connection chip second preferred embodiment electrical block diagram.Wherein in an embodiment, described receiving element 22 and described switch unit 21 are connected by receiving input port and receiving output port signal, described receiving element 22 and described microprocessor 1 by described power input, receive data terminal and end signal is connected with receiving data;
Described transmitting element 23 and described switch unit 21 are connected by sending input port and sending output port signal, described transmitting element 23 and described microprocessor 1 by described power output end, send data terminal, with sending data end signal be connected;
Described switch unit 21 is connected by selecting side signal with described microprocessor 1, and described microprocessor 1 controls described switch unit 21 by described selecting side and is communicated with described receiving element 22, or controls described switch unit 21 and be communicated with described transmitting element 23; Described switch unit 21 carries out data communication by described signal input part and described signal output part and the external world.
The process that node connection chip of the present invention transmits and receive data is as follows: when described node connects chip needs to neighbor node transmission data, described microprocessor 1 controls described switch unit 21 by described selecting side and is communicated with described transmitting element 23, data by described transmission data terminal via described transmitting element 23 transmission input port and send output port, signal output part finally by switch unit sends, and completes the transmission of data.Described power output end and described transmission data ground end are used for providing power supply for described transmitting element.When described node connects chip needs from neighbor node reception data, described microprocessor 1 controls described switch unit 21 by described selecting side and is communicated with the signal input part of data via described switch unit 21 with described receiving element 22, and the reception input port that switch unit 21 is connected with described receiving element 22, and the reception data terminal that described receiving element 22 connects transfers to described microprocessor 1, completes the reception of data.
With reference to Fig. 4, Figure 4 shows that node of the present invention connects chip communication circuit preferred embodiment local circuit structural representation.As shown in Figure 4, with middle Line for separation, in figure, Tranceiver is the transmitting element that first node of the present invention connects chip, it is positioned at left side in this schematic diagram, in figure, Receiver is the receiving element that Section Point of the present invention connects chip, if it is positioned at right side in this schematic diagram, identical with Receiver label during the signal end of setting forth in Tranceiver follow-up, then distinguish description with left side and right side.In the diagram, the power output end (Power output) of described first node connection chip and transmission data ground are held between (left side) GND and are arranged the first electric capacity C1, transmission input port (left side) In (-) of described first node connection chip and transmission data ground are held between (left side) GND and are arranged the first resistance R1, between transmission data output end (left side) the Data output of described first node connection chip and transmission output port (left side) Out (+), the first phase inverter is set, combined by switching tube Q2 and Q3 in the diagram and form a phase inverter, namely when transmission data output end (left side) Data output is high level, sending output port (left side) Out (+) is low level, data can be reduced by the phase inverter of switching tube composite design to disturb, when transmission data input pin (left side) Data output is high level, Q2 opens, sending output port (left side) Out (+) is just low level, vice versa.Simultaneously, connect between transmission data input pin (left side) the Data input of chip and transmission input port (left side) In (-) at described first node and the first switching tube Q1 is set, when transmission data input pin (left side) Data Input is high level, switching tube Q1 opens, just send data to the In (-) in left side, reduce data interference; the power input Power Input of described Section Point connection chip and reception data ground are held between (right side) GND and are arranged the second electric capacity C2, reception input port (right side) In (+) of described Section Point connection chip and reception data ground are held between (right side) GND and are arranged the second resistance R2, described second resistance R2 connects with described second electric capacity C2, between reception data output end (right side) the Data Output of described Section Point connection chip and reception output port (right side) Out (-), the second phase inverter is set, combined by switching tube Q4 and Q5 in the diagram and form a phase inverter, namely when receiving output port (right side) Out (-) for high level, receiving data output end (right side) Data output is low level, data can be reduced by the phase inverter of switching tube composite design to disturb, when opening for Q5 during high level when reception output port (right side) Out (-), receiving data output end (right side) Data output is just low level, vice versa.Between reception data input pin (right side) the Data input of described Section Point connection chip and reception input port (right side) In (+), second switch pipe Q6 is set, when reception data input pin (right side) Data input is high level, switching tube Q6 opens, just send data to the In (+) on right side, reduce data interference.
Merely depict node of the present invention at this and connect chip communication circuit preferred embodiment local circuit structural representation and principle of work thereof, when this area understands this local circuit structural representation and principle of work thereof, the any improvement made this is inventive concept of the present invention, does not enumerate at this.
The embodiment of the present invention describes the principle of work of node connection chip data communicating circuit by preferred embodiment local circuit structural representation, process of data communication is succinct and can reduce signal disturbing, improves the work efficiency that node connects chip data communicating circuit.
For achieving the above object, present invention also offers a kind of node and connect the chip data means of communication.
With reference to Fig. 5, Figure 5 shows that node of the present invention connects chip data means of communication preferred embodiment schematic flow sheet.Described node connects the chip data means of communication and comprises the steps:
S1: the selecting side of first node connection chip described in the Microprocessor S3C44B0X of first node connection chip is connected chip power output end with described first node connects, arranging described first node connection chip is master chip, and the transmitting element that described first node connects chip data port is effective;
S2: the selecting side of Section Point connection chip described in the Microprocessor S3C44B0X of Section Point connection chip be connected the reception data of chip with described Section Point is held and connected, arranging described Section Point connection chip is from chip, and the receiving element that described Section Point connects chip data port is effective;
S3: the FPDP of described first node connection chip is connected the dataport data communication of chip with described Section Point.
Shown in composition graphs 3, the process that node connection chip of the present invention and other nodes are connected chip data communication is as follows: when described node connects chip needs to other nodes connection chip transmission data, the microprocessor 1 of described node connection chip controls described switch unit 21 by described selecting side and is communicated with described transmitting element 23, data by described transmission data terminal via described transmitting element 23 transmission input port and send output port, signal output part finally by switch unit sends, and completes the transmission of data.Described power output end and described transmission data ground end are used for providing power supply for described transmitting element.When described node connects chip needs from neighbor node reception data, described microprocessor 1 controls described switch unit 21 by described selecting side and is communicated with the signal input part of data via described switch unit 21 with described receiving element 22, and the reception input port that switch unit 21 is connected with described receiving element 22, and the reception data terminal that described receiving element 22 connects transfers to described microprocessor 1, completes the reception of data.
The embodiment of the present invention connect the transmitting element of microprocessor controls FPDP of chip by node or receiving element effective, thus first node is connected chip and be connected chip with Section Point and be set to master chip respectively and from chip, data communication link is provided for neighbor node connects chip, connect chip data communicating circuit by node and transmit detailed node connection chip information, for meshed network Quick is for detailed nodal information.
Particularly, wherein in an embodiment, described step S3 comprises:
S31: the FPDP that the FPDP that described first node connects chip connects chip to described Section Point sends data, the data that the FPDP that the FPDP that described Section Point connects chip receives described first node connection chip sends;
Further, the local circuit structural representation shown in composition graphs 4, described step S31 comprises:
S311: the microprocessor controls transmission data output end that first node connects chip is connected with transmission data ground end signal;
Particularly, shown in composition graphs 4, the microprocessor controls that first node connects chip sends data output end (left side) Data output and holds (left side) GND signal to be connected with sending data, namely sending data output end (left side) Data output is low level, because described first node connects between the transmission data output end (Data output) of chip and transmission output port (left side) Out (+), the first phase inverter is set, combined by switching tube Q2 and Q3 in the diagram and form a phase inverter, therefore, sending output port (left side) Out (+) is high level.
S312: first node connects the power output end of chip via the first electric capacity, the second electric capacity, the first resistance and the second resistance, is the first electric capacity and the second capacitor charging;
Particularly, when sending output port (left side) Out (+) for high level, first node connects the power output end Power output of chip via the first electric capacity C1, the second electric capacity C2, the first resistance R1 and the second resistance R2, is that the first electric capacity C1 and the second electric capacity C2 charge.This process can be understood as first node, and to connect chip be that Section Point connects chip and sends the process of data and also can be understood as first node and connect chip for Section Point and connect the process that chip provides power supply;
S313: after charging terminates, the data that first node connects chip are sent to through the transmitting element that first node connects chip data port the receiving element that Section Point connects chip data port;
Particularly, when the first electric capacity C1 and the second electric capacity C2 reach capacity voltage time, the data that first node connects chip are sent to through the transmitting element Tanceiver that first node connects chip data port the receiving element Receiver that Section Point connects chip data port.
S314: the microprocessor controls transmission data output end that first node connects chip is connected with power output end signal;
Particularly, microprocessor controls transmission data output end (left side) the Data output that first node connects chip is connected with power output end (Power output) signal, namely sending data output end (left side) Data output is high level, because described first node connects between the transmission data output end (Data output) of chip and transmission output port (left side) Out (+), the first phase inverter is set, combined by switching tube Q2 and Q3 in the diagram and form a phase inverter, namely when sending data output end (Data output) for high level, sending output port (left side) Out (+) is low level, data can be reduced by the phase inverter of switching tube composite design to disturb, namely when transmission data input pin (Data output) is opened for Q2 during high level, sending output port (left side) Out (+) is just low level.
S315: the second electric capacity is by the second conductive discharge, and second switch management and control Section Point connects the receiving element Received signal strength of chip data port.
Particularly, when sending output port (left side) Out (+) for low level, second electric capacity C2 is discharged by the second resistance R2, second switch pipe Q6 opens, and controls (right side) Data input Received signal strength that Section Point connects the receiving element of chip data port.So far the FPDP transmission data of FPDP to described Section Point connection chip that described first node connects chip are completed, the data that the FPDP that the FPDP that described Section Point connects chip receives described first node connection chip sends.
Wherein in an embodiment, described step S3 also comprises:
S32: the FPDP that the FPDP that described Section Point connects chip connects chip to described first node sends data, the data that the FPDP that the FPDP that first node connects chip receives described Section Point connection chip sends.
Further, wherein in an embodiment, described step S32 comprises:
S321: the microprocessor controls reception data output end that Section Point connects chip is connected with reception data ground end signal;
Particularly, shown in composition graphs 4, the microprocessor controls that Section Point connects chip receives data output end (right side) Data output and holds (right side) GND signal to be connected with receiving data, namely receiving data output end (right side) Data output is low level, because described first node connects between the reception data output end (Data output) of chip and reception output port (right side) Out (+), the first phase inverter is set, combined by switching tube Q4 and Q5 in the diagram and form a phase inverter, therefore, receiving output port (right side) Out (+) is high level.
S322: Section Point connects the power input of chip via the first electric capacity, the second electric capacity, the first resistance and the second resistance, is the first electric capacity and the second capacitor charging;
Particularly, when receiving output port (right side) Out (+) for high level, Section Point connects the power input Power input of chip via the first electric capacity C1, the second electric capacity C2, the first resistance R1 and the second resistance R2, is that the first electric capacity C1 and the second electric capacity C2 charge.This process can be understood as Section Point, and to connect chip be that first node connects chip and receives the process of data and also can be understood as Section Point and connect chip for first node and connect the process that chip provides power supply;
S323: after charging terminates, the data that Section Point connects chip are sent to through the receiving element that Section Point connects chip data port the transmitting element that first node connects chip data port;
Particularly, when the first electric capacity C1 and the second electric capacity C2 reach capacity voltage time, the data that Section Point connects chip are sent to through the transmitting element Tanceiver that Section Point connects chip data port the receiving element Receiver that first node connects chip data port.
S324: the microprocessor controls reception data output end that Section Point connects chip is connected with power input signal;
Particularly, microprocessor controls reception data output end (right side) the Data output that Section Point connects chip is connected with power input (Power input) signal, namely receiving data output end (right side) Data output is high level, because described Section Point connects between the reception data output end (Data output) of chip and reception output port (right side) Out (+), the first phase inverter is set, combined by switching tube Q4 and Q5 in the diagram and form a phase inverter, namely when reception data output end (right side) Data output is high level, receiving output port (right side) Out (+) is low level, data can be reduced by the phase inverter of switching tube composite design to disturb, namely when reception data input pin (Data output) is opened for Q2 during high level, receiving output port (right side) Out (+) is just low level.
S325: the first electric capacity is by the first conductive discharge, and the first switch controlled first node connects the transmitting element Received signal strength of chip data port.
Particularly, when receiving output port (right side) Out (+) for low level, first electric capacity C1 is discharged by the first resistance R1, first switching tube Q1 opens, and controls (left side) Data input Received signal strength that first node connects the receiving element of chip data port.So far the FPDP transmission data of FPDP to described first node connection chip that described Section Point connects chip are completed, the data that the FPDP that the FPDP that described first node connects chip receives described Section Point connection chip sends.
These are only the preferred embodiments of the present invention; not thereby the scope of the claims of the present invention is limited; every utilize instructions of the present invention and accompanying drawing content to do equivalent structure or equivalent flow process conversion; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.
Claims (7)
1. a node connects chip communication circuit, it is characterized in that, described node connection chip communication circuit comprises first node connection chip and is connected chip with Section Point, and described first node connection chip is connected chip signal and connects and carry out data communication with described Section Point; Described node connects the FPDP that chip comprises microprocessor and is connected with described microprocessor signals, described FPDP comprises switch unit, receiving element and transmitting element, described FPDP and described microprocessor by power input, receive data terminal, receive data ground hold, selecting side, power output end, transmission data terminal, send data end signal be connected; Described reception data terminal comprises reception data input pin and receives data output end, and described transmission data terminal comprises transmission data input pin and transmission data output end;
The selecting side of first node connection chip described in the Microprocessor S3C44B0X of described first node connection chip is connected chip power output end with described first node connects, it is master chip that described first node connects chip, and the FPDP transmitting element that described first node connects chip is effective; Described in the Microprocessor S3C44B0X of described Section Point connection chip, the selecting side of Section Point connection chip be connected the reception data of chip with described Section Point is held and is connected, it is from chip that described Section Point connects chip, and the FPDP receiving element that described Section Point connects chip is effective.
2. node as claimed in claim 1 connects chip communication circuit, it is characterized in that, described receiving element and described switch unit are connected by receiving input port and receiving output port signal, between described receiving element with described microprocessor by described power input, receive data terminal and end signal is connected with receiving data;
Described transmitting element and described switch unit are connected by sending input port and sending output port signal, between described transmitting element with described microprocessor by described power output end, send data terminal, with sending data end signal be connected;
Described switch unit is connected by selecting side signal with described microprocessor, and described processor controls described switch unit by described selecting side and is communicated with described receiving element, or controls described switch unit and be communicated with described transmitting element; Described switch unit carries out data communication by described signal input part and described signal output part and the external world.
3. node as claimed in claim 2 connects chip communication circuit, it is characterized in that, the power output end of described first node connection chip and transmission data ground arrange the first electric capacity between holding, the transmission input port of described first node connection chip and transmission data ground arrange the first resistance between holding, between the transmission data output end of described first node connection chip and transmission output port, the first phase inverter is set, between the transmission data input pin of described first node connection chip and transmission input port, the first switching tube is set; The power input of described Section Point connection chip and reception data ground arrange the second electric capacity between holding, the reception input port of described Section Point connection chip and reception data ground arrange the second resistance between holding, between the reception data output end of described Section Point connection chip and reception output port, the second phase inverter is set, between the reception data input pin of described Section Point connection chip and reception input port, second switch pipe is set.
4. node connects chip data means of communication, it is characterized in that, described node connects the chip data means of communication and comprises the steps:
S1: the selecting side of first node connection chip described in the Microprocessor S3C44B0X of first node connection chip is connected chip power output end with described first node connects, arranging described first node connection chip is master chip, and the transmitting element that described first node connects chip data port is effective;
S2: the selecting side of Section Point connection chip described in the Microprocessor S3C44B0X of Section Point connection chip be connected the reception data of chip with described Section Point is held and connected, arranging described Section Point connection chip is from chip, and the receiving element that described Section Point connects chip data port is effective;
S3: the FPDP of described first node connection chip is connected the dataport data communication of chip with described Section Point.
5. node as claimed in claim 4 connects the chip data means of communication, and it is characterized in that, described step S3 comprises:
S31: the FPDP that the FPDP that described first node connects chip connects chip to described Section Point sends data, the data that the FPDP that the FPDP that described Section Point connects chip receives described first node connection chip sends;
S32: the FPDP that the FPDP that described Section Point connects chip connects chip to described first node sends data, the data that the FPDP that the FPDP that first node connects chip receives described Section Point connection chip sends.
6. node as claimed in claim 5 connects the chip data means of communication, and it is characterized in that, described step S31 comprises:
S311: the microprocessor controls transmission data output end that first node connects chip is connected with transmission data ground end signal;
S312: first node connects the power output end of chip via the first electric capacity, the second electric capacity, the first resistance and the second resistance, is the first electric capacity and the second capacitor charging;
S313: after charging terminates, the data that first node connects chip are sent to through the transmitting element that first node connects chip data port the receiving element that Section Point connects chip data port;
S314: the microprocessor controls transmission data output end that first node connects chip is connected with power output end signal;
S315: the second electric capacity is by the second conductive discharge, and second switch management and control Section Point connects the receiving element Received signal strength of chip data port.
7. the node as described in claim 5 or 6 connects the chip data means of communication, and it is characterized in that, described step S32 comprises:
S321: the microprocessor controls reception data output end that Section Point connects chip is connected with reception data ground end signal;
S322: Section Point connects the power input of chip via the first electric capacity, the second electric capacity, the first resistance and the second resistance, is the first electric capacity and the second capacitor charging;
S323: after charging terminates, the data that Section Point connects chip are sent to through the receiving element that Section Point connects chip data port the transmitting element that first node connects chip data port;
S324: the microprocessor controls reception data output end that Section Point connects chip is connected with power input signal;
S325: the first electric capacity is by the first conductive discharge, and the first switch controlled first node connects the transmitting element Received signal strength of chip data port.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510158279.0A CN104899172B (en) | 2015-04-03 | 2015-04-03 | Node connects the chip data means of communication |
| PCT/CN2015/078559 WO2016155085A1 (en) | 2015-04-03 | 2015-05-08 | Node connection chip communication circuit and method for data communication |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510158279.0A CN104899172B (en) | 2015-04-03 | 2015-04-03 | Node connects the chip data means of communication |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104899172A true CN104899172A (en) | 2015-09-09 |
| CN104899172B CN104899172B (en) | 2017-08-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510158279.0A Expired - Fee Related CN104899172B (en) | 2015-04-03 | 2015-04-03 | Node connects the chip data means of communication |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN104899172B (en) |
| WO (1) | WO2016155085A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016155440A1 (en) * | 2015-04-03 | 2016-10-06 | 深圳市共创百业科技开发有限公司 | Node connection chip communication circuit applicable in damage detection system |
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| CN1228641A (en) * | 1998-03-05 | 1999-09-15 | 三星电子株式会社 | Fan-out expansion circuit for RS-485 multidrop connection |
| US6463496B1 (en) * | 1998-07-27 | 2002-10-08 | Richard Wolf Gmbh | Interface for an I2C bus |
| US20070115954A1 (en) * | 2005-10-18 | 2007-05-24 | Sunplus Technology Co., Ltd. | Transmitting circuit, receiving circuit, interface switching module and interface switching method for SATA and SAS interfaces |
| CN203057158U (en) * | 2013-01-31 | 2013-07-10 | 珠海格力电器股份有限公司 | 485 communication circuit and communication system |
| CN204537428U (en) * | 2015-04-03 | 2015-08-05 | 深圳市易特科信息技术有限公司 | The node being applied to damage detection system connects chip communication circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103136145A (en) * | 2011-11-29 | 2013-06-05 | 中国航空工业集团公司第六三一研究所 | Interconnected chip and data transmission method between chips |
| CN102567587A (en) * | 2012-01-04 | 2012-07-11 | 青岛海信信芯科技有限公司 | FPGA (field programmable gate array) interconnection method and device utilizing same |
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2015
- 2015-04-03 CN CN201510158279.0A patent/CN104899172B/en not_active Expired - Fee Related
- 2015-05-08 WO PCT/CN2015/078559 patent/WO2016155085A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1228641A (en) * | 1998-03-05 | 1999-09-15 | 三星电子株式会社 | Fan-out expansion circuit for RS-485 multidrop connection |
| US6463496B1 (en) * | 1998-07-27 | 2002-10-08 | Richard Wolf Gmbh | Interface for an I2C bus |
| US20070115954A1 (en) * | 2005-10-18 | 2007-05-24 | Sunplus Technology Co., Ltd. | Transmitting circuit, receiving circuit, interface switching module and interface switching method for SATA and SAS interfaces |
| CN203057158U (en) * | 2013-01-31 | 2013-07-10 | 珠海格力电器股份有限公司 | 485 communication circuit and communication system |
| CN204537428U (en) * | 2015-04-03 | 2015-08-05 | 深圳市易特科信息技术有限公司 | The node being applied to damage detection system connects chip communication circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2016155440A1 (en) * | 2015-04-03 | 2016-10-06 | 深圳市共创百业科技开发有限公司 | Node connection chip communication circuit applicable in damage detection system |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2016155085A1 (en) | 2016-10-06 |
| CN104899172B (en) | 2017-08-22 |
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