CN108683577A - Interface conversion circuit and double nip device - Google Patents
Interface conversion circuit and double nip device Download PDFInfo
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- CN108683577A CN108683577A CN201810822538.9A CN201810822538A CN108683577A CN 108683577 A CN108683577 A CN 108683577A CN 201810822538 A CN201810822538 A CN 201810822538A CN 108683577 A CN108683577 A CN 108683577A
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40032—Details regarding a bus interface enhancer
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/02—Details
Abstract
The present invention provides a kind of interface conversion circuit and double nip devices, are related to the technical field of interface conversion, which includes：The first converting unit and the second converting unit being electrically connected to each other；It further include the control unit being electrically connected respectively with the first converting unit and the second converting unit；Wherein, the first converting unit includes 485 circuits of RS, and the second converting unit includes M BUS slave circuits.Control unit in the circuit can effectively reduce the case where data transmission fails caused by the second converting unit self-characteristic；In addition, using interface switching device of the microcontroller as processing unit in compared to the prior art, the circuit cost is relatively low, and the phenomenon that will not result in waste of resources.
Description
Technical field
The present invention relates to interface conversion technical fields, more particularly, to a kind of interface conversion circuit and double nip device.
Background technology
The managements through quantification such as water, electricity, gas, the heat in China adhere to different management organizations separately, correspond to different meter reading methods and
Management mode.Due to the difference of meter reading method, cause the communication interface corresponding to each management through quantification unit all different, therefore logical
Letter this kind of device of interface convertor comes into being.In table class industry, RS-485 and M-BUS are that two kinds of more universal communications connect
Mouthful.Currently used interface mounting means is to go to copy terminal device of the collection with M-BUS slave interfaces using M-BUS host interface
Data, RS-485 interfaces go to copy terminal device data of the collection with RS-485 interfaces.If scene is damaged due to RS-485 interfaces
Or when load capacity deficiency, using two different level and signaling interface, M-BUS host interface, which then can not be acquired directly, to be had
The terminal device data of RS-485 interfaces, so needing to carry out the level conversion between two kinds of interfaces.
Two kinds of varying levels are predominantly uniformly converted to identifiable Transistor-Transistor Logic level by existing level conversion mode, still
Since the signal transmission characteristics and echoing characteristic of M-BUS slaves itself can lead to data transmission fails.It is this to improve at present
Situation, it is proposed that the higher processing units of costs such as microcontroller are installed between level converter, but this method needs to compile
Program writing code is supported, however being only used for signal conversion between two kinds of interfaces can result in waste of resources again.
Invention content
In view of this, the purpose of the present invention is to provide a kind of interface conversion circuit and double nip device, can effectively subtract
Few the case where data send failure between interface not of the same race, while interface conversion cost can also be reduced.
In a first aspect, an embodiment of the present invention provides a kind of interface conversion circuit, which includes：Be electrically connected to each other
One converting unit and the second converting unit；It further include the control list being electrically connected respectively with the first converting unit and the second converting unit
Member；Wherein, the first converting unit includes RS-485 circuits, and the second converting unit includes M-BUS slave circuits；First converting unit
Input terminal be connected with first interface, for receive first interface transmission the first differential signal, by the first differential signal turn
It is changed to the first logic level signal, and the first logic level signal is sent respectively to the second converting unit and control unit；The
Two converting units are converted to current signal for receiving the first logic level signal, by the first logic level signal, and by electric current
Signal is sent to second interface；Wherein, the second converting unit is sent out when receiving the first logic level signal to the first converting unit
Send return path signal；Control unit is used for the return path signal that the second converting unit of one-way isolation is sent to the first converting unit.
With reference to first aspect, an embodiment of the present invention provides the first possible embodiments of first aspect, wherein the
Two converting units are additionally operable to receive the voltage signal that second interface is sent, and voltage signal is converted to the second logic level signal,
And the second logic level signal is sent respectively to the first converting unit and control unit.
The possible embodiment of with reference to first aspect the first, an embodiment of the present invention provides second of first aspect
Possible embodiment, wherein the second converting unit includes TSS721A chips, and is connected with TSS721A chips anti-interference
Circuit；TSS721A chips are used to the first logic level signal being converted to current signal, and voltage signal is converted to second
Logic level signal；The interference that anti-jamming circuit carries when being used to inhibit second interface to send voltage signal to TSS721A chips
Signal.
The possible embodiment of with reference to first aspect the first, an embodiment of the present invention provides the third of first aspect
Possible embodiment, wherein the first converting unit is additionally operable to receive the second logic level signal of the second converting unit transmission,
Second logic level signal is converted into the second differential signal, and the second differential signal is sent to first interface.
The third possible embodiment with reference to first aspect, an embodiment of the present invention provides the 4th kind of first aspect
Possible embodiment, wherein the first converting unit includes：BL3085A chips, and the overvoltage that is connected with BL3085A chips
Protect circuit；BL3085A chips be used for by the first differential signal be converted to the first logic level signal and by the second logic electricity
Ordinary mail number is converted to the second differential signal；Overvoltage crowbar is set between the first converting unit and first interface, for for
First converting unit provides overvoltage protection.
With reference to first aspect, an embodiment of the present invention provides the 5th kind of possible embodiments of first aspect, wherein the
It is connected with the first phase inverter and the second phase inverter between one converting unit and the second converting unit in turn；First phase inverter for pair
The first logic level signal that first converting unit is sent carries out first time reverse phase, obtains the electricity of the first logic after a reverse phase
Ordinary mail number, and the first logic level signal after a reverse phase is transferred to the second phase inverter；Second phase inverter is used for warp
The first logic level signal after reverse phase carries out second of reverse phase, obtains the letter of the first logic level after secondary reverse phase
Number, and the first logic level signal after secondary reverse phase is transferred to the second converting unit.
With reference to first aspect, an embodiment of the present invention provides the 6th kind of possible embodiments of first aspect, wherein control
Unit processed includes sequentially connected third phase inverter, the first delay circuit, the 4th phase inverter and the second delay circuit；Wherein,
The input terminal of three phase inverters connects with the second converting unit, the input terminal phase of the output end of third phase inverter and the first delay circuit
Connect, the output end of the first delay circuit connects with the first input end of the 4th phase inverter, the second input terminal of the 4th phase inverter with
Second converting unit connects, and the output end of the 4th phase inverter connects with the second delay circuit, the output end of the second delay circuit with
First converting unit connects.
The 6th kind of possible embodiment with reference to first aspect, an embodiment of the present invention provides the 7th kind of first aspect
Possible embodiment, wherein third phase inverter is NOT gate circuit structure；4th phase inverter is OR-NOT circuit structure.
The 7th kind of possible embodiment with reference to first aspect, an embodiment of the present invention provides the 8th kind of first aspect
Possible embodiment, wherein the structure of the first delay circuit and the second delay circuit is identical, and is RC delay circuits.
Second aspect, the embodiment of the present invention also provide a kind of double nip device, wherein the double nip device includes connecting successively
First interface, interface conversion circuit and the second interface connect；Wherein, interface conversion circuit is above-mentioned first aspect to first aspect
Any one of the 8th kind of possible embodiment interface conversion circuit.
Interface conversion circuit provided in an embodiment of the present invention, the first converting unit (including RS-485 circuits) receive first and connect
The first differential signal that mouth is sent, the second conversion is sent respectively to after the first differential signal is converted to the first logic level signal
Unit (including M-BUS slaves circuit) and control circuit, the second converting unit receives the first logic level signal, by the first logic
Level signal is sent to second interface after being converted to current signal, and control circuit controls the first converting unit single to the second conversion
The return path signal of the second converting unit transmission is not received when first transmission data.The conversion interface circuit when carrying out data transmission,
The conversion between unlike signal twice has been carried out, has realized that the data between distinct interface are sent.The present embodiment by be arranged control unit,
The return path signal that can be sent to the first converting unit with the second converting unit of one-way isolation, to effectively reduce because of M-BUS slaves
Caused by circuit own signal transmission characteristic the case where data transmission fails.In addition, using microcontroller in compared to the prior art
As the interface switching device of processing unit, the circuit cost is relatively low, and the phenomenon that will not result in waste of resources.
Other features and advantages of the present invention will illustrate in the following description, also, partly become from specification
It obtains it is clear that understand through the implementation of the invention.The purpose of the present invention and other advantages are in specification, claims
And specifically noted structure is realized and is obtained in attached drawing.
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, preferred embodiment cited below particularly, and coordinate
Appended attached drawing, is described in detail below.
Description of the drawings
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art are briefly described, it should be apparent that, in being described below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
It puts, other drawings may also be obtained based on these drawings.
Fig. 1 is a kind of structural schematic diagram of interface conversion circuit provided in an embodiment of the present invention；
Fig. 2 is a kind of circuit diagram of interface conversion circuit provided in an embodiment of the present invention；
Fig. 3 is a kind of structural schematic diagram of double nip device provided in an embodiment of the present invention；
Fig. 4 is the structural schematic diagram of another interface conversion circuit provided in an embodiment of the present invention；
Fig. 5 is a kind of operational process schematic diagram of interface conversion circuit provided in an embodiment of the present invention；
Fig. 6 is a kind of UART protocol sequence diagram provided in an embodiment of the present invention；
Fig. 7 is that a kind of working condition of interface conversion circuit provided in an embodiment of the present invention switches schematic diagram；
Fig. 8 is a kind of transmitting and receiving process schematic of interface conversion circuit provided in an embodiment of the present invention.
Specific implementation mode
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with attached drawing to the present invention
Technical solution be clearly and completely described, it is clear that described embodiments are some of the embodiments of the present invention, rather than
Whole embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not making creative work premise
Lower obtained every other embodiment, shall fall within the protection scope of the present invention.
It at present in technology, does not install and be easy to cause data transmission fails in the conversion circuit of processing unit, and be mounted with to locate
It manages in the conversion equipment of unit using microcontroller as processing unit, cost is higher and can result in waste of resources, and is based on this, this
A kind of interface conversion circuit and double nip device that inventive embodiments provide, can be in the communication between realizing two kinds of distinct interfaces
And cost is not high.
For ease of understanding the present embodiment, first to a kind of interface conversion circuit disclosed in the embodiment of the present invention into
Row is discussed in detail.
Embodiment one：
A kind of structural schematic diagram of interface conversion circuit 100 shown in Figure 1, including：First turn be electrically connected to each other
Change unit 102 and the second converting unit 104；Further include being electrically connected respectively with the first converting unit 102 and the second converting unit 104
Control unit 106；Wherein, the first converting unit 102 includes RS-485 circuits, and the second converting unit 104 includes M-BUS slaves
Circuit；The input terminal of first converting unit 102 is connected with first interface, the first difference letter for receiving first interface transmission
Number, the first differential signal is converted into the first logic level signal, and the first logic level signal is sent respectively to second turn
Change unit 104 and control unit 106；Second converting unit 104 is for receiving the first logic level signal, by the first logic level
Signal is converted to current signal, and current signal is sent to second interface；Wherein, the second converting unit 104 is receiving first
When logic level signal, return path signal is sent to the first converting unit 102；Second converting unit 104 is additionally operable to reception second and connects
Second interface voltage signal is converted to the second logic level signal, and the second logic level signal is sent out by the voltage signal of mouth
It send to the first converting unit 102 and control unit；First converting unit 102 is additionally operable to receive the transmission of the second converting unit 104
Second logic level signal is converted to the second differential signal, and the second differential signal is sent to by the second logic level signal
First interface.The passback letter that control unit 106 is sent for the second converting unit of one-way isolation 104 to the first converting unit 102
Number.
Wherein, logic level signal can be TTL signal, and TTL signal can be by the first converting unit and the second converting unit
Identification, and TTL signal follows UART communication protocols.
In one embodiment, first interface is RS-485 interfaces, and measuring terminal is sent out data by RS-485 buses
It send to RS-485 interfaces, wherein the mode of RS-485 bus transfer datas is differential mode, i.e. the metering that RS-485 is received is whole
End data is differential signal, therefore it is differential signal that the first converting unit, which receives,.Second interface is M-BUS host interface,
It is M-BUS slave chips in second converting unit, wherein M-BUS slaves chip has when carrying out data transmission with M-BUS hosts
There is following characteristic：For M-BUS slaves chip when receiving M-BUS hosts or M-BUS bus signals, judgement is M-BUS hosts
Or the voltage change in M-BUS buses, it is voltage modulated mode, i.e., the signal that M-BUS slaves chip receives is voltage signal；
And when M-BUS slaves chip is to M-BUS hosts or M-BUS bus transmission datas made always by changing the electric current in bus
Electric current on line generates variation, is current-modulation, i.e., what M-BUS slaves chip was sent is current signal.
In addition, control unit is used for the return path signal that the second converting unit of one-way isolation is sent to the first converting unit, it is
Another property based on M-BUS slave chips：Echo (ECHO) effect, in the internal conversion figure of M-BUS slave chips, when
After reception pin RX or RXI pin receives signal, it can be found the signal received by TX the and TXI pins of itself
It spreads out of, i.e., when M-BUS slave chips are actively sent, signal is only sent by pin TX and TXI；And work as M-BUS slaves
The signal and received signal for when chip receives signal by RX and RXI pins, sending, and sending again while receiving
Unanimously.For example, interface A is USB interface, interface B is the interface being arranged on M-BUS slaves, when host C transmits number by interface A
According to when, interface A, which is converted a signal into after TTL signal, to be sent to the RX pins of interface B, M-BUS slave and is receiving the same of TTL signal
When, and the TTL signal received is sent to interface A by TX pins, which can be sent back host C by interface A, such as
Fruit host C is not dealt with, and be may result in host C one and is directly received the identical data sent with it, causes error in data；If
Host C does not know that the signal is the data that M-BUS slaves are returned by ECHO effects, and host C, which receives the data, can then lead to data
Misjudgment.Control unit in the embodiment of the present invention is it is possible to prevente effectively from since M-BUS slaves chip itself ECHO effects are made
At data transmission fails.
For example, the first converting unit receives the data that measuring terminal is sent by RS-485 buses and RS-485 interfaces,
Middle data can be continuous data, and the first converting unit converts a signal into TTL signal, and the RO pins of the first converting unit will
TTL signal is sent respectively to the second converting unit and control unit, RX meetings while receiving TTL signal of the second converting unit
The TTL signal of passback is sent to the DI pins of the first converting unit by TX pins, an important function of control unit is exactly
The first converting unit is set to reject return path signal.Second converting unit passes through M-BUS after TTL signal is converted to current signal
Interface is sent to M-BUS hosts.
Interface conversion circuit provided in an embodiment of the present invention has been carried out when carrying out data transmission between unlike signal twice
Conversion realizes that the data between distinct interface are sent, while the control unit in the circuit can be effectively reduced because the second conversion is single
The situation of data transmission state disorder caused by first self-characteristic and mistake, reliable data pass between ensure that two kinds of interfaces
It is defeated.In addition, using interface switching device of the microcontroller as processing unit in compared to the prior art, which is only made by hardware
For processing unit, it is not necessarily to the support of program code, it is at low cost.
In practical applications, the second converting unit is additionally operable to receive the voltage signal that second interface is sent, by voltage signal
The second logic level signal is converted to, and the second logic level signal is sent respectively to the first converting unit and control unit.
First converting unit is additionally operable to receive the second logic level signal of the second converting unit transmission, and the second logic level signal is turned
It is changed to the second differential signal, and the second differential signal is sent to first interface.For example, M-BUS hosts are connect by M-BUS hosts
Mouth can send the voltage signal of continuous data to the second converting unit transmission data, wherein data for request measuring terminal, the
Voltage signal is converted to TTL signal by two converting units, and TTL signal is sent respectively to first by the RX pins of the second converting unit
The DI pins and control unit of converting unit, control unit control the first converting unit after receiving TTL signal, it are made to allow to connect
The Transistor-Transistor Logic level for receiving the transmission of the second converting unit, after TTL signal is converted to differential signal by the second converting unit, by differential signal
It is sent to measuring terminal by RS-485 interfaces and RS-485 buses.
Fig. 2 shows a kind of circuit diagrams of interface conversion unit of the embodiment of the present invention, wherein the second converting unit
Further include：TSS721A chips, and the anti-jamming circuit that is connected with TSS721A chips；TSS721A chips by first for patrolling
It collects level signal and is converted to current signal, and voltage signal is converted into the second logic level signal；Anti-jamming circuit is used for
The interference signal carried when second interface being inhibited to send voltage signal to TSS721A chips.
When specific implementation, the replacement of other chips, such as TSS521, BL15721A may be used in TSS721A chips.In reality
In, TSS721A chips may be implemented transceiving data, carry out Transistor-Transistor Logic level signal and voltage signal, Transistor-Transistor Logic level signal and electricity
Flowing the functions such as the conversion between signal, wherein BUSL1 and BUSL2 pins are used to receive the voltage signal of M-BUS interfaces transmission,
The signal that TX pins are used to be converted into Transistor-Transistor Logic level is sent, and RX pins are used to receive the TTL letters of the first converting unit transmission
Number.In addition, because voltage signal is influenced by bus length, therefore SC pins are grounded by capacitance ubC2, can play weakening
The influence of bus length, while can inhibit to transmit the interference signal carried when voltage signal.Wherein, VIO is to connect with power supply
Pin, GND is the pin to connect with ground.
First converting unit includes：BL3085A chips, and the overvoltage crowbar that is connected with BL3085A chips；
BL3085A chips are used to the first differential signal being converted to the first logic level signal and turn the second logic level signal
It is changed to the second differential signal；Overvoltage crowbar is set between the first converting unit and first interface, for being converted for first
Unit provides overvoltage protection.
When specific implementation, the replacement of other chips, such as MAX485 may be used in BL3085A chips.In practical applications,
BL3085A chips may be implemented transceiving data, carry out the conversion between Transistor-Transistor Logic level signal and differential signal, wherein A and B pins
Differential signal for receiving the transmission of RS-485 buses is additionally operable to send differential signal to RS-485 buses, and DI pins are for connecing
The Transistor-Transistor Logic level signal of the second converting unit transmission is received, RO pins are used to send Transistor-Transistor Logic level signal to the second converting unit, and VCC is
The pin to connect with power supply, GND are the pin to connect with ground.In addition, one end of overvoltage crowbar and A, B of BL3085A draw
Foot is connected, and the other end connects with RS-485 buses, plays the role of overvoltage protection to BL3085A.
It is connected with the first phase inverter and the second phase inverter between first converting unit and the second converting unit in turn；First is anti-
Phase device is used to carry out first time reverse phase to the first logic level signal that the first converting unit is sent, and obtaining will be after a reverse phase
The first logic level signal, and the first logic level signal after a reverse phase is transferred to the second phase inverter；Second is anti-
Phase device carries out second of reverse phase for the first logic level signal after a reverse phase, obtains first after secondary reverse phase and patrols
Level signal is collected, and the first logic level signal after secondary reverse phase is transferred to the second converting unit.
When specific implementation, the cores such as other logic gate chip, triode or metal-oxide-semiconductors may be used in nor gate 74HC02D chips
Piece replaces.In practical applications, by taking nor gate as an example, 3A, 3B, 3Y pin in 74HC02D chips constitute the first phase inverter,
Middle 3A and 3B pins link together, and 3A and 3B is input, and 3Y is output, is carried out to the first logic level signal anti-for the first time
Phase；4A, 4B, 4Y pin in 74HC02D chips constitutes the second phase inverter, and wherein 4A and 4B pins link together, 4A and 4B
For input, 4Y is output, carries out second of reverse phase to the logic level signal after a reverse phase, is exported to second turn by 4Y
Change the RX pins of unit.In addition, VCC is the pin to connect with power supply, GND is the pin to connect with ground.In practical applications, two
Secondary operated in anti-phase can play the role of signal shaping and improve output driving ability.
Control unit includes sequentially connected third phase inverter, the first delay circuit, the 4th phase inverter and the second delay electricity
Road；Wherein, the input terminal of third phase inverter connects with the first converting unit, the output end of third phase inverter and the first delay circuit
Input terminal connect, the output end of the first delay circuit connects with the first input end of the 4th phase inverter, the of the 4th phase inverter
Two input terminals connect with the second converting unit, and the output end of the 4th phase inverter connects with the second delay circuit, the second delay circuit
Output end connect with the first converting unit.
When specific implementation, third phase inverter can be provided with the 4th phase inverter by 74HC02D chips, wherein 74HC02D cores
2A, 2B, 2Y pin in piece constitutes third phase inverter, is NOT gate circuit structure, and wherein 2A and 2B is input, and 2Y is output；
1A, 1B, 1Y pin in 74HC02D chips constitutes the 4th phase inverter, is OR-NOT circuit structure, and wherein 1A is the 4th phase inverter
The second input terminal, 1B be the 4th phase inverter the second input terminal, 1Y be output；XR1, xC1, xR4, xaD6 constitute the first delay
Circuit, the effect of wherein diode xaD6 are to prevent reverse leakage current；XaR4, xaR7, xaC6, xaD7 constitute the second delay electricity
Road, the effect of wherein diode xaD7 are to prevent reverse phase leakage current.The structure of first delay circuit and the second delay circuit is identical,
And it is RC delay circuits.
The design of interface conversion circuit provided in an embodiment of the present invention is simple, makes second using simple logic control element
Converting unit is when receiving so that and the first converting unit rejects the return path signal that the second converting unit is sent, to
The ECHO effects for avoiding the second converting unit have evaded and have received data mode mistake and data perturbation caused by ECHO effects,
It ensure that reliable data transmission between two kinds of interfaces.
Embodiment two：
On the basis of the above embodiments, the present invention also provides a kind of double nip device, Fig. 3 shows a kind of double nip
The structural schematic diagram of device, the double nip device include sequentially connected first interface 302, interface conversion circuit 100 and second
Interface 304；Wherein, interface conversion circuit 100 is the interface conversion circuit in example one.
In one embodiment, first interface is RS-485 interfaces, and second interface is M-BUS host interface, and first connects
It is connected by RS-485 buses between mouth and interface conversion circuit, it is total by M-BUS between second interface and interface conversion circuit
Line connects.What is transmitted between first interface and interface conversion circuit is differential signal, and second interface is sent to interface conversion circuit
Be voltage signal, what interface conversion circuit was sent to second interface is current signal.
It is apparent to those skilled in the art that for convenience and simplicity of description, the double of foregoing description connect
Mouth device specific work process can refer to the corresponding process in previous embodiment, and details are not described herein.
Embodiment three：
On the basis of the above embodiments, an embodiment of the present invention provides a kind of another structures of interface conversion circuit to show
It is intended to, referring to Fig. 4, wherein M-BUS buses connect with the second converting unit, are handled comprising M-BUS slaves in the second converting unit
The RX pins of circuit, the second converting unit are connect with the second inverter output, the input terminal of the second phase inverter and the first reverse phase
The output end of device connects, the input terminal of the first phase inverter RO pins with the input terminal of control unit and the first converting unit respectively
Connect, the TX pins of the second converting unit connect respectively at the input terminal of control unit and the DI pins of the first converting unit, control
The output end of unit processed connects with the RE/DE pins of the first converting unit, includes RS-485 processing circuits in the first converting unit,
First converting unit connects with RS-485 buses.Inside control unit, the input terminal of third phase inverter is set as a points, output
End is set as b points and is connected with the first delay circuit；The first input end of the other end of first delay circuit and the 4th phase inverter
It is connected, is set as c points, the second input terminal of the 4th phase inverter connects with the TX pins of the second converting unit, is set as d points, the
The output end of four phase inverters is set as e points, and is connected with the second delay circuit；The other end of second delay circuit and the first conversion
The RE/DE pins of unit are connected, and are set as f points.
Based on this, present example provides a kind of operational process of interface conversion circuit, and one kind shown in Figure 5 connects
The flow chart of the application method of mouth conversion equipment, includes the following steps：
Step S502, the second converting unit receive second interface and send voltage signal, voltage signal is converted to second and is patrolled
Collect level signal.
In one embodiment, second interface uses M-BUS host interface, is M-BUS slaves in the second converting unit
TSS721A chips may be used in processing circuit, M-BUS slave processing circuits.Wherein, the first converting unit and the second converting unit
Between transmit is TTL logic levels, TTL logic levels belong to half-duplex operation mode, i.e., first send and receive afterwards, it then follows UART
Agreement, temporal order are followed successively by start bit, data bit, check bit sum stop position, wherein start bit is low level, stop position
For high level.TSS721A chips receive the voltage signal that M-BUS hosts are sent, and voltage signal is converted to TTL logic electricity
It is flat, wherein to be sent to the second converting unit by the voltage modulated mode of low and high level when voltage signal.
Step S504, the second logic level signal is sent respectively to the first converting unit to the second converting unit and control is single
Member.
In one embodiment, after voltage signal is converted to TTL signal by TSS721A chips, by TX pins export to
The d points of control unit and the DI pins of the first converting unit.According to UART protocol, TX pins first send one start bit, so
Transmission data position, check bit sum stop position successively afterwards.
Step S506, control unit control the first converting unit, and the first conversion unit is made to allow to receive the second converting unit
The second logic level signal sent.
Since the start bit is low level, i.e. d points are low level, since c points by default are low level, then e points
It for high level, after e points are high level, charges to the second delay circuit, f points are high level, at this time the first converting unit
The ends RE/DE are that the ends DE are effective, that is, the first converting unit is allowed to receive the TTL signal that the second converting unit is sent.
Step S508, the first converting unit receive the second logic level signal, and the second logic level signal is converted to the
Two differential signals, and the second differential signal is sent to first interface.
In one embodiment, BL3085A chips can provide between data transmit-receive and TTL signal and differential signal
Conversion function, after the first converting unit receives the second logic level, BL3085A is converted into the second differential signal
Afterwards, the second differential signal is sent to by RS-485 buses by A, B pin.
Step S510, the first differential signal that the first interface to be received such as first converting unit is sent.
Since the second delay circuit is electrically charged after start bit, become high level, and kept for a period of time, when TX pins
After the completion of sending signal to the DI pins of the first converting unit, i.e. TX sends stop position, and TX pins are high level, and second prolongs at this time
When circuit start to discharge, when the second delay circuit electric discharge after the completion of, f points just become low level.F points be low level after, first
Converting unit is in short wait state, i.e. the first converting unit waits for the first differential signal that first interface is sent.
Step S512, the first converting unit receive the first differential data that first interface is sent, and the first differential data is turned
It is changed to the first logic level DATA.
Wherein, the first differential signal is received by A, B pin of BL3085A chips, the conversion between line level of going forward side by side obtains
TTL signal.
Step S514, the first logic level signal is sent respectively to the second converting unit to the first converting unit and control is single
Member.
Specifically, TTL signal is sent to a points and the first reverse phase of control unit by BL3085A chips by RO pins
Device, the first phase inverter are sent to the second phase inverter after carrying out reverse phase to signal, the second phase inverter by received signal again
The RX pins of the second converting unit are sent to after carrying out reversely.Preferably, BL3085A chips transmission data equally follows UART associations
View, i.e., Transistor-Transistor Logic level signal is sent successively according to start bit, data bit, check bit sum stop position.
Step S516, control unit control the first converting unit, and the first converting unit is made to reject the second converting unit
The return path signal of transmission.
In view of start bit is low level, i.e. a points are low level, and b points are high level, and c points are high level, because in acquiescence shape
TX pins are high level under state, i.e. d points are high level, and the e points after the 4th phase inverter are low level to c points with d points, then f points are low
Level, the first converting unit RE pin low levels are effective, i.e., at this time the first converting unit by RO pins to the second converting unit
The first logic level signal is sent, while DI pins reject the return path signal that the second converting unit is sent.
Step S518, the second converting unit receive the first logic level signal that the first converting unit is sent, first are patrolled
It collects level signal and is converted to current signal, and current signal is sent to second interface.
After the TX pins of TSS721A chips receive the first logic level signal, by signal by way of current-modulation, i.e.,
First logic level signal is converted into current signal, current signal is sent to by M-BUS hosts by M-BUS buses.Wherein,
Current-modulation mode is transmitted signals in M-BUS buses and M-BUS hosts by changing the electric current in bus.Example
Such as, TSS721A chips consume 10mA electric currents to M-BUS buses if signal is logic 1, if signal is logical zero TSS721A cores
Piece consumes 5mA electric currents to M-BUS buses.
Step S520, the voltage signal that the second interface to be received such as second converting unit is sent.
BL3085A chips send start bit by RO pins to a points of control unit, and start bit is low level, through third
B points are high level after inverter, are charged to the first delay circuit, when RO pins send signal after the completion of, i.e. RO pins
Stop position is sent, RO pin levels are high level at this time, and after third inverter, the b points of control unit are low level, the
One delay circuit starts to discharge, and after the completion of electric discharge, the second converting unit is in short wait state, that is, waits for second interface again
It is secondary to send voltage signal to the second converting unit.
Example IV：
In one embodiment, the data between two kinds of interfaces are transmitted by Transistor-Transistor Logic level signal, wherein Transistor-Transistor Logic level
Signal follows UART protocol, an embodiment of the present invention provides a kind of sequence diagram of UART protocol, a kind of UART shown in Figure 6
Agreement sequence diagram.Specifically, the sequential of UART protocol includes spare bits, start bit, data bit, check bit sum stop position；Wherein,
Spare bits are high level, and start bit is low level, and stop position is high level.
It is low level feature that the embodiment of the present invention, which uses start bit in UART protocol, designs simple logic circuit conduct
Control unit makes the first converting unit and the second converting unit enter default conditions after reception has sent signal；Wherein, give tacit consent to
State is that the first converting unit and the second converting unit are in idle state, and first interface to be received is waited to be sent with second interface
The state of data.For ease of understanding, the working condition of interface conversion circuit shown in Figure 7 switches schematic diagram, wherein work
State includes：
First converting unit restores default conditions with the second converting unit.
First converting unit sends signal condition to the second converting unit：First converting unit receives what first interface was sent
Signal is simultaneously transmitted to the second converting unit, and the second converting unit receives the data and is transmitted to second interface.
Second converting unit sends signal condition to the first converting unit：Second converting unit receives what second interface was sent
Signal is simultaneously transmitted to the first converting unit, and the first converting unit receives the data and is transferred to first interface.
In one embodiment, when first interface sends signal to the first converting unit, interface conversion circuit is in
First converting unit sends signal condition to the second converting unit；After signal is sent completely, the first converting unit and the second conversion
Unit is in default conditions, and the first converting unit and the second converting unit wait for switch to subsequent work state at this time；When second
When interface sends signal to the second converting unit, interface conversion circuit, which is in the second converting unit and is sent to the first converting unit, to be believed
Number state；After signal is sent completely, the first converting unit and the second converting unit are restored again to default conditions.
Further, in the first converting unit when carrying out signal transmission with the second converting unit, the first converting unit is only
The signal of the second converting unit transmission can be received, the second converting unit of no normal direction sends signal；Or first converting unit can only
Signal is sent to the second converting unit, the signal of the second converting unit transmission can not be received.For ease of understanding, shown in Figure 8
Interface conversion circuit transmitting and receiving process schematic, transmitting and receiving process includes the following steps：
Step S802, default conditions；That is the first translation interface is in idle condition with the second translation interface.
The output end TX pins of step S804, the second converting unit send start bit to the first converting unit.
Step S806, the charging of the second delay circuit, the Enable Pin DE of the first converting unit are effective；Wherein, Enable Pin DE has
Effect, which shows as the first converting unit, can receive the signal of the second converting unit transmission, but the first converting unit is without normal direction second
Converting unit sends signal.
Step S808, the output end TX pins of the second converting unit to the first converting unit transmission data position, check bit, stop
Stop bit.
Step S810, the electric discharge of the second delay circuit, the Enable Pin DE failures of the first converting unit, Enable Pin RE are effective；Its
In, Enable Pin RE, which effectively shows as the first converting unit, to send signal, but the first converting unit to the second converting unit
The signal of the second converting unit transmission can not be received.
Step S812, default conditions.
The output end RO pins of step S814, the first converting unit send start bit to the second converting unit.
Step S816, the charging of the first delay circuit, the Enable Pin RE of the first converting unit are effective.
Step S818, the output end RO pins of the first converting unit to the second converting unit transmission data position, check bit, stop
Stop bit.
Step S820, the electric discharge of the first delay circuit；Wherein, restore default conditions after the electric discharge of the first delay circuit.
Interface conversion circuit provided in an embodiment of the present invention increases control unit on the basis of available circuit, when
RX pin transmission datas from the RO pins of one converting unit to the second converting unit when, control unit can control the first conversion list
The return path signal that member the second converting unit of rejection is sent, i.e. the second converting unit of one-way isolation are sent to the first converting unit
Return path signal ensure that so as to avoid status error and data perturbation caused by the ECHO effects of the second converting unit
Reliable data transmission between first interface and second interface.
It is apparent to those skilled in the art that for convenience and simplicity of description, the double of foregoing description connect
The specific work process of the circuit diagram of mouth device can refer to the corresponding process in previous embodiment, and details are not described herein.
It should be noted that in the description of invention unless specifically defined or limited otherwise, term " installation ", " phase
Even ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or be integrally connected；It can
Can also be electrical connection to be mechanical connection；It can be directly connected, can also indirectly connected through an intermediary, Ke Yishi
Connection inside two elements.For the ordinary skill in the art, above-mentioned term can be understood at this with concrete condition
Concrete meaning in invention.
Institute is described above, only specific implementation mode of the invention, but scope of protection of the present invention is not limited thereto, appoints
What those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, answer
It is included within the scope of the present invention.Therefore, protection scope of the present invention is answered described is with scope of the claims
It is accurate.
Claims (10)
1. a kind of interface conversion circuit, which is characterized in that including：The first converting unit being electrically connected to each other and the second conversion are single
Member；It further include the control unit being electrically connected respectively with first converting unit and second converting unit；Wherein, described
One converting unit includes RS-485 circuits, and second converting unit includes M-BUS slave circuits；
The input terminal of first converting unit is connected with first interface, and first for receiving the first interface transmission is poor
First differential signal is converted to the first logic level signal, and first logic level signal is distinguished by sub-signal
It is sent to second converting unit and described control unit；
Second converting unit is converted to first logic level signal for receiving first logic level signal
Current signal, and the current signal is sent to second interface；Wherein, second converting unit is patrolled in reception described first
When collecting level signal, return path signal is sent to first converting unit；
The return path signal that described control unit is sent for the second converting unit described in one-way isolation to first converting unit.
2. circuit according to claim 1, which is characterized in that second converting unit, which is additionally operable to receive described second, to be connect
The voltage signal is converted to the second logic level signal, and second logic level is believed by the voltage signal that mouth is sent
Number it is sent respectively to first converting unit and described control unit.
3. circuit according to claim 2, which is characterized in that second converting unit includes TSS721A chips, and
The anti-jamming circuit being connected with the TSS721A chips；
The TSS721A chips are used to first logic level signal being converted to the current signal, and by the electricity
Pressure signal is converted to second logic level signal；
It is carried when the anti-jamming circuit is for inhibiting the second interface to send the voltage signal to the TSS721A chips
Interference signal.
4. circuit according to claim 2, which is characterized in that first converting unit is additionally operable to receive described second turn
Second logic level signal for changing unit transmission, the second differential signal is converted to by second logic level signal, and
Second differential signal is sent to the first interface.
5. circuit according to claim 4, which is characterized in that first converting unit includes：BL3085A chips, with
And the overvoltage crowbar being connected with the BL3085A chips；
The BL3085A chips are used to first differential signal is converted to first logic level signal and by institute
It states the second logic level signal and is converted to second differential signal；
The overvoltage crowbar is set between first converting unit and the first interface, for being described first turn
It changes unit and overvoltage protection is provided.
6. circuit according to claim 1, which is characterized in that first converting unit and second converting unit it
Between be connected with the first phase inverter and the second phase inverter in turn；
First phase inverter is used to carry out for the first time first logic level signal that first converting unit is sent
Reverse phase obtains the first logic level signal after a reverse phase, and first logic level after a reverse phase is believed
Number it is transferred to second phase inverter；
Second phase inverter is used for the first logic level signal to described after a reverse phase and carries out second of reverse phase, obtains
The first logic level signal after secondary reverse phase, and first logic level signal after secondary reverse phase is transferred to institute
State the second converting unit.
7. circuit according to claim 1, which is characterized in that described control unit includes sequentially connected third reverse phase
Device, the first delay circuit, the 4th phase inverter and the second delay circuit；
Wherein, the input terminal of the third phase inverter connects with second converting unit, the output end of the third phase inverter
Connect with the input terminal of first delay circuit, the output end of first delay circuit and the first of the 4th phase inverter
Input terminal connects, and the second input terminal of the 4th phase inverter connects with second converting unit, the 4th phase inverter
Output end connects with second delay circuit, and the output end of second delay circuit connects with first converting unit.
8. circuit according to claim 7, which is characterized in that the third phase inverter is NOT gate circuit structure；Described
Four phase inverters are OR-NOT circuit structure.
9. circuit according to claim 7, which is characterized in that first delay circuit and second delay circuit
Structure is identical, and is RC delay circuits.
10. a kind of double nip device, which is characterized in that the double nip device includes sequentially connected first interface, interface turn
Change circuit and second interface；Wherein, the interface conversion circuit is claim 1 to 9 any one of them interface conversion circuit.
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| CN112398716A (en) * | 2020-11-12 | 2021-02-23 | 深圳云顶智慧科技有限公司 | Low-cost MBUS host circuit |
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| CN113595581A (en) * | 2021-07-28 | 2021-11-02 | 深圳市永旭电气技术有限公司 | Safe receiving and transmitting state control method and circuit of half-duplex serial port communication circuit |
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