CN104899005B - A kind of random number harvester and crypto chip - Google Patents

A kind of random number harvester and crypto chip Download PDF

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Publication number
CN104899005B
CN104899005B CN201510330324.6A CN201510330324A CN104899005B CN 104899005 B CN104899005 B CN 104899005B CN 201510330324 A CN201510330324 A CN 201510330324A CN 104899005 B CN104899005 B CN 104899005B
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China
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random
random number
delayer
digital units
data
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CN201510330324.6A
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Chinese (zh)
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CN104899005A (en
Inventor
毛兴中
杨碧波
王海洋
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北京联想核芯科技有限公司
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Abstract

The embodiment of the present invention, which provides a kind of random number harvester and crypto chip, wherein random number harvester, to be included:The data for producing and exporting random data signals produce digital units;The clock for producing and exporting random clock signal produces digital units;Digital units are produced with the data and the clock produces digital units and is connected, when receiving the random clock signal, the corresponding random data signals in metastable state state are acquired according to the random clock signal, obtain the data acquisition digital units of random number.The present invention can reduce the difficulty of the IP design reuses in random number harvester, lifting design convenience.

Description

A kind of random number harvester and crypto chip

Technical field

The present invention relates to data acquisition technology field, and in particular to a kind of random number harvester and crypto chip

Background technology

Random number harvester is to refer to produce random number, and the device for being acquired random number, as random number is sent out Raw device etc.;The random number that random number harvester is exported, it can be used in the cryptographic algorithm of crypto chip as secret key;Cause This, random number harvester is module necessary to crypto chip, and the quality for the random number that random number harvester is exported is good The bad security performance for directly affecting crypto chip.

With the development of crypto chip, IP reuses a key property as crypto chip;But existing use mould Intend the random number harvester of circuit realiration when designing IP, the production technology of heavy dependence crypto chip;Only in code core When the production technology of piece is identical with the production technology of random number harvester, random number harvester just can be real in crypto chip Existing IP is reused;As can be seen that existing random number harvester is in terms of IP reuses, using more limiting to, and can not be in password General purpose I P is reused in chip.

The content of the invention

In view of this, the embodiment of the present invention provides a kind of random number harvester and crypto chip, existing random to solve Present in number harvesters in terms of IP reuses, the problem of using more limiting to.

To achieve the above object, the embodiment of the present invention provides following technical scheme:

A kind of random number harvester, including:

The data for producing and exporting random data signals produce digital units;

The clock for producing and exporting random clock signal produces digital units;

Digital units are produced with the data and the clock produces digital units and is connected, and are receiving the random clock letter Number when, the corresponding random data signals in metastable state state are acquired according to the random clock signal, obtain with The data acquisition digital units of machine number.

Wherein, the data produce digital units and included:

N number of the first delayer to connect of contacting, each first delayer outputting data signals;

First NAND gate, the first input pin of first NAND gate connect with the output pin of the delayer of n-th first, Second input pin of first NAND gate receives the enable signal of outside input;

The first phase inverter to connect with the output pin of first NAND gate and the input pin of first the first delayer, institute State the first phase inverter and export the random data signals.

Wherein, the delayer is follower, and N is odd number.

Wherein, the clock produces digital units and included:

First the second delayer to connect to m-th series winding;

The second delayer that M+1 connects to l-th series winding, each second delayer export clock signal;

Data selector, the output pin difference of input pin and M to M-i the second delayer of the data selector Connecting, the output pin of the data selector connects with M+1 the second delayers, wherein, one of the data selector Input pin corresponds to second delayer in the M to M-i the second delayers, 1 < M-i < M;

Second NAND gate, the first input pin of second NAND gate connect with the output pin of the delayer of l-th second, Second input pin of second NAND gate receives the enable signal of outside input;

The second phase inverter to connect with the output pin of second NAND gate and the input pin of first the second delayer, institute State the second phase inverter and export the random clock signal.

Wherein, the delayer is follower, and L is odd number.

Wherein, the clock produces digital units and also included:

Sequential sets circuit, and the sequential sets parameter of the circuit for the sequential of output adjustment clock signal;

Wherein, the input pin of the data selector receives the parameter, to be prolonged according to the parameter to connect second The clock signal of slow device output carries out sequential adjustment.

Wherein, the data acquisition digital units include:

According to the random clock signal received, the random data signals for being in metastable state state accordingly are latched, are obtained The trigger of random number.

Wherein, the trigger includes:

First latch and the second latch;

Wherein, the D interface of the first latch produces digital units with the data and connected, and G interface receives the clock production The random clock signal of the inverted of raw digital units output;

The D interface of second latch connects with the Q interfaces of first latch, and G interface receives the clock production The random clock signal of raw digital units output, the random number obtained by the output of Q interfaces.

The embodiment of the present invention also provides a kind of crypto chip, including at least one random number harvester described above.

Wherein, the quantity of the random number harvester is more than 1, and is connected in parallel between random number harvester;It is described Crypto chip also includes:

Connect with the random number harvester being connected in parallel, and export the XOR circuit of final random number.

Based on above-mentioned technical proposal, random number harvester provided in an embodiment of the present invention, including:Produce and export random The data of data-signal produce digital units;The clock for producing and exporting random clock signal produces digital units;With the number Be connected according to producing digital units and the clock and producing digital units, when receiving the random clock signal, according to it is described with Machine clock signal is acquired to the corresponding random data signals in metastable state state, obtains the data acquisition number of random number Word cell.The embodiment of the present invention uses the digital circuit collection of metastable state data, and analog circuit is used compared to existing The random number harvester of realization, the embodiment of the present invention use digital circuit random number harvester, can reduce with The difficulty of IP design reuses in machine number harvester, lifting design convenience, and the random number harvester provided can be Realize that IP is reused between the crypto chip of more various processes, the random number harvester provided is in terms of IP reuses Using relatively broad.

Brief description of the drawings

In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this The embodiment of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis The accompanying drawing of offer obtains other accompanying drawings.

Fig. 1 is the structural representation of random number harvester provided in an embodiment of the present invention;

Fig. 2 is the structural representation that data provided in an embodiment of the present invention produce digital units;

Fig. 3 is the structural representation that clock provided in an embodiment of the present invention produces digital units;

Fig. 4 is another structural representation that clock provided in an embodiment of the present invention produces digital units;

Fig. 5 is the structural representation of trigger provided in an embodiment of the present invention;

Fig. 6 is another structural representation of random number harvester provided in an embodiment of the present invention;

Fig. 7 is the structural representation of crypto chip provided in an embodiment of the present invention.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made Embodiment, belong to the scope of protection of the invention.

Fig. 1 is the structural representation of random number harvester provided in an embodiment of the present invention, and reference picture 1, the random number adopts Acquisition means can include:Data produce digital units 100, and clock produces digital units 200, data acquisition digital units 300;Its In, data acquisition digital units 300 produce digital units 100 with data respectively and clock produces digital units 200 and is connected;

In embodiments of the present invention, data produce digital units 100 and can be used for producing random data signals, and by caused by Random data signals are exported to data acquisition digital units 300;

Clock produces digital units 200 and can be used for producing random clock signal, and caused random clock signal is exported To data acquisition digital units 300;

Data acquisition digital units 300 can receive data and produce the random data signals that digital units 100 export, and clock Produce the random clock signal that digital units 200 export;Data acquisition odd number word cell 300 can receive random clock signal When, the corresponding random data signals in metastable state state are acquired according to the random clock signal received, so as to Obtain random number;

In embodiments of the present invention, data acquisition digital units 300 can control random data by random clock signal The collection of signal, so as to latch dwelling in the random data signals of metastable state state, obtain random number;

The random data signals of metastable state state refer to, can not reach in stipulated time section can acknowledgement state data letter Number, used by regarding the random data signals in metastable state state gathered as random number, random number collection can be achieved Device produces and gathers the function of random number.

As can be seen that the embodiment of the present invention is produced random data signals and (counted using digital units circuit realiration concussion ring Random data signals are produced according to digital units are produced);Using the random clock signal of digital units circuit realiration different delays Produce (i.e. clock produces digital units and produces random clock signal);And then use digital units circuit, according to generated when Clock signal, in metastable state, data acquisition is carried out to concussion ring, metastable random data signals is obtained, realizes to random number Collection (i.e. data acquisition digital units collection in metastable state state random data signals), with this reach using numeral electricity The purpose for the random number harvester that road is realized so that random number harvester is in terms of IP reuses using relatively broad;It is optional , the inherently uncertain state of metastable state random data signals, it may be possible to 1, it is also possible to 0.

Random number harvester provided in an embodiment of the present invention, including:Produce and export the data production of random data signals Raw digital units;The clock for producing and exporting random clock signal produces digital units;With the data produce digital units and The clock produces digital units and is connected, when receiving the random clock signal, according to the random clock signal to corresponding The random data signals in metastable state state be acquired, obtain the data acquisition digital units of random number.It is of the invention real Apply example and use the digital circuit collection of metastable state data, gathered compared to the existing random number realized using analog circuit Device, the embodiment of the present invention use the random number harvester of digital circuit, can reduced in random number harvester Difficulty, the lifting design convenience of IP design reuses, and the random number harvester provided can be in more different production works Realize that IP is reused between the crypto chip of skill, the random number harvester provided is in terms of IP reuses using relatively broad.

Fig. 2 shows that data provided in an embodiment of the present invention produce the structural representation of digital units 100, reference picture 2, number It can include according to digital units 100 are produced:N number of first delayer 110, the first NAND gate 120, the first phase inverter 130;

Wherein, N number of first delayer 110 is made up of first the first delayer 110 to the first delayer of n-th 110, figure Leftmost first delayer is first the first delayer in 2, and the first delayer of rightmost is the delayer of n-th first; In embodiments of the present invention, N number of series winding of first delayer 110 connects, and each exportable data-signal of first delayer;

First input pin of the first NAND gate 120 connects with the output pin of the first delayer of n-th 110, first with it is non- Second input pin of door 120 receives the enable signal of outside input;

Optionally, enable signal can be 0 or 1.

The input output pin with the first NAND gate 120, and first the first delayer 110 respectively of first phase inverter 130 Input pin be connected, the first phase inverter 130 is handled input signal, exportable random data signals.

Optionally, data shown in Fig. 2 are produced in digital units, and the first delayer can select follower to realize, and selected Follower quantity can be odd number, i.e. N is odd number.

Fig. 3 shows that clock provided in an embodiment of the present invention produces the structural representation of digital units 200, and reference picture 3 should Clock, which produces digital units 200, to be included:L the second delayers 210, data selector 220, the second NAND gate 230, second Phase inverter 240;

For ease of description, L the second delayers 210 can be made up of two parts, and a part is first the second delayer 210 To the second delayer of m-th 210, another part is M+1 the second delayers 210 to the second delayer of l-th 210;

Wherein, first to the second delayer of m-th 210 series winding connect, M+1 to the second delayer of l-th 210 contact phase Connect, each exportable clock signal of second delayer 210;

The input pin of data selector 220 connects respectively with the output pin of M to M-i the second delayers 210, data The output pin of selector 220 connects with M+1 the second extenders 210, wherein, an input pin pair of data selector 220 Answer second delayer in M to M-i the second delayers, 1 < M-i < M;

Optionally, M to M-i the second delayers 210 can be M to second the second delayer 210.

First input pin of the second NAND gate 230 connects with the output pin of the second delayer of l-th 210, second with it is non- Second input pin of door 230 receives the enable signal of external number;

Second phase inverter 240 and the output pin of the second NAND gate 230 and the input pin phase of first the second delayer 210 Connect, the second phase inverter 240 can be believed according to the input of the signal and first the second delayer 210 of the output of the second NAND gate 230 Number handled, so as to export random clock signal.

Optionally, clock shown in Fig. 3 is produced in digital units, and the second delayer can be follower, and follower quantity Can be odd number, i.e. L is odd number.

Optionally, Fig. 4 shows that clock provided in an embodiment of the present invention produces another alternative construction of digital units, knot Close shown in Fig. 3 and Fig. 4, clock, which produces digital units, to be included:Sequential sets circuit 250, and sequential sets circuit 250 can be defeated Go out to adjust the parameter of the sequential of clock signal, so that clock produces random clock signal caused by digital units adjustment Sequential;

Optionally, the input pin of data selector 220 can receive the parameter that sequential sets circuit 250 to export, with according to institute State the clock signal that parameter exports to the second delayer 220 to connect and carry out sequential adjustment;As shown in figure 4, sequential sets circuit 250 connect with the input pin of data selector 220, when data selector 220 can receive the adjustment that sequential setting circuit 250 exports The parameter of the sequential of clock signal;

In embodiments of the present invention, when how much the numerical value of the parameter determines that clock produces digital units work, really How many individual delayers are used;The difference of the delayer number used, by influence overall clock produce digital units delay when Between length, so as to influence the frequency that the clock finally realized produces digital units output random clock signal.

Optionally, sequential sets circuit to store and record the parameter of adjustment sequential, so as to need to adjust clock signal Sequential when export stored parameter;The parameter can be write in the production test link of crypto chip, be then subject to Keep;It can also be set dynamically when crypto chip works by the firmware (Firmware) inside crypto chip;

Specifically, nonvolatile memory can be selected, such as EEPROM, Flash, One Time Programmable unit (OTP), or The memory banks such as electrical fuse (eFuse) realize that sequential sets circuit;Accordingly, in the Wafer tests of crypto chip, it is possible to Correct suitable parameter is write direct in test process in above-mentioned memory bank, these parameters will not after memory bank power down Lose, can be directly using the parameter set in above-mentioned memory bank during subsequent cryptographic chip operation;

Optionally, register also can be selected and realizes that sequential sets circuit;But register is after a power failure, the number in register According to when can lose, therefore the parameter being configured, it is necessary to be initialized on each crypto chip after electricity, by firmware journey Sequence is by the parameter read-in register.

Optionally, in embodiments of the present invention, data acquisition digital units 300 can be realized by trigger, and trigger can root According to the random clock signal received, the random data signals for being in metastable state state accordingly are latched, so as to obtain random number;

Specifically, trigger can be barricaded as by two latch, for latching the random data signals during being in metastable state; Fig. 5 shows a kind of alternative construction of trigger provided in an embodiment of the present invention, reference picture 5, and trigger can include:First lock The latch 320 of storage 310 and second;

Wherein, the D interface of the first latch 310 produces digital units 100 with data and connected, and G interface receives clock and produced The random clock signal of the inverted that digital units 200 export;

The D interface of second latch 320 connects with the Q interfaces of the first latch 310, and G interface receives clock and produces numeral The random clock signal that unit 100 exports, the random number obtained by the output of Q interfaces.

Optionally, Fig. 6 shows another structure of random number harvester provided in an embodiment of the present invention, can together join According to.

It is worth noting that, in embodiments of the present invention, data produce digital units and once design completion, delay therein The number of device (the first delayer) is fixed, and the frequency that data generate in the course of work is fixed;But different pieces of information produces Because of the difference of delayer number in digital units, its data generation frequency is also different;

For clock produces digital units, clock produces digital units and once designs completion, delayer therein (the Two delayers) number be fixed, but in the course of work effectively participate in work delayer number be it is configurable, therefore The clock frequency that clock is produced in digital units is variable;

And the difference, the difference of number of unit component (cell) species with selection, clock produce digital units and produced The frequency of random clock signal is also different;When using identical unit component and identical number, to ensure final clock Produce the frequency of random clock signal caused by digital units and expectation is as far as possible consistent, in the design process of rear end, placement-and-routing It should be carried out by certain requirement, and make it that the delay parameter of the whole link of clock generation digital units is expectable;But for not Same unit component, because its delayer quantity differs, clock will be also caused to produce digital units and produce random clock signal Final frequency also differ;

Data acquisition digital units in specific works, can at the time of random data signals change, i.e., random number it is believed that When number being in metastable section, the random clock signal caused by clock produces digital units goes to sample corresponding random data Signal, so as to obtain the random data signals of uncertain, unpredictable data result, ensure output random number.

Optionally, when the embodiment of the present invention is being realized, data produce digital units can with clock produce digital units into To existing;And data produce digital units and produce digital units with clock, the delayer of odd number number can be used, to reduce electricity The electric leakage probability on road;

Further, the embodiment of the present invention can be set a plurality of data acquisition link, shown in a data acquisition link routing diagram 1 with Machine number harvester is formed, so as to connect XOR circuit after the parallel connection of a plurality of data acquisition link, by XOR circuit to each bar After the random number of data acquisition link output is handled, final random number is exported.

The embodiment of the present invention is the random number harvester using digital circuit;Based on this, the present invention can reduce Difficulty, the lifting design convenience of IP design reuses in random number harvester, and the random number harvester provided can Realize that IP is reused between the crypto chip of more various processes, the random number harvester provided is in IP reuse sides Face is using relatively broad.

The embodiment of the present invention is also provided with a kind of crypto chip, and the crypto chip can include at least one described above Random number harvester.

Crypto chip provided in an embodiment of the present invention has the following advantages that:

With digital circuit metastable state data acquisition, the reusability of convenient design;In different chip production manufacturers, no With under technique, IP reuse is very convenient, without redesigning;IP design can be reduced and verify expense (during simulation IP, every time Replacement procedure is required for redesign, again independent flow checking, then just dares to be used in crypto chip);Chip can be adjusted flexibly It is whole, per chips it is independently adjustable, even if deviation be present in production technology, can also after chip production is returned, in test process, Finely tune sampling time point, it is not necessary to modification design, regenerate.

Further, the embodiment of the present invention can provide quantity be more than 1 random number harvester, and random number harvester it Between be connected in parallel;On this basis, crypto chip is also set up:Connect with the random number harvester being connected in parallel, and export most The XOR circuit of whole random number;

Fig. 7 shows the structural representation of crypto chip provided in an embodiment of the present invention, and reference picture 7, the crypto chip can With including:

Multiple random number harvesters 1 being connected in parallel,

Connect with multiple random number harvesters 1 being connected in parallel, the random number of each random number harvester output is entered After row processing, the XOR circuit 2 of final random number is exported.

The foregoing description of the disclosed embodiments, professional and technical personnel in the field are enable to realize or using the present invention. A variety of modifications to these embodiments will be apparent for those skilled in the art, as defined herein General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one The most wide scope caused.

Claims (10)

  1. A kind of 1. random number harvester, it is characterised in that including:
    The data for producing and exporting random data signals produce digital units;
    The clock for producing and exporting random clock signal produces digital units;
    Digital units are produced with the data and the clock produces digital units and is connected, and are receiving the random clock signal When, the corresponding random data signals in metastable state state are acquired according to the random clock signal, obtained random Several data acquisition digital units.
  2. 2. random number harvester according to claim 1, it is characterised in that the data, which produce digital units, to be included:
    N number of the first delayer to connect of contacting, each first delayer outputting data signals;
    First NAND gate, the first input pin of first NAND gate connects with the output pin of the delayer of n-th first, described Second input pin of the first NAND gate receives the enable signal of outside input;
    The first phase inverter to connect with the output pin of first NAND gate and the input pin of first the first delayer, described One phase inverter exports the random data signals.
  3. 3. random number harvester according to claim 2, it is characterised in that the delayer is follower, and N is strange Number.
  4. 4. random number harvester according to claim 1, it is characterised in that the clock, which produces digital units, to be included:
    First the second delayer to connect to m-th series winding;
    The second delayer that M+1 connects to l-th series winding, each second delayer export clock signal;
    Data selector, the input pin of the data selector distinguish phase with the output pin of M to M-i the second delayers Connecing, the output pin of the data selector connects with the input pin of M+1 the second delayers, wherein, the data selector An input pin correspond to second delayer in the M to M-i the second delayers, 1 < M-i < M;
    Second NAND gate, the first input pin of second NAND gate connects with the output pin of the delayer of l-th second, described Second input pin of the second NAND gate receives the enable signal of outside input;
    The second phase inverter to connect with the output pin of second NAND gate and the input pin of first the second delayer, described Two phase inverters export the random clock signal.
  5. 5. random number harvester according to claim 4, it is characterised in that the delayer is follower, and L is strange Number.
  6. 6. random number harvester according to claim 4, it is characterised in that the clock produces digital units and also wrapped Include:
    Sequential sets circuit, and the sequential sets parameter of the circuit for the sequential of output adjustment clock signal;
    Wherein, the input pin of the data selector receives the parameter, with according to the parameter to the second delayer for connecting The clock signal of output carries out sequential adjustment.
  7. 7. according to the random number harvester described in claim any one of 1-6, it is characterised in that the data acquisition numeral is single Member includes:
    According to the random clock signal received, the random data signals for being in metastable state state accordingly are latched, are obtained random Several triggers.
  8. 8. random number harvester according to claim 7, it is characterised in that the trigger includes:
    First latch and the second latch;
    Wherein, the D interface of the first latch produces digital units with the data and connected, and G interface receives the clock and produces number The random clock signal of the inverted of word cell output;
    The D interface of second latch connects with the Q interfaces of first latch, and G interface receives the clock and produces number The random clock signal of word cell output, the random number obtained by the output of Q interfaces.
  9. 9. a kind of crypto chip, it is characterised in that including at least one random number collection as described in claim any one of 1-8 Device.
  10. 10. crypto chip according to claim 9, it is characterised in that the quantity of the random number harvester is more than 1, And it is connected in parallel between random number harvester;The crypto chip also includes:
    Connect with the random number harvester being connected in parallel, and export the XOR circuit of final random number.
CN201510330324.6A 2015-06-15 2015-06-15 A kind of random number harvester and crypto chip CN104899005B (en)

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