CN108962329B - Efuse controller, Efuse system and Efuse programming method - Google Patents
Efuse controller, Efuse system and Efuse programming method Download PDFInfo
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- CN108962329B CN108962329B CN201810814382.XA CN201810814382A CN108962329B CN 108962329 B CN108962329 B CN 108962329B CN 201810814382 A CN201810814382 A CN 201810814382A CN 108962329 B CN108962329 B CN 108962329B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
Abstract
The application discloses an Efuse controller, an Efuse system and an Efuse programming method, wherein the Efuse controller comprises the following components: the data shaping module is used for receiving the clock input signal at a first input end and receiving the data input signal at a second input end, and an output end of the data shaping module outputs and shapes the data input signal according to the clock input signal to generate a shaped output signal; the input end of the counter is used for receiving the clock input signal, and the output end of the counter is used for outputting the counting result of the clock input signal; a logic AND circuit, one of the two input terminals is used for receiving the clock input signal, and the other input terminal is used for receiving the shaping output signal; the output end of the logic AND gate circuit is used for connecting with the STROBE signal input end of the Efuse module; a decoding circuit, one of the two input terminals is used for receiving the counting result, and the other input terminal is used for receiving the shaping output signal; the output end of the decoding circuit is used for being connected with the data signal input end of the Efuse module. The implementation of the application can realize simple and effective Efuse burning.
Description
Technical Field
The application relates to the technical field of Efuse, in particular to an Efuse controller, an Efuse system and an Efuse programming method.
Background
The Efuse technology is widely applied to fine adjustment of internal parameters of chips in mass production, and stable, quick and simple Efuse burning can greatly improve the yield of chip mass production in mass production of large-scale chips.
The prior patent literature proposes various Efuse modules and burning technologies, such as CN106997782A, and provides an EFUSE burning method and a burning circuit, wherein a constant current source and an address vector are combined to generate a constant current pulse; correcting the EFUSE IP and determining the scanning current value of EFUSE bit in the full address range; and selecting the maximum value of the scanning current value as a constant current source setting value, performing the EFUSE for programming test, and downloading data from other EFUSEs. According to the application, the EFUSE is programmed by constant current pulse, and the EFUSE programming condition is controlled by the current vector, so that the condition consistency of the EFUSE is ensured no matter the length of the line, the condition of blowing the EFUSE in a bursting mode of the thermal effect in the past is avoided, and the EFUSE is fused by adopting an electromigration mode, so that the stability of the EFUSE in the programming process is improved, and the data retention of the EFUSE at high temperature is also improved. As another example, CN107369472a provides an Efuse module programming device and an application method thereof, where the Efuse module is disposed on the circuit board and includes a first port and a second port; the circuit board is provided with a first connecting hole and a second connecting hole; the first port of the Efuse module is connected with the first connecting hole through a first wire, and the second port of the Efuse module is connected with the second connecting hole through a second wire; the first wire and the second wire are respectively connected with the power supply unit; the first connecting hole can be provided with a first locking piece so as to disconnect the power supply unit from the first lead; the second connection hole may be inserted with a second locking member to disconnect the power supply unit from the second wire. As the wires of the Efuse module on the circuit board pass through the connecting holes, the clamp is designed to complete the test of different products, thereby greatly reducing the production cost and improving the test efficiency.
However, the above burning methods are complex, so a simple and effective Efuse burning method and system are needed.
Disclosure of Invention
In view of the above, the present application aims to provide an Efuse controller, an Efuse system, and an Efuse programming method, so as to implement simple and efficient Efuse programming.
Specifically, the present application provides an Efuse controller including: the data shaping module comprises a first input end, a second input end and an output end, wherein the first input end is used for receiving a clock input signal, the second input end is used for receiving a data input signal, and the output end of the data shaping module outputs and shapes the data input signal according to the clock input signal to generate a shaped output signal; the counter, the input end is used for receiving the clock input signal, the output end is used for outputting the result of counting the said clock input signal; the logic AND circuit comprises two input ends and an output end, wherein one of the two input ends is used for receiving a clock input signal, and the other input end is used for receiving the shaping output signal; the output end of the logic AND gate circuit is used for connecting with the STROBE signal input end of the Efuse module; the decoding circuit comprises two input ends and an output end, wherein one of the two input ends is used for receiving the counting result, and the other input end is used for receiving the shaping output signal; and the output end of the decoding circuit is used for being connected with the data signal input end of the Efuse module.
Further, the data shaping module is a primary trigger, and the primary trigger is used for generating a shaped output signal according to the shaping trigger of the data input signal at the initial rising edge of each period of the clock input signal.
Further, the primary flip-flop is specifically configured to generate a high-level shaped output signal when the data input signal is high at a start rising edge of each cycle of the clock input signal; when the data input signal is low, a low shaped output signal is generated.
Further, the Efuse controller further includes: and the input end of the delayer is connected with the output end of the logic AND gate circuit, and the output end of the delayer is used for being connected with the data signal input end of the Efuse module.
Further, the delay time of the delay device is 50ns.
Further, the Efuse controller further includes a reset signal input terminal, where the reset signal input terminal is configured to receive a reset signal, and the reset signal is active low.
Further, the counter is a counter of 0 to 15, when the reset signal is at a low level, the counting result of the counter is set to an identification value different from 0 to 15, and the counting result of the counter is set to the identification value at the next clock after each counting 15.
Specifically, the application also provides an Efuse system, which comprises an Efuse module, and the Efuse system further comprises the Efuse controller, wherein the Efuse controller is connected with the Efuse module.
Specifically, the application also provides an Efuse programming method, which comprises the following steps:
receiving a reset signal, a clock input signal and a data input signal respectively;
when the reset signal is in a non-valid state, the data input signal is shaped according to the clock input signal, a shaped output signal is generated, and a counting result of the clock input signal is generated;
performing logical AND operation on the clock input signal and the shaping output signal, and generating and outputting a STROBE signal of the Efuse module according to the result of the logical AND operation;
and decoding the shaped output signal according to the counting result to generate and output a data signal of the Efuse module.
Further, the step of shaping the data input signal according to the clock input signal, the step of generating a shaped output signal comprises:
generating a high-level shaped output signal when the data input signal is high at a start rising edge of each period of the clock input signal; when the data input signal is low, a low shaped output signal is generated.
Further, the step of generating and outputting a STROBE signal of the Efuse module according to the result of the logical and operation includes:
and delaying the result of the logical AND operation for a preset time to obtain a delayed signal which is used as a STROBE signal of the Efuse module.
Further, the counter is a counter of 0 to 15, when the reset signal is at a low level, the counting result of the counter is set to an identification value different from 0 to 15, and the counting result of the counter is set to the identification value at the next clock after each counting 15.
According to the Efuse controller, the Efuse system and the Efuse programming method, the data input signals are shaped according to the clock input signals to generate shaped output signals, and a counting result of the clock input signals is generated; further performing logical AND operation on the clock input signal and the shaping output signal, and generating and outputting a STROBE signal of the Efuse module according to the result of the logical AND operation; and decoding the shaping output signal according to the counting result, and generating and outputting a data signal of the Efuse module, so that the Efuse module can simply and effectively burn according to the STROBE signal and the data signal.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description, serve to explain the principles of the application. In the drawings, like reference numerals are used to identify like elements. The drawings, which are included in the description, illustrate some, but not all embodiments of the application. Other figures can be derived from these figures by one of ordinary skill in the art without undue effort.
Fig. 1 is a schematic structural diagram of an Efuse system according to an embodiment of the present application;
FIG. 2 is a timing chart of a 16bits Efuse programming control provided by an embodiment of the present application;
fig. 3 is a schematic flow chart of an Efuse programming method according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application. It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be arbitrarily combined with each other.
The reactive coordination control method and the reactive coordination control system for the direct-drive permanent magnet fan are explained in detail below with reference to the attached drawings.
Referring to fig. 1, an Efuse system provided by an embodiment of the present application includes an Efuse module and an Efuse controller, where the Efuse controller is connected to the Efuse module. Wherein, this Efuse controller includes:
the data shaping module comprises a first input end, a second input end and an output end, wherein the first input end is used for receiving a clock input signal, the second input end is used for receiving a data input signal, and the output end of the data shaping module outputs and shapes the data input signal according to the clock input signal to generate a shaped output signal;
the counter, the input end is used for receiving the clock input signal, the output end is used for outputting the result of counting the said clock input signal;
the logic AND circuit comprises two input ends and an output end, wherein one of the two input ends is used for receiving a clock input signal, and the other input end is used for receiving the shaping output signal; the output end of the logic AND gate circuit is used for connecting with the STROBE signal input end of the Efuse module;
the decoding circuit comprises two input ends and an output end, wherein one of the two input ends is used for receiving the counting result, and the other input end is used for receiving the shaping output signal; and the output end of the decoding circuit is used for being connected with the data signal input end of the Efuse module.
Preferably, the data shaping module is a primary flip-flop, and the primary flip-flop is configured to generate a shaped output signal according to the data input signal shaping trigger at a start rising edge of each period of the clock input signal.
Further preferably, the primary flip-flop is specifically configured to generate a high-level shaped output signal when the data input signal is high at a start rising edge of each cycle of the clock input signal; when the data input signal is low, a low shaped output signal is generated.
Specifically, the Efuse controller further includes: and the input end of the delayer is connected with the output end of the logic AND gate circuit, and the output end of the delayer is used for being connected with the data signal input end of the Efuse module. Specifically, the delay time of the delay device is 50ns.
In a specific operation, the Efuse controller further includes a reset signal input terminal, where the reset signal input terminal is configured to receive a reset signal, and the reset signal is valid at a low level. Specifically, the counter is a counter of 0 to 15, and when the reset signal is at a low level, the count result of the counter is set to an identification value different from 0 to 15, and the count result of the counter is set to the identification value at the next clock after each count 15.
The Efuse controller has the function of judging whether the data input signal Din needs to be burnt or not; high level: the Efuse needs to be programmed, low: no programming is required. The 16bits programming is directly controlled by counting the programming clock, an external high-frequency clock is not needed when the Efuse is programmed, only the high level of the current clock is needed to be used for controlling the bit programming signal of the Efuse, and in time sequence, the programming master control signal strobe_en of the Efuse is delayed for 50ns through an analog RC to generate a STROBE signal in accordance with the standard requirement of the Efuse.
FIG. 2 is a schematic diagram showing a recording timing control of the present application, rst_n is a reset signal; data_in is the Data to be burned; clk_in is an external clock signal that satisfies the programming timing. Firstly, data is Data to be burnt after passing through a primary trigger by Data shaping. The bit_cnt [4:0] is a counter of 0-15 according to clock setting, and is set to 0x1F when resetting, and 1 count is added only when the clock is burnt. After the burn-in, it is recommended to give one more clk_in as the end clock to reset the counter to 0x1F. The strobe_en directly takes the high level of clk_in, and is directly applied as a STROBE signal to the Efuse after being delayed by 50ns by the RC of the analog block. WL 0-WL 15 is used to select which bit of 16bits needs to be burned. The logic of WL [0] -WL [15] can be directly obtained by decoding and combining bit_cnt and data_in_q.
Referring to fig. 3, an embodiment of the present application provides an Efuse burning method, which is a method corresponding to the system shown in fig. 1, and the explanations of fig. 1 and fig. 2 can be applied to this embodiment. Specifically, the method comprises the following steps:
step 301: receiving a reset signal, a clock input signal and a data input signal respectively;
step 303: when the reset signal is in a non-valid state, the data input signal is shaped according to the clock input signal, a shaped output signal is generated, and a counting result of the clock input signal is generated;
step 305: performing logical AND operation on the clock input signal and the shaping output signal, and generating and outputting a STROBE signal of the Efuse module according to the result of the logical AND operation;
step 307: and decoding the shaped output signal according to the counting result to generate and output a data signal of the Efuse module.
Preferably, the step of shaping the data input signal in dependence on the clock input signal, the step of generating a shaped output signal comprises:
generating a high-level shaped output signal when the data input signal is high at a start rising edge of each period of the clock input signal; when the data input signal is low, a low shaped output signal is generated.
Preferably, the step of generating and outputting a STROBE signal of the Efuse module according to the result of the logical and operation includes:
and delaying the result of the logical AND operation for a preset time to obtain a delayed signal which is used as a STROBE signal of the Efuse module.
Preferably, the counter is a counter of 0 to 15, and when the reset signal is at a low level, the count result of the counter is set to an identification value different from 0 to 15, and the count result of the counter is set to the identification value at the next clock after each count 15.
The embodiment generates a shaped output signal by shaping the data input signal according to the clock input signal and generates a counting result of the clock input signal; further performing logical AND operation on the clock input signal and the shaping output signal, and generating and outputting a STROBE signal of the Efuse module according to the result of the logical AND operation;
and decoding the shaping output signal according to the counting result, and generating and outputting a data signal of the Efuse module, so that the Efuse module can simply and effectively burn according to the STROBE signal and the data signal.
It will be understood by those skilled in the art that all or part of the steps/units/modules implementing the above embodiments may be implemented by hardware associated with program instructions, and the above programs may be stored in a computer readable storage medium, which when executed, perform steps including corresponding steps in the units of the above embodiments; and the aforementioned storage medium includes: various media such as ROM, RAM, magnetic or optical disk may store program code.
While the foregoing is directed to embodiments of the present application, other and further details of the application may be had by the present application, it should be understood that the foregoing description is merely illustrative of the present application and that no limitations are intended to the scope of the application, except insofar as modifications, equivalents, improvements or modifications are within the spirit and principles of the application.
Claims (12)
1. An Efuse controller, comprising:
the data shaping module comprises a first input end, a second input end and an output end, wherein the first input end is used for receiving a clock input signal, the second input end is used for receiving a data input signal, and the output end of the data shaping module outputs and shapes the data input signal according to the clock input signal to generate a shaped output signal;
the counter, the input end is used for receiving the clock input signal, the output end is used for outputting the result of counting the said clock input signal;
the logic AND circuit comprises two input ends and an output end, wherein one of the two input ends is used for receiving a clock input signal, and the other input end is used for receiving the shaping output signal; the output end of the logic AND gate circuit is used for connecting with the STROBE signal input end of the Efuse module;
the decoding circuit comprises two input ends and an output end, wherein one of the two input ends is used for receiving the counting result, and the other input end is used for receiving the shaping output signal; and the output end of the decoding circuit is used for being connected with the data signal input end of the Efuse module.
2. The Efuse controller of claim 1 wherein the data shaping module is a primary flip-flop for generating a shaped output signal based on the data input signal shaping trigger at a beginning rising edge of each cycle of the clock input signal.
3. The Efuse controller of claim 2 wherein the primary flip-flop is specifically configured to generate a high-level shaped output signal when the data input signal is high at a beginning rising edge of each cycle of the clock input signal; when the data input signal is low, a low shaped output signal is generated.
4. An Efuse controller according to any one of claims 1 to 3 further comprising: and the input end of the delayer is connected with the output end of the logic AND gate circuit, and the output end of the delayer is used for being connected with the STROBE signal input end of the Efuse module.
5. The Efuse controller of claim 4 wherein the delay has a delay time length of 50ns.
6. The Efuse controller of claim 4 further comprising a reset signal input for receiving a reset signal, the reset signal being active low.
7. The Efuse controller according to claim 6, wherein the counter is a counter of 0 to 15, a count result of the counter is set to an identification value different from 0 to 15 when the reset signal is at a low level, and a count result of the counter is set to the identification value at a next clock after each count of 15.
8. An Efuse system comprising an Efuse module, wherein said Efuse system further comprises an Efuse controller according to any one of claims 1 to 7, said Efuse controller being connected to said Efuse module.
9. An Efuse programming method based on the Efuse system of claim 8, comprising:
receiving a reset signal, a clock input signal and a data input signal respectively;
when the reset signal is in a non-valid state, the data input signal is shaped according to the clock input signal, a shaped output signal is generated, and a counting result of the clock input signal is generated;
performing logical AND operation on the clock input signal and the shaping output signal, and generating and outputting a STROBE signal of the Efuse module according to the result of the logical AND operation;
and decoding the shaped output signal according to the counting result to generate and output a data signal of the Efuse module.
10. The Efuse programming method of claim 9, wherein the step of shaping the data input signal based on the clock input signal to generate a shaped output signal comprises:
generating a high-level shaped output signal when the data input signal is high at a start rising edge of each period of the clock input signal; when the data input signal is low, a low shaped output signal is generated.
11. The Efuse programming method according to any one of claims 9 or 10, wherein the step of generating and outputting a STROBE signal of the Efuse module according to a result of the logical and operation includes:
and delaying the result of the logical AND operation for a preset time to obtain a delayed signal which is used as a STROBE signal of the Efuse module.
12. The Efuse programming method of claim 11, wherein a counter is a counter of 0 to 15, a count result of the counter is set to an identification value different from 0 to 15 when the reset signal is at a low level, and a count result of the counter is set to the identification value at a next clock after each count of 15.
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| CN114203245B (en) * | 2022-02-18 | 2022-05-10 | 深圳市芯茂微电子有限公司 | eFuse control method and related assembly |
| CN117111857A (en) * | 2023-09-15 | 2023-11-24 | 上海合芯数字科技有限公司 | Method, device, equipment and storage medium for reading data information |
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