CN104899005A - Random number acquisition device and password chip - Google Patents
Random number acquisition device and password chip Download PDFInfo
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- CN104899005A CN104899005A CN201510330324.6A CN201510330324A CN104899005A CN 104899005 A CN104899005 A CN 104899005A CN 201510330324 A CN201510330324 A CN 201510330324A CN 104899005 A CN104899005 A CN 104899005A
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Abstract
The embodiment of the invention provides a random number acquisition device and a password chip, wherein the random number acquisition device comprises a digital signal generation unit for generating and outputting a random data signal, a digital clock generation unit for generating and outputting a random clock signal, and a digital data acquisition unit for acquiring a corresponding random data signal in a metastable state according to a random clock signal and obtaining the random number. According to the invention, the difficulty of IP reuse design in the random number acquisition device can be reduced, and the design convenience is improved.
Description
Technical field
The present invention relates to data acquisition technology field, be specifically related to a kind of random number harvester and crypto chip.
Background technology
Random number harvester refers to and can produce random number, and to the device that random number gathers, as randomizer etc.; The random number that random number harvester exports, can be used as secret key and use in the cryptographic algorithm of crypto chip; Therefore, random number harvester is the necessary module of crypto chip, and the quality of the random number that random number harvester exports directly affects the security performance of crypto chip.
Along with the development of crypto chip, IP reuses the key property becoming crypto chip; But the random number harvester that existing employing mimic channel realizes is when designing IP, the production technology of heavy dependence crypto chip; Only when the production technology of crypto chip is identical with the production technology of random number harvester, random number harvester just can realize IP and reuse in crypto chip; Can find out, existing random number harvester is in IP reuses, and application is comparatively limited to, and cannot reuse by general purpose I P in crypto chip.
Summary of the invention
In view of this, the embodiment of the present invention provides a kind of random number harvester and crypto chip, with solve existing for existing random number harvester in IP reuses, apply the problem of comparatively limiting to.
For achieving the above object, the embodiment of the present invention provides following technical scheme:
A kind of random number harvester, comprising:
Produce and export random data signals data produce digital units;
Produce and export the clock generating digital units of random clock signal;
Produce digital units with described data to be connected with described clock generating digital units, when receiving described random clock signal, according to described random clock signal, the random data signals being in metastable state state is accordingly gathered, obtain the data acquisition digital units of random number.
Wherein, described data generation digital units comprises:
The first delayer that N number of series winding connects, each first delayer outputting data signals;
First Sheffer stroke gate, the first input pin of described first Sheffer stroke gate connects with the output pin of N number of first delayer, and the second input pin of described first Sheffer stroke gate receives the enable signal of outside input;
The first phase inverter connected with the output pin of described first Sheffer stroke gate and the input pin of first the first delayer, described first phase inverter exports described random data signals.
Wherein, described delayer is follower, and N is odd number.
Wherein, described clock generating digital units comprises:
First to M the second delayer connected of contacting;
The second delayer that M+1 connects to L series winding, each second delayer clock signal;
Data selector, the input pin of described data selector connects respectively with the output pin of M to M-i the second delayer, the output pin of described data selector connects with M+1 the second delayer, wherein, second delayer in corresponding described M to M-i second delayer of an input pin of described data selector, 1 < M – i < M;
Second Sheffer stroke gate, the first input pin of described second Sheffer stroke gate connects with the output pin of L the second delayer, and the second input pin of described second Sheffer stroke gate receives the enable signal of outside input;
The second phase inverter connected with the output pin of described second Sheffer stroke gate and the input pin of first the second delayer, described second phase inverter exports described random clock signal.
Wherein, described delayer is follower, and L is odd number.
Wherein, described clock generating digital units also comprises:
Sequential arranges circuit, and described sequential arranges circuit for exporting the parameter of the sequential of adjustment clock signal;
Wherein, the input pin of described data selector receives described parameter, to carry out sequential adjustment according to described parameter to the clock signal that the second delayer connected exports.
Wherein, described data acquisition digital units comprises:
According to received random clock signal, latch the random data signals being in metastable state state accordingly, obtain the trigger of random number.
Wherein, described trigger comprises:
First latch and the second latch;
Wherein, D interface and the described data of the first latch produce digital units and connect, and G interface receives the random clock signal after the negate of described clock generating digital units output;
The D interface of described second latch connects with the Q interface of described first latch, and G interface receives the random clock signal that described clock generating digital units exports, and Q interface exports the random number obtained.
The embodiment of the present invention also provides a kind of crypto chip, comprises the random number harvester that at least one is described above.
Wherein, the quantity of described random number harvester is greater than 1, and is connected in parallel between random number harvester; Described crypto chip also comprises:
Connect with the random number harvester be connected in parallel, and export the XOR circuit of final random number.
Based on technique scheme, the random number harvester that the embodiment of the present invention provides, comprising: produce and export random data signals data produce digital units; Produce and export the clock generating digital units of random clock signal; Produce digital units with described data to be connected with described clock generating digital units, when receiving described random clock signal, according to described random clock signal, the random data signals being in metastable state state is accordingly gathered, obtain the data acquisition digital units of random number.The embodiment of the present invention adopts the digital circuit collection of metastable state data, compared to the random number harvester that existing employing mimic channel realizes, the embodiment of the present invention adopts the random number harvester of digital circuit, the difficulty of the IP design reuse in random number harvester can be reduced, promote design convenience, and the random number harvester provided can realize IP between the crypto chip of more various processes reuses, the random number harvester provided is applied comparatively extensive in IP reuses.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only embodiments of the invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to the accompanying drawing provided.
The structural representation of the random number harvester that Fig. 1 provides for the embodiment of the present invention;
The structural representation of the data generation digital units that Fig. 2 provides for the embodiment of the present invention;
The structural representation of the clock generating digital units that Fig. 3 provides for the embodiment of the present invention;
Another structural representation of the clock generating digital units that Fig. 4 provides for the embodiment of the present invention;
The structural representation of the trigger that Fig. 5 provides for the embodiment of the present invention;
Another structural representation of the random number harvester that Fig. 6 provides for the embodiment of the present invention;
The structural representation of the crypto chip that Fig. 7 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The structural representation of the random number harvester that Fig. 1 provides for the embodiment of the present invention, with reference to Fig. 1, this random number harvester can comprise: data produce digital units 100, clock generating digital units 200, data acquisition digital units 300; Wherein, data acquisition digital units 300 produces digital units 100 with data respectively and is connected with clock generating digital units 200;
In embodiments of the present invention, data produce digital units 100 and can be used for producing random data signals, and export the random data signals of generation to data acquisition digital units 300;
Clock generating digital units 200 can be used for producing random clock signal, and exports the random clock signal of generation to data acquisition digital units 300;
Data acquisition digital units 300 can receive the random data signals that data produce digital units 100 output, and the random clock signal that clock generating digital units 200 exports; Data acquisition single digital unit 300 when receiving random clock signal, can gather the random data signals being in metastable state state accordingly according to received random clock signal, thus obtaining random number;
In embodiments of the present invention, data acquisition digital units 300 controls the collection of random data signals by random clock signal, thus latches dwelling in the random data signals of metastable state state, obtains random number;
The random data signals of metastable state state refers to, cannot reach in stipulated time section can the data-signal of acknowledgement state, by the gathered random data signals being in metastable state state is used as random number, random number harvester can be realized and produce and the function gathering random number.
Can find out, the embodiment of the present invention adopts digital units circuit realiration concussion ring, produces random data signals (namely data produce digital units and produce random data signals); The generation (namely clock generating digital units produces random clock signal) of the random clock signal adopting digital units circuit realiration difference to postpone; And then adopt digital units circuit, according to generated clock signal, when metastable state, data acquisition is carried out to concussion ring, obtain metastable random data signals, realize the collection (namely the collection of data acquisition digital units is in the random data signals of metastable state state) to random number, reach the object of the random number harvester adopting digital circuit with this, random number harvester is applied in IP reuses comparatively extensive; Optionally, metastable state random data signals is uncertain state inherently, may be 1, also may be 0.
The random number harvester that the embodiment of the present invention provides, comprising: produce and export random data signals data produce digital units; Produce and export the clock generating digital units of random clock signal; Produce digital units with described data to be connected with described clock generating digital units, when receiving described random clock signal, according to described random clock signal, the random data signals being in metastable state state is accordingly gathered, obtain the data acquisition digital units of random number.The embodiment of the present invention adopts the digital circuit collection of metastable state data, compared to the random number harvester that existing employing mimic channel realizes, the embodiment of the present invention adopts the random number harvester of digital circuit, the difficulty of the IP design reuse in random number harvester can be reduced, promote design convenience, and the random number harvester provided can realize IP between the crypto chip of more various processes reuses, the random number harvester provided is applied comparatively extensive in IP reuses.
The data that Fig. 2 shows the embodiment of the present invention to be provided produce the structural representation of digital units 100, and with reference to Fig. 2, data produce digital units 100 and can comprise: N number of first delayer 110, first Sheffer stroke gate 120, first phase inverter 130;
Wherein, N number of first delayer 110 is made up of to N number of first delayer 110 first the first delayer 110, and in Fig. 2, leftmost first delayer is first the first delayer, and rightmost the one the first delayers are N number of first delayer; In embodiments of the present invention, N number of first delayer 110 series winding connects, and the exportable data-signal of each first delayer;
First input pin of the first Sheffer stroke gate 120 connects with the output pin of N number of first delayer 110, and the second input pin of the first Sheffer stroke gate 120 receives the enable signal of outside input;
Optionally, enable signal can be 0 or 1.
The input of the first phase inverter 130 respectively with the output pin of the first Sheffer stroke gate 120, be connected with the input pin of first the first delayer 110, the first phase inverter 130 pairs input signal processes, exportable random data signals.
Optionally, data shown in Fig. 2 produce in digital units, and the first delayer can select follower to realize, and selected follower quantity can be odd number, and namely N is odd number.
Fig. 3 shows the structural representation of the clock generating digital units 200 that the embodiment of the present invention provides, and with reference to Fig. 3, this clock generating digital units 200 can comprise: L the second delayer 210, data selector 220, the second Sheffer stroke gate 230, second phase inverter 240;
For ease of describing, L the second delayer 210 can be made up of two parts, a part be first the second delayer 210 to M the second delayer 210, another part is that M+1 the second delayer 210 is to L the second delayer 210;
Wherein, first to M the second delayer 210 series winding connects, and M+1 to L the second delayer 210 series winding connects, all exportable clock signal of each second delayer 210;
The input pin of data selector 220 connects respectively with the output pin of M to M-i the second delayer 210, the output pin of data selector 220 connects with M+1 the second extender 210, wherein, second delayer in corresponding M to M-i second delayer of an input pin of data selector 220,1 < M – i < M;
Optionally, M to M-i the second delayer 210 can be M to the second the second delayer 210.
First input pin of the second Sheffer stroke gate 230 connects with the output pin of L the second delayer 210, and the second input pin of the second Sheffer stroke gate 230 receives the enable signal of external number;
Second phase inverter 240 connects with the output pin of the second Sheffer stroke gate 230 and the input pin of first the second delayer 210, second phase inverter 240 can process according to the input signal of the signal of the output of the second Sheffer stroke gate 230 and first the second delayer 210, thus exports random clock signal.
Optionally, in the digital units of clock generating shown in Fig. 3, the second delayer can be follower, and follower quantity can be odd number, and namely L is odd number.
Optionally, Fig. 4 shows the another kind of alternate configurations of the clock generating digital units that the embodiment of the present invention provides, shown in composition graphs 3 and Fig. 4, clock generating digital units can also comprise: sequential arranges circuit 250, sequential arranges the parameter of the sequential of the exportable adjustment clock signal of circuit 250, thus the sequential of the random clock signal that the adjustment of clock generating digital units is produced;
Optionally, the input pin of data selector 220 can receive the parameter that sequential arranges circuit 250 output, to carry out sequential adjustment according to described parameter to the clock signal that the second delayer 220 connected exports; As shown in Figure 4, sequential arranges circuit 250 and connects with the input pin of data selector 220, and data selector 220 can receive the parameter that sequential arranges the sequential of the adjustment clock signal that circuit 250 exports;
In embodiments of the present invention, when how much numerical value of described parameter determines the work of clock generating digital units, how many delayers are really employed; The difference of the delayer number used, will affect the time length of overall clock generation digital units delay, thus the frequency of the final clock generating digital units output random clock signal realized of impact.
Optionally, sequential arranges the parameter that circuit could store and record adjustment sequential, thus exports stored parameter when needing the sequential adjusting clock signal; This parameter can write in the production test link of crypto chip, is then kept; Also when crypto chip works, can be dynamically arranged by the firmware (Firmware) of crypto chip inside;
Concrete, can select nonvolatile memory, as EEPROM, Flash, One Time Programmable unit (OTP), or the memory bank such as electrical fuse (eFuse) realizes sequential and arranges circuit; Accordingly, when the Wafer test of crypto chip, just can write direct in above-mentioned memory bank in test process by correctly suitable parameter, these parameters can not be lost after memory bank power down, in subsequent cryptographic chip operation process, directly can use the parameter arranged in above-mentioned memory bank;
Optionally, register also can be selected to realize sequential and circuit is set; But register after a power failure, the data in register can be lost, and when therefore arranging described parameter, need to carry out initialization after each crypto chip powers on, by firmware program by described parameter read-in register.
Optionally, in embodiments of the present invention, data acquisition digital units 300 can be realized by trigger, and trigger according to received random clock signal, can latch the random data signals being in metastable state state accordingly, thus obtain random number;
Concrete, trigger can be barricaded as by two latchs, for latching the random data signals during being in metastable state; Fig. 5 shows a kind of alternate configurations of the trigger that the embodiment of the present invention provides, and with reference to Fig. 5, trigger can comprise: the first latch 310 and the second latch 320;
Wherein, D interface and the data of the first latch 310 produce digital units 100 and connect, and G interface receive clock produces the random clock signal after the negate of digital units 200 output;
The D interface of the second latch 320 connects with the Q interface of the first latch 310, and G interface receive clock produces the random clock signal that digital units 100 exports, and Q interface exports the random number obtained.
Optionally, Fig. 6 shows another structure of the random number harvester that the embodiment of the present invention provides, can together reference.
It should be noted that in embodiments of the present invention, data produce digital units once design, and the number of delayer (the first delayer) is wherein fixing, and in the course of work, the frequency of data genaration is fixing; But different pieces of information produces the difference because of delayer number in digital units, and its data genaration frequency is also different;
For clock generating digital units, clock generating digital units is once design, the number of delayer (the second delayer) is wherein fixing, but in the course of work, the number of the delayer of effective participation work is configurable, and the clock frequency therefore in clock generating digital units is variable;
And along with the difference of the unit component chosen (cell) kind, the difference of number, the frequency that clock generating digital units produces random clock signal is also different; When adopting identical unit component and number is identical, for ensureing that the frequency of the random clock signal that final clock generating digital units produces is as far as possible consistent with expectation, in the design process of rear end, placement-and-routing should be undertaken by certain requirement, and the delay parameter of the whole link of clock generating digital units can be expected; But for different unit components, because its delayer quantity is not identical, also will the final frequency of clock generating digital units generation random clock signal be made also not identical;
Data acquisition digital units is when specific works, can when random data signals changes, namely when random data signals is in metastable interval, corresponding random data signals of sampling is gone with the random clock signal that clock generating digital units produces, thus obtain the random data signals of uncertain, unpredictable data result, ensure to export random number.
Optionally, in the embodiment of the present invention when realizing, data produce digital units can be existed in pairs with clock generating digital units; And data produce digital units and clock generating digital units, all can use the delayer of odd number number, to reduce the electric leakage probability of circuit;
Further, the embodiment of the present invention can arrange many data acquisition link roads, article one, random number harvester shown in data acquisition link routing diagram 1 is formed, thus connect XOR circuit by after many data acquisition link road parallel connections, after the random number that pieces of data collection link exports being processed by XOR circuit, export final random number.
The embodiment of the present invention is the random number harvester adopting digital circuit; Based on this, the present invention can reduce difficulty, the lifting design convenience of the IP design reuse in random number harvester, and the random number harvester provided can realize IP between the crypto chip of more various processes reuses, the random number harvester provided is applied comparatively extensive in IP reuses.
The embodiment of the present invention also provides a kind of crypto chip, and this crypto chip can comprise at least one random number harvester described above.
The crypto chip tool that the embodiment of the present invention provides has the following advantages:
With the data acquisition of digital circuit metastable state, the reusability of convenient design; Under different chip production manufacturer, different process, IP reuse is very convenient, need not redesign; Design and the checking expense (during Simulation with I P, each Replacement procedure all needs redesign, again flow checking separately, then just dares to be used in crypto chip) of IP can be reduced; Chip can adjust flexibly, and every chips is adjustable separately, even if there is deviation in production technology, also can after chip production be returned, and in test process, fine setting sampling time point, does not need Amending design, regenerates.
Further, the embodiment of the present invention can provide quantity to be greater than the random number harvester of 1, and is connected in parallel between random number harvester; On this basis, crypto chip is also arranged: connect with the random number harvester be connected in parallel, and export the XOR circuit of final random number;
Fig. 7 shows the structural representation of the crypto chip that the embodiment of the present invention provides, and with reference to Fig. 7, this crypto chip can comprise:
Multiple random number harvester 1 be connected in parallel,
Connect with multiple random number harvester 1 be connected in parallel, after the random number of each random number harvester output is processed, export the XOR circuit 2 of final random number.
To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (10)
1. a random number harvester, is characterized in that, comprising:
Produce and export random data signals data produce digital units;
Produce and export the clock generating digital units of random clock signal;
Produce digital units with described data to be connected with described clock generating digital units, when receiving described random clock signal, according to described random clock signal, the random data signals being in metastable state state is accordingly gathered, obtain the data acquisition digital units of random number.
2. random number harvester according to claim 1, is characterized in that, described data produce digital units and comprise:
The first delayer that N number of series winding connects, each first delayer outputting data signals;
First Sheffer stroke gate, the first input pin of described first Sheffer stroke gate connects with the output pin of N number of first delayer, and the second input pin of described first Sheffer stroke gate receives the enable signal of outside input;
The first phase inverter connected with the output pin of described first Sheffer stroke gate and the input pin of first the first delayer, described first phase inverter exports described random data signals.
3. random number harvester according to claim 2, is characterized in that, described delayer is follower, and N is odd number.
4. random number harvester according to claim 1, is characterized in that, described clock generating digital units comprises:
First to M the second delayer connected of contacting;
The second delayer that M+1 connects to L series winding, each second delayer clock signal;
Data selector, the input pin of described data selector connects respectively with the output pin of M to M-i the second delayer, the output pin of described data selector connects with M+1 the second delayer, wherein, second delayer in corresponding described M to M-i second delayer of an input pin of described data selector, 1 < M – i < M;
Second Sheffer stroke gate, the first input pin of described second Sheffer stroke gate connects with the output pin of L the second delayer, and the second input pin of described second Sheffer stroke gate receives the enable signal of outside input;
The second phase inverter connected with the output pin of described second Sheffer stroke gate and the input pin of first the second delayer, described second phase inverter exports described random clock signal.
5. random number harvester according to claim 4, is characterized in that, described delayer is follower, and L is odd number.
6. random number harvester according to claim 4, is characterized in that, described clock generating digital units also comprises:
Sequential arranges circuit, and described sequential arranges circuit for exporting the parameter of the sequential of adjustment clock signal;
Wherein, the input pin of described data selector receives described parameter, to carry out sequential adjustment according to described parameter to the clock signal that the second delayer connected exports.
7. the random number harvester according to any one of claim 1-6, is characterized in that, described data acquisition digital units comprises:
According to received random clock signal, latch the random data signals being in metastable state state accordingly, obtain the trigger of random number.
8. random number harvester according to claim 7, is characterized in that, described trigger comprises:
First latch and the second latch;
Wherein, D interface and the described data of the first latch produce digital units and connect, and G interface receives the random clock signal after the negate of described clock generating digital units output;
The D interface of described second latch connects with the Q interface of described first latch, and G interface receives the random clock signal that described clock generating digital units exports, and Q interface exports the random number obtained.
9. a crypto chip, is characterized in that, comprises at least one random number harvester as described in any one of claim 1-8.
10. crypto chip according to claim 9, is characterized in that, the quantity of described random number harvester is greater than 1, and is connected in parallel between random number harvester; Described crypto chip also comprises:
Connect with the random number harvester be connected in parallel, and export the XOR circuit of final random number.
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| CN104899005B (en) | 2017-12-12 |
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