CN104881519A - Single-event upset effect distinguishing method based on circuit simulation - Google Patents

Abstract

A single-event upset effect distinguishing method based on circuit simulation is characterized in that a theoretical model is built by combining the physical interaction process of space heavy ions and an SRAM device; the response result of a SRAM device electric signal fault mode is obtained by circuit simulation, and whether the device can have the single-event upset effect or not under conditions such as different heavy ion types and different particle incidence dip angles. The method has the advantages that ground heavy ion experiments are not needed, whether the particles under different conditions can cause single-event upset or not under a space radiation environment can be distinguished only by circuit simulation, and the method is visual and simple.

Description

A kind of Single event upset effecf method of discrimination based on circuit simulation

Technical field

The invention belongs to microelectronics technology, relate to a kind of response being obtained fault electric signal by circuit simulation, differentiate whether basic unit of storage SRAM the method for single-particle inversion occurs.

Background technology

The various particles from immense universe are filled with: proton, electronics, α particle, heavy ion, gamma-rays etc. in space, the radiation effect that these particles cause, especially Single event upset effecf (SEU:Single EventUpset) affect the reliability of space electronic system.

The configuring area of the Xilinx FPGA of AEROSPACE APPLICATION is made up of SRAM elementary cell.SRAM type FPGA and SRAM memory etc. are the Primary Components in space electronic system, and single particle effect is the chief threat that it faces.For SRAM type FPGA, more than 90 percent single particle effect occurred is Single event upset effecf.When heavy ion incides the sensitive nodes of SRAM, can cause the upset of transistor state, SRAM Single event upset effecf causes node momentary current after can be regarded as single particle incidence, causes the phenomenon that logic overturns.The basic physical process that single-particle inversion occurs is that particle deposits enough energy in device sensitive volume, thus produce enough ionization electric charges, when high energy charged particles passes through the sensitive volume of semiconductor devices, by generation ionization electric charge on the path that particle passes through, the charged moiety be deposited in device sensitive volume is collected by electrode, when the electric charge collected exceedes the critical charge of circuit state, circuit just there will be upset, occurs the confusion of logic function.

The method of current differentiation device generation single particle effect, is mainly realized by the test of ground Heavy ion simulation.The single particle effect carried out based on ground simulation test depends on the restriction of domestic heavy ion source, and beam time cannot ensure, and ground experiment expense is relatively costly.And when being differentiated by analog simulation, the model method of extensive employing is all F.B.Mclean " funnel " model theory based on classics, but " funnel " model can not characterize the temporal properties that heavy ion causes electric current, need the charge-trapping mechanism in the device interface caused in conjunction with heavy ion in carrier transport theoretical research space radiation environment.And funnel model just carries out theoretical modeling for single MOS cell, only obtain the critical charge value Q that can cause MOS cell generation single-particle inversion _c, namely collect the charge threshold that electric charge can cause single-particle inversion.

Summary of the invention

The technical matters that the present invention solves is: overcome the deficiencies in the prior art, provide a kind of Single event upset effecf method of discrimination based on circuit simulation, the method can differentiate whether circuit single-particle inversion can occur under different-energy, different angles, variety classes heavy ion radiation condition fast and effectively.

Technical solution of the present invention is: a kind of Single event upset effecf method of discrimination based on circuit simulation, comprises the steps:

(1) determine incident heavy ion type, and calculate heavy ion and incide the electron-hole pair concentration N that SRAM device produces; Wherein:

$N=\frac{\mathrm{LET}}{3.6},\mathrm{LET}=\frac{1}{\mathrm{\ρ}}\frac{\mathrm{dE}}{\mathrm{dx}}$

LET is the linear energy transfer coefficient of heavy ion, and ρ is the backing material density of SRAM device, for the stopping power that the final dump energy of heavy ion is corresponding;

(2) the transient current source model produced after SRAM device is incided in foundation,

I(t)＝I ₀·sec(θ)[exp(-αt)-exp(-βt)]

$I_0=-q\stackrel{\‾}{\mathrm{\μ}}N{E}_0,\mathrm{\α}=\frac{{\mathrm{k\ϵ}}_0}{q\stackrel{\‾}{\mathrm{\μ}}{N}_D},\mathrm{\β}={10}^{11}{s}^{-1}$

Wherein: I ₀be approximate maximum current, θ refers to the incident inclination angle of heavy ion, and t is time variable, μ _nfor electron mobility, μ _pfor hole mobility, E ₀for ionization energy, k is Boltzmann constant, and q is electron charge, ε ₀=8.85 × 10 ^-14f/cm, N _dfor the density of donor impurity;

(3) the transient current source model equivalence of step (2) being set up becomes full sized pules current source; The parameter of described full sized pules current source comprises current minimum I ₁, current maxima I ₂, pulse width P _w, rise time T _r, fall time T _f, cycle PER;

(4) according to SRAM device technological parameter, host age preference transistor and dead resistance, set up equivalent parasitic circuit, then in equivalent parasitic circuit at least one parasitic transistor PN junction on a full sized pules current source in parallel, the position that single-particle inversion may occur the SRAM device that the position of PN junction emulates as required is determined;

(5) when acquisition SRAM device is working properly, the output waveform of described equivalent parasitic circuit is as reference waveform, using the output waveform of described equivalent parasitic circuit after superposition full sized pules current source as actual waveform, if actual waveform is consistent with reference waveform, then judge that single-particle inversion does not occur SRAM device, if actual waveform and reference waveform inconsistent, then judge SRAM device there occurs single-particle inversion.

The present invention's advantage is compared with prior art: the inventive method is in conjunction with carrier transport theory, obtain the electric current temporal properties that heavy ion causes, and the equivalence of electric current temporal properties is become the normalized current source model in SPICE, the response results of the Single event upset effecf of circuit can be obtained intuitively.By this method, for different heavy ion radiations, different circuit forms, modeling and simulating can be carried out, can differentiate whether circuit single-particle inversion can occur under different-energy, different angles, variety classes heavy ion radiation condition fast and effectively.Ground accelerator test is the more direct method of one differentiating Single event upset effecf, but because ground accelerator beam time is nervous, and it is expensive, cost is very high to cause the single particle effect of circuit to differentiate, and the method that this method emulates based on circuit modeling, can differentiate for different circuit realiration economy, efficiently Single event upset effecf, the electric response result of the circuit simulation device of acquisition can be used for Failure Injection Technique.

Accompanying drawing explanation

Fig. 1 is the FB(flow block) of the inventive method;

Fig. 2 (a) attaches most importance to the current-responsive obtained in ion incidence to device, and Fig. 2 (b) is the full sized pules current source schematic diagram that current source model equivalence becomes in SPICE software;

Fig. 3 is the equivalent parasitic circuit diagram that SRAM of the present invention affects by Single event upset effecf;

Fig. 4 is the simulation result schematic diagram of SRAM Single event upset effecf of the present invention; Fig. 4 (a) is correct output waveform, and Fig. 4 (b) is for there occurs the wrong output waveform of single-particle inversion.

Embodiment

The kind of the heavy ion in space is different, and incident direction to be the total space incident, the therefore influencing mechanism of the first heavy ion of Water demand different particle kind, energy and incident angle.Then incide on the basis of the current impulse model that device produces at acquisition heavy ion, combined circuit emulation mode, heavy ion can be realized and incide the change that circuit causes circuit to export, and then obtain the electric response of fault, thus differentiate whether device single-particle inversion occurs.

Fig. 1 is the process flow diagram of the Single event upset effecf method of discrimination that the present invention is based on circuit simulation, is that embodiment is described in detail below with SRAM device.

(1) calculate heavy ion and incide the electron-hole pair concentration N that device produces;

According to incident heavy ion kind, energy, carry out the calculating of LET value, heavy ion LET value computing formula is:

$\mathrm{LET}=\frac{1}{\mathrm{\ρ}}\frac{\mathrm{dE}}{\mathrm{dx}}$

Wherein:

LET: the linear energy transfer coefficient of heavy ion, unit is MeVcm ²/ mg;

ρ: backing material density, the density of silicon is 2.33 × 10 ³mg/cm ³;

DE/dx: the stopping power that the final dump energy of heavy ion is corresponding, unit is MeV/cm.

The heavy ion of certain type incides in substrate, and its energy is E.The corresponding relation of dE/dx existence and heavy ion type, energy and substrate type, comparatively authoritative is the result that SRIM software provides at present.

Illustrate the computation process of dE/dx below: with the data instance of C ion in substrate Si, SRIM software can provide data layout as shown in Table 1 below.

Table 1 SRIM calculates the correlation parameter of C ion incidence to silicon substrate

Wherein " Ion Energy " represents heavy ion energy, and " dE/dx Elec. " represents electronic stopping power, and unit is MeVcm ²/ mg, " dE/dx Nuclear " represents nuclear stopping power, and unit is MeVcm ²/ mg, " Projected Range " represents heavy ion range, longitudinal qi that " Longitudinal Straggling " represents range from, the horizontal qi that " Lateral Straggling " represents range from.

The LET value of heavy ion refers to electronic stopping power and nuclear stopping power sum, therefore needs " dE/dx Elec. " and " dE/dx Nuclear " to be added to obtain total stopping power.But due to " dE/dx Nuclear ", to compare " dE/dx Elec. " much little, therefore can ignore.So C ion incidence is in silicon substrate, the relation of different-energy E and stopping power dE/dx is as shown in table 2:

Table 2 C ion energy and stopping power

According to LET value, the concentration N of the incident rear electron-hole pair (charge carrier) produced can be calculated.For silicon substrate, produce the energy that an electron-hole pair needs 3.6eV, so the concentration of the electron-hole pair produced is:

$N=\frac{\mathrm{LET}}{3.6}$

N: the concentration of electron-hole pair, unit is individual/cm.

(2) the transient current source model produced after device is incided in foundation;

Current source derivation of equation based semiconductor Transport Model and charge carrier continuity equation, as follows:

$\frac{\mathrm{dn}}{\mathrm{dt}}=G_n-R_n+\frac{1}{q}\▿\·J_n,\frac{\mathrm{dp}}{\mathrm{dt}}=G_p-R_p-\frac{1}{q}\▿\·J_p$

$J_n={\mathrm{q\μ}}_n\mathrm{nE}+q{D}_n\▿n,J_p=q{\mathrm{\μ}}_p\mathrm{pE}-q{D}_p\▿p$

Wherein:

J _nand J _prefer to electron current density and hole current density respectively;

E refers to electric field intensity;

G _nand G _prefer to the generation rate in electronics and hole respectively;

R _nand R _prefer to the recombination rate in electronics and hole respectively;

N and p refers to the concentration in electron density and hole respectively;

Q is electron charge, q=1.6 × 10 ^-19c;

D _nand D _prefer to the coefficient of diffusion in electronics and hole respectively;

μ _nfor electron mobility;

μ _pfor hole mobility;

for gradient signs.

Obtain heavy ion based on funnel model and incide current-responsive in device substrate, in conjunction with transport equation and charge carrier continuity equation, obtain by approximate treatment the current source formula that heavy ion incidence causes:

I(t)＝I ₀·sec(θ)[exp(-αt)-exp(-βt)]

$I_0=-q\stackrel{\‾}{\mathrm{\μ}}N{E}_0,\mathrm{\α}=\frac{{\mathrm{k\ϵ}}_0}{q\stackrel{\‾}{\mathrm{\μ}}{N}_D},\mathrm{\β}={10}^{11}{s}^{-1}$

Wherein:

I ₀approximate maximum current, relevant with device semiconductor material dopant profiles with heavy ion type, energy;

θ refers to the incident inclination angle of heavy ion;

α ties the relevant parameter of charge-trapping with pn;

β attach most importance to Ion track set up parameter;

T is time variable.

for silicon substrate: μ _n=1200cm ²/ (V.s), μ _p=500cm ²/ (V.s);

N obtains in step (1);

E ₀for ionization energy, be 1.05eV in silicon.

K=1.38 × 10 ^-23j/K is Boltzmann constant;

ε ₀＝8.85×10 ^-14F/cm；

N _dfor the density of donor impurity, choose according to concrete device technology situation, be generally 1 × 10 ¹⁵individual/cm ³.

The current source model set up is used in device, represents the current-responsive caused by heavy ion incidence.

(3) current source model equivalence becomes the full sized pules current source in SPICE software;

According to the current source model that step (2) obtains, equivalence becomes the full sized pules current source in SPICE software, for follow-up circuit simulation.

Fig. 2 (a) attaches most importance to the current-responsive obtained in ion incidence to device, and then obtains current source model, and the equivalence of Fig. 2 (b) current source model becomes the full sized pules current source in SPICE software.I in Fig. 2 (a) ₀for current maxima, t ₁and t ₂respectively electric current ascent stage and electric current decline stage, electric current is I ₀two times of × 90% correspondence.Then the relation of Fig. 2 (a) and Fig. 2 (b) is mapped, as the parameter that Fig. 2 (b) wherein needs confirmed standard pulse current source, comprises current minimum I ₁, current maxima I ₂, pulse width P _w, rise time T _r, fall time T _f, cycle PER.

Normalized current source model parameter is determined as follows: current minimum I ₁=0; Current maxima I ₂=I ₀; Rise time T _rfor electric current in Fig. 2 (a) is that 0 moment is to t ₁the time span in moment; Fall time T _ffor in Fig. 2 (a) from t ₂moment reduces to the time span in 0 moment to electric current, pulse width P _w=t ₂-t ₁; The numerical value that cycle PER chooses is greater than the T.T. needed for emulation, to ensure only to occur primary current pulse in simulation process.The length of 0-t1 is that to rise to electric current from 0 be I to electric current ₀when × 90%, corresponding time span.

(4) set up device parasitic equivalent electrical circuit, emulation obtains device Single event upset effecf result;

According to device technology parameter, by SPICE software according to device concrete condition, the parameter of the primary elements such as host age preference transistor, resistance.In the transient current source utilizing step (3) to obtain, in conjunction with the equivalent parasitic circuit model set up, emulation obtains device Single event upset effecf result.

According to the concrete technology situation of device, i.e. material, substrate thickness, well depth, the doping content of SRAM device substrate, the parameters such as the dead resistance in acquisition equivalent electrical circuit and parasitic transistor.Utilizing step (3) to obtain on the basis in transient current source, set up equivalent parasitic circuit model, as shown in Figure 3.SRAM is mainly made up of the CMOS of two feedback arrangements each other, CMOS is made up of a PMOS and NMOS, the PMOS that is connected with power supply is above a parasitic diode, the NMOS that is connected with ground wire is below a parasitic triode, this is also the usual way of conventional transistors parasitic circuit.Because the interface of incident heavy ion effect CMOS in sram can cause Single event upset effecf, therefore the current source that produces of incident heavy ion is all in parallel with the PN junction of each transistor (comprising diode and triode).Dead resistance is placed between NMOS and ground wire, the dead resistance of typical process can span generally between 100-1000.Here it should be noted that, although three PN junction positions are in parallel in figure 3 full sized pules current source, this is not unique mode.In real work, according to actual needs, the incident effect caused of the PN junction position of emulation full sized pules current source in parallel simulation heavy ion can needed.

Emulation obtains the equivalent parasitic Simulation results that SRAM affects by single-particle inversion, and if Fig. 4, Fig. 4 (a) are correct output waveform, Fig. 4 (b) is for there occurs the wrong output waveform of single-particle inversion.Circuit is the low and high level exporting one-period under normal circumstances, when have collected electric charge in transistor interface after heavy ion incidence, defining pulse current source, high level being dragged down, thus becomes low level, namely there occurs Single event upset effecf.In a word, if the heavy ion under certain condition incides circuit, after emulation, high level becomes low level originally, or low level becomes high level originally, just can differentiate under this kind of heavy ion condition, there occurs single-particle inversion; If low and high level does not change, just can differentiate under this kind of heavy ion condition, not there occurs Single event upset effecf.Realize Single event upset effecf to differentiate, obtain the SRAM failure mode analysis (FMA) indication of Single event upset effecf impact simultaneously.

The content be not described in detail in instructions of the present invention belongs to the known technology of those skilled in the art.

Claims (1)

1., based on a Single event upset effecf method of discrimination for circuit simulation, it is characterized in that comprising the steps:

(1) determine incident heavy ion type, and calculate heavy ion and incide the electron-hole pair concentration N that SRAM device produces; Wherein:

$N=\frac{\mathrm{LEF}}{3.6},\mathrm{LET}=\frac{1}{\mathrm{\ρ}}\frac{\mathrm{dE}}{\mathrm{dx}}$

LET is the linear energy transfer coefficient of heavy ion, and ρ is the backing material density of SRAM device, for the stopping power that the final dump energy of heavy ion is corresponding;

(2) the transient current source model produced after SRAM device is incided in foundation,

I(t)＝I ₀·sec(θ)[exp(-αt)-exp(-βt)]

$I_0=-q\stackrel{\‾}{\mathrm{\μ}}{\mathrm{NE}}_0,\mathrm{\α}=\frac{{\mathrm{k\ϵ}}_0}{q\stackrel{\‾}{\mathrm{\μ}}{N}_D},\mathrm{\β}={10}^{11}{s}^{-1}$

Wherein: I ₀be approximate maximum current, θ refers to the incident inclination angle of heavy ion, and t is time variable, μ _nfor electron mobility, μ _pfor hole mobility, E ₀for ionization energy, k is Boltzmann constant, and q is electron charge, ε ₀=8.85 × 10 ^-14f/cm, N _dfor the density of donor impurity;

(3) the transient current source model equivalence of step (2) being set up becomes full sized pules current source; The parameter of described full sized pules current source comprises current minimum I ₁, current maxima I ₂, pulse width P _w, rise time T _r, fall time T _f, cycle PER;

(4) according to SRAM device technological parameter, host age preference transistor and dead resistance, set up equivalent parasitic circuit, then in equivalent parasitic circuit at least one parasitic transistor PN junction on a full sized pules current source in parallel, the position that single-particle inversion may occur the SRAM device that the position of PN junction emulates as required is determined;

(5) when acquisition SRAM device is working properly, the output waveform of described equivalent parasitic circuit is as reference waveform, using the output waveform of described equivalent parasitic circuit after superposition full sized pules current source as actual waveform, if actual waveform is consistent with reference waveform, then judge that single-particle inversion does not occur SRAM device, if actual waveform and reference waveform inconsistent, then judge SRAM device there occurs single-particle inversion.