CN104838615B - Signal synchronization system, node synchronization system, signal synchronization method, and node synchronization method - Google Patents

Abstract

In the signal synchronizing system of the present invention, primary module is counted, when count value reaches a reference value set in advance, generate the 1st reference signal, slave module is counted, when count value reaches a reference value, generate the 2nd reference signal, the interval for synchronizing correcting process is counted, after count value reaches and synchronizes the correcting process spacing value of correcting process, receive the 1st reference signal and restart, counted, after the count value at the interval for representing to synchronize correcting process reaches correcting process spacing value, count value after obtaining the count value for generating the 2nd reference signal and receiving the 1st reference signal and restart, the count value for being used for generating the 2nd reference signal will be offset and receive the 1st reference signal and the value of difference between count value after restarting temporarily is set in counting for generating the 2nd reference signal as a reference value.

Description

Signal synchronization system, node synchronization system, signal synchronization method, and node synchronization method

technical field

The present invention relates to a signal synchronization system, a node synchronization system, a signal synchronization method, and a node synchronization method for synchronizing predetermined signals.

Background technique

Conventionally, when a predetermined program is executed by a processor or the like, a multiprocessor system is known that executes processing by a plurality of processors for the purpose of coping with large-scale processing, increasing the processing speed, and distributing the load. In such a multiprocessor system, in order to realize the synchronization of counters (timers) between multiple processors, the master processor generates an interrupt signal to the counter of the slave processor, etc., and the slave processor realizes the timer according to the interrupt signal. Synchronization of counters.

In addition, in an existing industrial network such as a transmission system for factory control, each device constituting the system needs to exchange large-capacity data with each other while ensuring real-time performance. Therefore, for example, when mutual access is event-based based on the occurrence of an access request from an application installed in each device, the network load depends on the application, and real-time performance may not be guaranteed.

Therefore, conventionally, there has been a technique in which a virtual shared memory (common memory) is provided for each device, and own-node data is transmitted to all nodes (stations) on the network at update timing. In the case of using the above technology, the received nodes update their data and make it available for application programs to access, thereby realizing a data exchange mode that ensures real-time performance. In addition, conventionally, a method for realizing efficient broadcast communication (BROADCAST COMMUNICATION) on a network during the above-mentioned data exchange has been proposed (for example, refer to Patent Document 1).

In Patent Document 1, a time-division multiplexing access method using a built-in timer of each node and a built-in timer correction of a slave node based on a synchronization frame from a master node are used together. In addition, in the method disclosed in Patent Document 1, a network is configured in which transmission paths are connected by a bus or a serial cable.

prior art literature

patent documents

Patent Document 1: Japanese Patent Laid-Open No. 2005-159754

Contents of the invention

The technical problem to be solved by the invention

However, in the above-mentioned counter synchronization correction process performed between the master processor and the slave processor, it is preferable that the master processor directly (slave hardware) reset the counter of the slave processor. However, since this counter is used as an execution standard for a plurality of program processes performed internally, if it can be freely rewritten from the outside, problems may arise in other processes. In addition, when the counter is built in a CPU (Central Processing Unit: central processing unit) of the slave processor, etc., the counter of the slave processor cannot be reset directly from the master processor. Therefore, conventionally, when an interrupt signal is sent from the master processor to the slave processor, the slave processor receives the signal and indirectly (software-wise) executes counter reset processing by predetermined software.

In the above case, a delay time occurs due to overhead (overhead) or the like between the slave processor receiving the interrupt signal from the master processor and executing the reset process of its own counter corresponding to the signal. Therefore, conventionally, even if reset processing is performed, there is still a counter synchronization error between the master processor and the slave processor.

In addition, for the synchronization of counters between nodes having a master-slave relationship between networks, for example, a method such as clearing a timer by receiving a synchronization frame is conceivable. However, as described above, if the timer is cleared by firmware after the synchronization frame is received, an error will occur in the counter due to delay time such as the system overhead.

Therefore, in the conventional method of synchronizing the nodes using the synchronization frame, when the firmware of the microcomputer is used to measure and correct the synchronization time between the master node and each slave node, the processing of the microcomputer error due to time.

Therefore, in order to suppress the impact on other processes caused by the rewriting of the counter, the following method is considered: the slave hardware counts the interrupt signals sent from the master processor to the slave processor, based on the relationship with the counter in the slave processor. The difference between them is used to adjust the count target (reference value) of the counter of the slave processor, so as to realize the synchronization between the master processor and the slave processor.

Since the counters of the master processor and the counters of the slave processors have different electrical characteristics, it is difficult to estimate how many counters there are between the master processor and the slave processors. Therefore, if the synchronization correction process of adjusting the reference value of the counter of the slave processor is performed every interrupt signal, the synchronization between the master processor and the slave processor can be ensured. However, if the synchronization correction processing is performed frequently, the processing load increases, which may affect other processing that should be executed originally.

The present invention has been made in view of the foregoing, and an object of the present invention is to provide a signal synchronization system, a node synchronization system, a signal synchronization method, and a node synchronization method capable of synchronizing predetermined signals with high precision while suppressing processing load.

Technical solutions adopted to solve technical problems

In order to solve the above problems, the signal synchronization system of the present invention includes a master module that operates based on a first reference signal, and a slave module that operates based on a second reference signal, and synchronizes the second reference signal with the first reference signal, It is characterized in that the master module includes: a first reference signal generating part, and the first reference signal generating part generates a first reference signal when the count value reaches a preset reference value by counting, and the slave module includes: a second A reference signal generation unit, the second reference signal generation unit generates a second reference signal by counting when the count value reaches the reference value; an interval counting unit, the interval counting unit counts the intervals for synchronous correction processing; system overhead A counting unit, the system overhead counting unit receives the first reference signal after the count value in the interval counting unit reaches the correction processing interval value for synchronous correction processing, thereby restarting, and counting; a count value acquisition unit, the count value acquisition After the count value in the interval counting part reaches the correction processing interval value, the count value of the second reference signal generating part and the count value of the system overhead counting part are acquired according to the reception of the first reference signal; and the synchronous correction part, the synchronous correction The unit temporarily sets, as a reference value, a value that cancels out a difference between the count value of the second reference signal generation unit and the count value of the overhead count unit in the second reference signal generation unit.

In addition, the present invention also includes technical solutions obtained by applying the constituent elements, expressions, or arbitrary combinations of constituent elements of the present invention to methods, devices, systems, computer programs, recording media, data structures, and the like.

Invention effect

According to the present invention, predetermined signals can be synchronized with high precision while suppressing the processing load.

Description of drawings

FIG. 1 is a diagram showing an example of a schematic configuration of a signal synchronization system according to Embodiment 1. As shown in FIG.

FIG. 2 is a diagram showing an example of a hardware configuration of a processor module.

FIG. 3 is a sequence diagram (Part 1) for explaining an example of synchronization correction processing in Embodiment 1. FIG.

FIG. 4 is a sequence diagram (Part 2) for explaining an example of synchronization correction processing in Embodiment 1. FIG.

FIG. 5 is a sequence diagram (Part 3 ) for explaining an example of synchronization correction processing in Embodiment 1. FIG.

FIG. 6 is a diagram showing an example of a rough procedure of a signal synchronization method.

FIG. 7 is a diagram showing an example of a schematic configuration of a node synchronization system in Embodiment 2. FIG.

FIG. 8 is a sequence diagram (Part 1) for explaining an example of synchronization correction processing in Embodiment 2. FIG.

FIG. 9 is a sequence diagram (Part 2) for explaining an example of synchronization correction processing in Embodiment 2. FIG.

FIG. 10 is a sequence diagram (Part 3) for explaining an example of synchronization correction processing in Embodiment 2. FIG.

FIG. 11 is a diagram for explaining an example of a notification procedure of a transmission delay time in Embodiment 2. FIG.

FIG. 12 is a diagram showing an example of a schematic configuration of a network transmission system including a node synchronization system using a master node and slave nodes in Embodiment 2. FIG.

FIG. 13 is a diagram showing an example of a rough procedure of a node synchronization method.

detailed description

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The dimensions, materials, and other specific numerical values shown in the related embodiments are merely examples for easy understanding of the present invention, and are not limited to the examples shown in the present invention except in cases explicitly indicated. . In this specification and the drawings, elements having substantially the same function and structure are assigned the same reference numerals to omit repeated description, and illustration of elements not directly related to the present invention is omitted.

(about this embodiment)

In this embodiment, for example, when synchronizing counters (timers) between multiple processor modules, multiple nodes each including at least one processor module, multiple nodes, devices, and substrates that have a master-slave relationship, the An interrupt signal (counter reset signal) from the master module side calculates the overhead value of the slave module side. In addition, in this embodiment, synchronization correction processing is performed based on the obtained overhead value and the counter on the slave module side.

However, if this synchronous correction process is executed frequently, the processing load will increase. Therefore, in this embodiment, the intervals at which the synchronous correction process is performed are counted, and periodically (intermittently) at a predetermined correction process interval value. Execute synchronous correction processing.

In addition, in the present embodiment, when the devices having a master-slave relationship are set as the master node and the slave node, the synchronization correction process is performed taking into account the delay time (transmission delay time) on the communication path.

Next, preferred embodiments of the signal synchronization system and the node synchronization system in this embodiment will be described with reference to the drawings.

(Embodiment 1: Signal Synchronization System)

FIG. 1 is a diagram showing an example of a schematic configuration of a signal synchronization system according to Embodiment 1. As shown in FIG. In the signal synchronization system 10 shown in FIG. 1 , as an example, a method for performing counter synchronization among a plurality of processor modules as modules (processor modules 11a to 11c in the example in FIG. 1 ) is shown. An example of a multiprocessor.

The signal synchronization system 10 shown in FIG. 1 has: a plurality of processor modules 11a-11c (hereinafter referred to as "processor modules 11" as needed), a transmission bus 12, and an I/O (input and output) module 13 (referred to as 13a-13d), the external device 14 (shown as 14a-14d in FIG. 1 ), and the compiling device 15. Here, in the example of FIG. 1 , for convenience of explanation, the processor module 11a is set as the master processor module, and the processor modules 11b and 11c are set as the slave processor modules, and the main structures of each processor module will be described. . Wherein, the number of slave processor modules is not limited to two as shown in FIG. 1 .

In addition, in this embodiment, it is not limited to the above-mentioned structure, and each single processor module has the same structure, so that it can be the master processor module 11a, and can also be the slave processor module 11b, 11c. In addition, the respective processor modules 11 are connected via a transmission bus 12 . In addition, in Embodiment 1, it is assumed that no delay time is generated due to the transmission bus 12 .

Here, the main processor module 11 a has a first reference signal generation unit 21 , a first calculation unit 22 , and a storage unit 23 . In addition, in the example of FIG. 1 , the first reference signal generating unit 21 is incorporated in a CPU described later, but the present invention is not limited thereto. For example, the first reference signal generating unit 21 and the CPU may be configured separately. In addition, the above-mentioned "built-in", for example, means that only each functional unit (first reference signal generation unit 21 , first calculation unit 22 ) in the CPU can access the first reference signal generation unit 21 .

In addition, the slave processor modules 11b and 11c have a second reference signal generating unit 31, a second calculating unit 32, an interval counting unit 33, an overhead counting unit 34, a count value acquiring unit 35, a synchronization judging unit 36, and a synchronization correcting unit 37. , and the storage unit 38 . In addition, in the example of FIG. 1 , the second reference signal generating unit 31 is incorporated in the CPU, but the present invention is not limited thereto. For example, the second reference signal generating unit 31 and the CPU may be configured separately.

The first reference signal generation unit 21 generates a first reference signal by counting until the count value reaches a preset reference value. In addition, the first reference signal generation unit 21 functions as a hardware counter (hereinafter also referred to as a “timer” as necessary). The count value described above is periodically counted based on the reference value. In FIG. 1, the above-mentioned hardware counters are indicated by dotted lines.

The first calculation unit 22 executes (calculates) a predetermined application program and the like stored in the storage unit 23 based on the first reference signal generated by the first reference signal generation unit 21 . In addition, the first reference signal is supplied (transmitted) as an interrupt signal (counter reset signal) to the slave processor modules 11b and 11c via the transfer bus 12 .

The storage unit 23 stores a predetermined application program (Sequence Program) that is calculated by the first calculation unit 22 . In addition, the predetermined application program that the first calculation unit 22 performs calculations is, for example, a process of instructing the I/O module 13a connected to the main processor module 11a and controlling the external device 14a using the I/O module 13a. Therefore, the storage unit 23 mainly stores programs for executing predetermined processing on the I/O module 13a connected to the processor module 11a and the external device 14a.

That is, the main processor module 11a generates the first reference signal every predetermined cycle, and the first calculating unit 22 controls a predetermined device by executing (calculating) an application program (sequence program) based on the first reference signal, The application program (sequence program) is executed periodically.

Next, the slave processor modules 11b and 11c will be described, but since the slave processor modules 11b and 11c have the same configuration, in the following description, the slave processor module 11b will be used for description, and the description of the slave processor module 11c will be omitted.

The second reference signal generation unit 31 counts, sets the same reference value as the reference value set in the first reference signal generation unit 21 , and generates the second reference signal by making the count value reach the reference value. In addition, the second reference signal generation unit 31 functions as a hardware counter. The count value described above is periodically counted based on the reference value. In addition, the respective counters of the first reference signal generating unit 21 and the second reference signal generating unit 31 are free-running counters, and advance by themselves.

The second calculation unit 32 executes (calculates) a predetermined application program or the like stored in the storage unit 38 based on the second reference signal generated by the second reference signal generation unit 31 .

In addition, the second reference signal generating unit 31 is a counter that can be accessed only from the second calculation unit 32 in the CPU, for example, and is built in the CPU (CPU built-in counter). That is, the second reference signal generation unit 31 is a counter that cannot be reset by hardware from the outside such as the main processor module 11a.

In addition, the second calculation unit 32 receives the first reference signal (synchronization reference signal) from the main processor module 11a as an interrupt signal, and starts a synchronization correction process described later.

The interval counting unit 33 counts, presets a correction processing interval value corresponding to the correction processing interval at which synchronization processing is performed, and generates a correction processing start signal indicating that when the count value reaches the correction processing interval value.

In addition, the correction processing interval value is set by the following calculation. For example, the allowable synchronization error between the master processor module 11a and the slave processor module 11b in order to satisfy the machining accuracy required by the signal synchronization system is set to 10 μs. In this case, in this embodiment, the shortest time until the synchronization error becomes 1 to 5 μs is calculated. Here, the synchronization error is set to 1 μs or more because if it is shorter than 1 μs, the frequency of the synchronization correction process will increase and the processing load will increase. quantity.

At this time, the frequency of the oscillators used in the master processor module 11 a and the slave processor module 11 b is set to 50 MHz, and the oscillation precision is set to 50 ppm. Under this condition, the shortest time for the synchronization error to become 1 μs is the time of one clock × the number of oscillations for which the synchronization error deviates, that is, 20 ns × ((1 μs/20 ns) × (1/50 ppm)) = 20 ms. Likewise, the minimum time for the synchronization error to become 5µs is 100ms. Therefore, the corrected time interval value may be a value obtained by converting 20 ms to 100 ms into a count value. By setting the correction processing interval value within the above range and intermittently executing the synchronous correction processing, it is possible to achieve higher machining accuracy and improve production quality while suppressing the processing load.

The system overhead counting unit 34 performs counting, and after receiving the correction process start signal, that is, after the count value of the interval counting unit 33 reaches the correction process interval value, measures the time starting from the reception of the above-mentioned first reference signal until execution. System overhead value up to synchronization correction processing. Specifically, the overhead counting unit 34 functions as a hardware counter (timer) that is restarted after receiving the first reference signal.

Since the overhead counting unit 34 is a counter constituted by hardware, it directly responds to the first reference signal, but the synchronization correction process takes time until preparations for reading the count value are completed, for example. The overhead is the time required until the preparation for reading the count value is complete. In addition, the system overhead represents the delay time from the occurrence of a certain event to the actual execution of the processing (software) corresponding to the event. In this example, the system overhead is from the restart point of the system overhead counting unit 34 to the actual execution of the synchronization correction process. time, but not limited to this.

After the count value acquisition unit 35 receives the correction process start signal, that is, after the count value of the interval counter 33 reaches the correction process interval value, based on the reception of the first reference signal, it acquires the time (start time) when the synchronization correction process is actually executed. ) of the count value of the second reference signal generation unit 31 and the count value of the overhead count unit 34 .

The synchronization determination unit 36 determines that the first reference signal is synchronized with the second reference signal when the count value of the second reference signal generation unit 31 acquired by the count value acquisition unit 35 is the same as the count value of the overhead counter unit 34 . In addition, when the count value of the second reference signal generating unit 31 acquired by the count value acquiring unit 35 is different from the count value of the overhead counting unit 34, the synchronization determination unit 36 determines that the first reference signal is different from the second reference signal. Signals are out of sync.

In addition, the synchronization judging unit 36 may perform time conversion on the count value of the second reference signal generating unit 31 acquired by the count value acquiring unit 35 and the count value of the system overhead counting unit 34, and when the two times are equal, determine In addition, when both times are different, it is judged to be out of synchronization. That is, in Embodiment 1, the unit time per clock of each counter may not be equal among the processor modules 11 . Therefore, in this case, each count value is converted into time, and the synchronization/non-synchronization determination is performed using the converted time.

The synchronization correction unit 37 sets a reference value in the second reference signal generation unit 31 when the synchronization determination unit 36 determines that the first reference signal is synchronized with the second reference signal. In addition, when the synchronization determination unit 36 determines that the first reference signal is not synchronized with the second reference signal, the synchronization correction unit 37 obtains the count value of the second reference signal generation unit 31 and the count value of the overhead count unit 34. The difference between the offset values. Specifically, the synchronization correction unit 37 subtracts the count value of the overhead counter unit 34 from the count value of the second reference signal generation unit 31 acquired by the count value acquisition unit 35 to obtain a synchronization correction value. Next, the synchronization correction unit 37 subtracts the obtained synchronization correction value from the reference value, and sets the subtracted value as a new reference value in the second reference signal generation unit 31 . The new reference value is a timer reference value temporarily used when the synchronization judging unit 36 judges that it is out of sync, with respect to the timer reference value (default reference value) used when the synchronization judging unit 36 judges that it is synchronous.

In addition, if the synchronization judging unit 36 judges that the first reference signal and the second reference signal are out of sync, and sets the subtracted value as a new reference value in the second reference signal generating unit 31, and uses the When the counting of the value obtained after the subtraction is completed, the synchronization correction unit 37 promptly sets the reference value in the second reference signal generation unit 31 . Accordingly, it is possible to temporarily change the reference value by the amount of the synchronization correction value. Here, an example in which correction corresponding to the synchronous correction value is performed once is given, but the present invention is not limited thereto, and may be performed several times. In this case, the synchronization correction unit 37 sets the reference value in the second reference signal generation unit 31 after the synchronization correction process is completed.

In addition, if the synchronization determination unit 36 determines that the first reference signal and the second reference signal are synchronized, the synchronization correction unit 37 can set the above-mentioned default reference value to the second reference signal generation unit 31 one by one, but it can also be In the case of maintaining synchronization, after setting the default reference value once, there is no further action.

In addition, in this embodiment, since the synchronization correction process is executed at every correction processing interval, there is a high possibility that the count value of the second reference signal generation unit 31 is different from the count value of the overhead count unit 34, and the synchronization determination unit 36 In many cases, it is determined that the first reference signal and the second reference signal are not synchronized. Therefore, it is not necessary to use the synchronization determination unit 36 to perform the determination, that is, regardless of whether the first reference signal and the second reference signal are synchronized or not, the synchronization correction unit 37 can obtain the sum of the count value and the second reference signal generation unit 31. A value obtained by canceling the difference between the count values of the overhead counting unit 34 is set in the second reference signal generating unit 31 as a new reference value.

Thus, by omitting the configuration of the synchronization judging unit 36 , judging processing becomes unnecessary, and the processing load corresponding to the amount of processing required for judging can be reduced.

The storage unit 38 stores a predetermined application program (sequence program) that is calculated by the second calculation unit 32 . In addition, the predetermined application program that the second calculation unit 32 performs calculations is, for example, to issue instructions to the I/O modules 13b, 13c connected to the slave processor module 11b, and use the I/O modules 13b, 13c to communicate with the external devices 14b, 14c. Controlled processing. Therefore, the storage unit 38 mainly stores programs for executing predetermined processing on the I/O modules 13b and 13c connected to the processor module 11b and the external devices 14b and 14c.

The I/O module 13 performs input/output processing with external devices 14 and the like. For example, the I/O module 13 outputs (transmits) data obtained from the connected external device 14 and the like to the processor module 11, or outputs the result of calculation and processing by the processor module 11 to the external device 14 and the like, or It is stored. That is, the processor module 11 uses the application program to calculate the input data obtained from the I/O module 13 , and provides the calculation result to the I/O module 13 as output data, thereby controlling the external device 14 .

The external device 14 is, for example, various sensors, motors, recording devices, and the like. The external device 14 performs detection or drive of data, input and output of data, and the like based on control signals and the like from the I/O module 13 .

Here, the reference values may be set in advance in the processor module 11a, the processor module 11b, and the processor module 11c, respectively, or may be set by an externally connected compiling device 15 (setting device).

The compiling device 15 can be implemented by adding a function of communicating with the processor module 11 and setting a reference value to a PC (Personal Computer) used by a user, etc., but it is not limited thereto, and may be a dedicated one. Set up the device. Thereby, the reference value (processing cycle) can be adjusted arbitrarily for each user.

Here, in the above example, a multiprocessor was described as an example of the signal synchronization system 10, but the signal synchronization signal system 10 only needs to include the first reference signal generation unit 21, the second reference signal generation unit 31, the system overhead The counting unit 34 , the counter value acquisition unit 35 , the synchronization determination unit 36 , and the synchronization correction unit 37 are sufficient.

In addition, the application example of the signal synchronization system 10 is not limited to multiprocessors, and can also be applied to, for example, a timer synchronization system in which the master device side is set as a transmission station of a digital signal that transmits date/time information of an atomic clock, On the other hand, the slave device side is set as an electronic clock.

(Example of Hardware Configuration of Processor Module 11)

Next, an example of the hardware configuration of the processor module 11 will be described with reference to the drawings. FIG. 2 is a diagram showing an example of a hardware configuration of the processor module 11 . The processor module 11 shown in FIG. 2 has an input unit 41 , an output unit 42 , a CPU 43 , an FPGA 44 , a memory 45 , and an external interface 46 , and these components are connected by a common bus B.

The input unit 41 inputs various operation signals such as execution of a program from a user or the like. In addition, the input unit 41 may include, for example, a pointing device such as a keyboard, a mouse, or a touch panel for the user to operate, and may include a voice input device when input is performed by voice or the like.

The output unit 42 has a display, and displays various windows, data, etc. necessary for the operation of the processor module 11 performing the processing in this embodiment, and displays the execution progress and results of the control program executed by the CPU 43 .

The CPU 43 controls the processing of the entire processor module 11 based on a control program such as an OS (Operating System) and an execution program stored in the memory 45 to realize each processing in this embodiment, such as various calculations. , Input and output of data with each hardware component, etc. In addition, the CPU 43 cooperates with the memory 45 to substantially perform the functions of the above-mentioned first calculation unit 22, second calculation unit 32, counter value acquisition unit 35, synchronization determination unit 36, and synchronization correction unit 37, and incorporates the first reference signal Generating part 21 , second reference signal generating part 31 . In addition, various information and the like required in the process of executing the program can also be obtained from the memory 45 , and the execution results and the like are stored in the memory 45 .

The FPGA (Field-Programmable Gate Array: Field Programmable Gate Array) 44 is an integrated circuit in which logic circuits can be rewritten. The FPGA 44 is composed of various logic circuits that assist the CPU 43 , and in the present embodiment, particularly functions as the interval counting unit 33 and the overhead counting unit 34 . However, the interval counting unit 33 may be processed by software.

The memory 45 stores execution programs and the like read by the CPU 43 . In addition, the memory 45 is constituted by ROM (Read Only Memory: Read Only Memory), RAM (Random Access Memory: Random Access Memory), and the like. In addition, the memory 45 may have storage means such as a hard disk as an auxiliary storage device. Moreover, the memory 45 stores the execution program in this embodiment, the control program installed in a computer, etc., and performs input and output as needed. In addition, the memory 45 corresponds to the above-mentioned storage units 23 , 38 and the like.

The external interface 46 transmits and receives data and control signals to and from other processor modules 11 via the transmission bus 12 and the like. In addition, the external interface 46 also transmits and receives data and control signals to and from the connected I/O module 13 .

With the hardware configuration described above, the synchronization correction processing in this embodiment can be executed. In addition, by installing and executing the program, the synchronization correction process in this embodiment can be easily realized by using a general-purpose personal computer or the like.

Next, an example of synchronization correction processing in Embodiment 1 will be described below.

(Example of synchronization correction processing in Embodiment 1)

3 to 5 are sequence diagrams (Part 1 to Part 3) for explaining an example of synchronization correction processing in the first embodiment. In the examples shown in FIGS. 3 to 5 , examples of synchronization of count values between the master processor module 11 a and the slave processor module 11 b are shown. In addition, although the reference value (processing cycle) in Embodiment 1 is set to 1000 μs, the present invention is not limited thereto, and the setting may be appropriately changed using, for example, the compiler device 15 described above.

In FIG. 3 , the first reference signal generation unit 21 of the main processor module 11 a counts. If the count value reaches the reference value at time (1) in FIG. 3 , the first reference signal is output. Then, the first computing unit 22 executes predetermined processing based on the first reference signal. In FIG. 3 , the area of the shaded triangle represents the change of the count value. As time goes by, the count value increases, and if the count target (such as a reference value) is reached, it is reset.

In addition, the second reference signal generator 31 of the slave processor module 11b counts. If the count value reaches the reference value at time (2) in FIG. 3 , the second reference signal is output. Then, the second computing unit 32 executes predetermined processing based on the second reference signal. Accordingly, the master processor module 11a and the slave processor module 11b execute predetermined processing based on the independent first reference signal and second reference signal, respectively.

In addition, in the slave processor module 11b, the interval count unit 33 counts, and when the count value reaches the correction processing interval value ((3) in FIG. 3 ), a correction processing start signal is generated. Preparations for synchronous correction processing are started based on the correction processing start signal.

The first reference signal generated in the master processor module 11a is sent to the slave processor module 11b as an interrupt signal. The slave processor module 11b receives the first reference signal as an interrupt, and starts the synchronization correction process by software ((4) in FIG. 3 ). At the same time, the overhead counting unit 34 of the slave processor module 11b clears the count value of the counter constituted by the hardware and restarts ((5) in FIG. 3 ). Next, when preparations for the synchronous correction process are completed, at time (6) in FIG. The counting unit 34 acquires a count value ((8) in FIG. 3 ).

The synchronization determination unit 36 converts the count value supplied from the count value acquisition unit 35 into time. Here, for example, 300 μs is obtained from the count value of the second reference signal generation unit 31 , and 300 μs is obtained from the count value of the overhead count unit 34 . Thereby, the overhead from the start of interruption of the first reference signal to the acquisition of the count value in the synchronization correction process can be measured, and the count value of the second reference signal generator 31 at that point can be acquired. In the case where the first reference signal is synchronized with the second reference signal, the count values should be equal.

The synchronization determination unit 36 compares the count value (300 μs) of the second reference signal generation unit 31 acquired by the count value acquisition unit 35 with the count value (300 μs) of the overhead counter unit 34 . In this case, since the two values are equal, the synchronization determination unit 36 determines that the first reference signal is synchronized with the second reference signal.

Since the synchronization determination unit 36 determines that the first reference signal is synchronized with the second reference signal, the synchronization correction unit 37 sets a reference value of 1000 μs in the second reference signal generation unit 31 as usual (the second reference signal is generated at this time). Part 31 does not restart). Then, since the count value reaches the reference value of 1000 μs at time (9) in FIG. 3 , the second reference signal generator 31 is restarted.

In addition, although the 2nd reference signal generation part 31 is built in the said CPU43, in this embodiment, it is not limited to this, You may provide separately from CPU43.

Incidentally, it should be noted that the synchronization correction processing shown in FIG. 3 includes the processing of the programs of the counter value acquisition unit 35 , the synchronization determination unit 36 , and the synchronization correction unit 37 .

Fig. 4 shows the case where the counter of the slave processor module 11b is delayed by 3 μs compared to the counter of the master processor module 11a.

In FIG. 4, the interval counting unit 33 of the slave processor module 11b counts, and when the count value reaches the correction processing interval value ((1) in FIG. 4 ), a correction processing start signal is generated. Preparations for synchronous correction processing are started based on the correction processing start signal.

Since the count value reaches the reference value, the first reference signal generator 21 of the main processor 11 a outputs the first reference signal every 1000 μs. After generating the correction processing start signal, the slave processor module 11b receives the first reference signal as an interrupt, and starts the synchronization correction processing by software ((2) in FIG. 4 ). At the same time, the overhead counting unit 34 of the slave processor module 11b clears the count value of the counter constituted by the hardware and restarts ((3) in FIG. 4 ). Next, when preparations for the synchronous correction process are completed, at time (4) in FIG. The overhead counting unit 34 acquires a count value ((6) in FIG. 4 ).

The synchronization determination unit 36 converts the count value supplied from the count value acquisition unit 35 into time. Here, for example, 297 μs is obtained from the count value of the second reference signal generation unit 31 , and 300 μs is obtained from the count value of the overhead count unit 34 . The synchronization determination unit 36 compares the two count values and determines that the first reference signal and the second reference signal are not synchronized because the two count values are different.

Since the synchronization determination unit 36 determines that it is out of synchronization, the synchronization correction unit 37 sets a temporary reference value in the second reference signal generation unit 31 so that the count value of the second reference signal generation unit 31 is the same as that of the overhead count unit 34. Differences between count values are canceled out. Specifically, the synchronization correcting unit 37 obtains the second reference signal generation unit using the formula "reference value (processing cycle) - (count value of the overhead counter unit 34 - count value of the second reference signal generation unit 31)". The reset value (reset value) of the count value of 31 is set in the second reference signal generator 31 as a temporary reference value. In the case of this example, the temporary reference value is 1000 μs−(300 μs−297 μs)=997 μs. Then, since the count value reaches the temporary reference value of 997 μs at time (7) in FIG. 4 , the second reference signal generation unit 31 restarts. That is, the value obtained by calculating the count value of the overhead counting unit 34 - the count value of the second reference signal generating unit 31 is a synchronization correction value.

Thus, in Embodiment 1, the second reference signal generator 31 can be restarted at approximately the same timing as the output timing of the first reference signal in the next third cycle in the second cycle. Therefore, Embodiment 1 can synchronize the first reference signal and the second reference signal. In addition, in the case of FIG. 4, the reference value after the 3rd cycle is set to 1000 microseconds.

FIG. 5 shows that the counter of the slave processor module 11b is 3 μs earlier than the counter of the master processor module 11a.

In FIG. 5, the interval counting unit 33 of the slave processor module 11b counts, and when the count value reaches the correction processing interval value ((1) in FIG. 5 ), a correction processing start signal is generated. Preparations for synchronous correction processing are started based on the correction processing start signal.

Since the count value reaches the reference value, the first reference signal generator 21 of the main processor module 11 a outputs the first reference signal every 1000 μs. After generating the correction process start signal, the slave processor module 11b receives the first reference signal as an interrupt, and starts the synchronization correction process by software ((2) in FIG. 5 ). At the same time, the overhead counting unit 34 of the slave processor module 11b clears the count value of the counter constituted by the hardware and restarts ((3) in FIG. 5 ). Next, when preparations for the synchronous correction process are completed, at time (4) in FIG. The overhead counting unit 34 acquires a count value ((6) in FIG. 5 ).

The synchronization determination unit 36 converts the count value supplied from the count value acquisition unit 35 into time. Here, for example, 303 μs is obtained from the count value of the second reference signal generation unit 31 , and 300 μs is obtained from the count value of the overhead count unit 34 . The synchronization determination unit 36 compares the two count values and determines that the first reference signal and the second reference signal are not synchronized because the two count values are different.

Since the synchronization determination unit 36 determines that it is out of synchronization, the synchronization correction unit 37 sets a temporary reference value for the second reference signal generation unit 31 so that the count value of the second reference signal generation unit 31 is equal to the count value of the overhead count unit 34 Differences between values are canceled out. Specifically, the synchronization correction unit 37 performs calculations in the same manner as described in FIG. 4 to obtain a temporary reference value, and sets the temporary reference value in the second reference signal generation unit 31 . In the case of this example, the provisional reference value is 1000 μs−(300 μs−303 μs)=1003 μs. Then, since the count value reaches the temporary reference value of 1003 μs at time (7) in FIG. 4 , the second reference signal generation unit 31 restarts. That is, the value obtained by calculating the count value of the overhead counting unit 34 - the count value of the second reference signal generating unit 31 is a synchronization correction value.

Thus, in Embodiment 1, the second reference signal generator 31 can be restarted at approximately the same timing as the output timing of the first reference signal in the next third cycle in the second cycle. Therefore, the signal synchronization system of this embodiment can synchronize the first reference signal and the second reference signal. In addition, the reference value is set to 1000 μs after the third cycle in FIG. 5 . As described above, in Embodiment 1, regardless of whether the counter (timer) of the slave processor module 11b is delayed or ahead of the counter (timer) of the master processor module 11a, the The counters are synchronized.

(Sequence example of signal synchronization method)

FIG. 6 is a diagram showing an example of a rough sequence of a signal synchronization method. In the example of FIG. 6 , for convenience of description, the synchronization using the master processor module 11a and the slave processor module 11b is described, but this embodiment is not limited thereto, and multiple slave processor modules can be connected to one The main processor modules are synchronized.

In the counter synchronization process of FIG. 6, first, the first reference signal generator 21 of the main processor module 11a generates a first reference signal (S01), and the second reference signal generator 31 of the slave processor module 11b generates a second reference signal. signal (S02). Also, this processing works periodically by hardware. In addition, the master processor module 11a also transmits the first reference signal obtained in the process of S01 to the slave processor module 11b. Therefore, the slave processor module 11b is always in a state capable of receiving the first reference signal.

In addition, the interval counting unit 33 of the slave processor module 11b counts the correction processing interval, and when the count value reaches the correction processing interval value, a correction processing start signal is generated to start preparations for the synchronous correction processing (S03).

If after the count value of the interval counter 33 reaches the correction processing interval value, the first reference signal (S04) sent by the main processor module 11a is received from the processor module 11b, then the synchronization correction process is started by software (S05) , and at the same time restart the system overhead counting unit 34 (S06). Then, the count value acquisition unit 35 acquires two count values of the second reference signal generation unit 31 and the overhead count unit 34 (S07), and the synchronization determination unit 36 performs a synchronization determination based on the two count values (S08). When it is judged that it is out of synchronization, the synchronization correction unit 37 performs synchronization correction (S09).

Accordingly, predetermined signals can be synchronized with high precision while suppressing the processing load.

(Implementation 2: Node Synchronization System)

The second embodiment is characterized in that the synchronization correction process is executed including the delay time caused by the transmission bus 12 in the first embodiment described above. FIG. 7 is a diagram showing an example of a schematic configuration of a node synchronization system in Embodiment 2. FIG. The node synchronization system 50 shown in FIG. 7 is an example that performs counter synchronization among a plurality of nodes such as nodes 51a to 51c.

The node synchronization system 50 has: a plurality of nodes 51a-51c (hereinafter referred to as "nodes 51" as needed), a communication path (communication network) 52, and an I/O (input-output) module 53 (referred to as 53a-53d in FIG. 7 shown), an external device 54 (shown as 54a-54d in FIG. 7 ), and a compiling device 55. That is, the node synchronization system 50 connects the master node 51a and the slave nodes 51b and 51c via the communication path 52 which is a communication network.

Here, for the convenience of description, the node 51a is used as the master node, and the nodes 51b and 51c are used as the slave nodes. The inherent structure of each node is described, but it is not limited to this. The structure of also has a structure of slave nodes, so that each node can be both a master node and a slave node. In addition, in Embodiment 2, it is assumed that a transmission delay time occurs in the communication path 52 .

Here, differences between Embodiment 2 (FIG. 7) and Embodiment 1 (FIG. 1) will be described first. The master control node 51a corresponds to the master processor module 11a in the first embodiment, and the slave nodes 51b and 51c correspond to the slave processor modules 11b and 11c in the first embodiment. In addition, the compiler device 55 is substantially equivalent to the compiler device 15 in Embodiment 1, and the I/O modules 53a to 53d are substantially equivalent to the I/O modules 13a to 13d in Embodiment 1. In addition, the external devices 54a to 54d are substantially equivalent to the external devices 14a to 14d in the first embodiment. Therefore, in the following description, the description of the same configuration as that of Embodiment 1 will be omitted.

The master node 51a has a first reference signal generation unit 61 (corresponding to the first reference signal generation unit 21 in the first embodiment), a first computing unit 62 (corresponding to the first computing unit 22 in the first embodiment), and a storage unit 63 (corresponding to the storage unit 23 in Embodiment 1), an interval counting unit 64 (corresponding to the interval counting unit 33 in Embodiment 1), a transmission delay time notification unit 65 , and a synchronization frame notification unit 66 .

The main difference between the master control node 51a and the master processor module 11a in the first embodiment is that the interval counting unit 33 provided in the slave processor module 11b in the first embodiment is provided as the interval counting unit 64, and a newly added A transmission delay time notification unit 65 and a synchronization frame notification unit 66 are provided. Therefore, in the following description, the main part of Embodiment 2 will be described, and the description of the same operations as in Embodiment 1 will be omitted.

An example of Embodiment 2 will be described below. In Embodiment 2, the interval counting unit 64 counts and presets a correction processing interval value corresponding to the correction processing interval for synchronous processing, and when the count value reaches the correction processing interval value, generates a correction Handle the start signal. In addition, since the correction processing interval value is substantially equal to Embodiment 1, description thereof is omitted here.

In addition, here, the correction processing interval is measured on the side of the master node 51a, but the correction processing interval may be measured on the side of the slave node 51b. In this case, when the counter value reaches the correction processing interval value in the slave node 51b, a correction processing start signal is transmitted to the master node 51a, and the synchronous correction processing is started.

After receiving the correction process start signal, the transmission delay time notification unit 65 of the master node 51a transmits a transmission delay time request frame to the slave nodes 51b and 51c in order to calculate the transmission delay time. The transmission delay time request frame has substantially the same format as a synchronization frame described later, but is different from the data of a predetermined portion (for example, a command portion) in the synchronization frame. The transmission delay time request frame is transmitted in synchronization with the first reference signal generated by the first reference signal generator 61 .

Next, the transmission delay time notification unit 65 receives a reception completion frame from the slave node that responded to the transmission delay time request frame. Then, the transmission delay time notification unit 65 calculates the round-trip transmission delay time between the master node 51a and the slave nodes 51b and 51c based on the difference between the time when the response frame is received and the time when the transmission delay time request frame is transmitted. . Then, the transmission delay time notification unit 65 transmits a transmission delay time notification frame including the calculated round-trip transmission delay time to the slave nodes 51b, 51c in synchronization with the next first reference signal, thereby notifying the slave nodes 51b, 51c The delay time generated by the communication path 52 is notified.

After notifying the round-trip delay time, the master node 51a transmits a pre-prepared synchronization frame to the slave nodes 51b and 51c via the communication path 52 based on the first reference signal (synchronized with the first reference signal). Note that this processing is executed by the synchronization frame notification unit 66 . As will be described in detail later, the synchronization frame is a synchronization reference for matching the count value of the second reference signal generator 71 of the slave nodes 51b and 51c with the count value of the first reference signal generator 61 of the master node 51a. Signal.

Next, the slave nodes 51b and 51c will be described. The slave nodes 51b and 51c include: a second reference signal generating unit 71 (corresponding to the second reference signal generating unit 31 in Embodiment 1), a second computing unit 72 (corresponding to the second computing unit 32 in Embodiment 1), a system The overhead counting unit 74 (corresponding to the system overhead counting unit 34 in Embodiment 1), the counter value acquiring unit 75 (corresponding to the counting value acquiring unit 35 in Embodiment 1), the synchronization judgment unit 76 (corresponding to the synchronization judgment in Embodiment 1 unit 36), synchronization correction unit 77 (corresponding to synchronization correction unit 37 of Embodiment 1), storage unit 78 (corresponding to storage unit 38 of Embodiment 1), reception completion notification unit 79 and frame reception unit 80. In addition, the CPU 43 incorporates a second reference signal generation unit 71 . Since the configurations of the slave nodes 51b and 51c are the same, in the following description, the slave node 51b will be used for description, and the description of the slave node 51c will be omitted.

The main difference from the processor module 11b of the first embodiment is that the synchronization determination unit 76 is different from the synchronization determination unit 36 of the first embodiment, and a reception completion notification unit 79 and a frame reception unit 80 are added. However, since other components are substantially the same as those in Embodiment 1, description thereof will be omitted here. Next, the synchronization correction process of the slave node 51b including the transmission delay time of the communication path 52 will be described.

The reception completion notification unit 79 receives the transmission delay time request frame from the master control node 51a, and transmits a reception completion frame to the master control node 51a based on the transmission delay time request frame.

The frame reception unit 80 receives the transmission delay time notification frame transmitted from the master node 51a, and saves the round-trip transmission delay time (value) included in the frame to the memory 45 and the like. Thus, the slave node 51b acquires the round-trip transmission delay time between the master node 51a and the slave node 51b from the master node 51a.

The slave node 51 b which has obtained the round-trip transmission delay time from the master node 51 a receives the synchronization frame, and generates an interrupt in the second computing unit 72 . The second calculation unit 72 having received the interrupt starts the synchronization correction process described later. Also, in the present embodiment, even if a synchronization frame is received without obtaining the round-trip delay time, it is of course possible to set the round-trip delay time to zero (0) to start the synchronization correction process. In addition, considering the speed at which an interrupt is sent to the second computing unit 72 after receiving a synchronization frame, it is preferable to use hardware logic such as FPGA 44 as a synchronization frame receiving unit, although not shown in the figure.

In addition, the overhead counting unit 74 measures an overhead value starting from the reception of the above-mentioned synchronization frame until execution of the synchronization correction process. Specifically, the overhead counting unit 74 functions as a hardware counter (timer) that restarts after receiving a synchronization frame.

The count value acquisition unit 75 acquires the count value of the second reference signal generation unit 71 and the count value of the overhead counter unit 74 at the start time of actually executing the synchronization correction process based on the reception of the synchronization frame.

The synchronization determination unit 76 divides the round-trip transmission delay time by 2 to obtain the one-way transmission delay time of the communication path 52, and further calculates the one-way transmission delay time and the elapsed time of the counted value of the overhead counting unit 74. The composite delay time obtained by adding the converted values. Then, the synchronization determination unit 76 compares the obtained total delay time with the time-converted value of the count value of the second reference signal generation unit 71 acquired by the count value acquisition unit 75 . When the comparison result is equal, the synchronization determination unit 76 determines that the first reference signal is synchronized with the second reference signal, and when they are not equal, the synchronization determination unit 76 determines that the first reference signal is not synchronized with the second reference signal. Here, synchronization means that the count value of the first reference signal generator 61 is equal to the count value of the second reference signal generator 71 .

In addition, the synchronization judging unit 76 may, of course, compare the count values of the respective counters in the same manner as the synchronization judging unit 36 of the first embodiment in terms of time, thereby judging whether it is synchronous or not.

In Embodiment 2, the synchronization correction unit 77 sets a reference value in the second reference signal generation unit 71 when the synchronization determination unit 76 determines that the first reference signal is synchronized with the second reference signal at every correction processing interval. In addition, when it is determined that the first reference signal and the second reference signal are out of synchronization, a value obtained by canceling the difference between the count value of the second reference signal generator 71 and the total delay time value is obtained. Specifically, the synchronization correction unit 77 subtracts the total delay time value from the count value of the second reference signal generation unit 71 acquired by the count value acquisition unit 75 to obtain a synchronization correction value. Next, the synchronization correction unit 77 subtracts the obtained synchronization correction value from the reference value, and sets the subtracted value as a new reference value in the second reference signal generation unit 71 . This new reference value is temporarily set (temporary reference value) with respect to the reference value (default reference value) set in the second reference signal generation unit 71 when the synchronization determination unit 76 determines that it is synchronous, and is used for The timing value of the second reference signal generator 71 is corrected.

In addition, in this embodiment, of course, when a default reference value is set in the second reference signal generating unit 71 and synchronization is maintained, the default reference value may not be rewritten thereafter.

Thus, in the present embodiment, it is possible to perform synchronization correction processing taking into account the influence of the transmission delay time when the synchronization reference signal (synchronization frame) is notified via the communication path 52 . That is, in Embodiment 2, it is possible to correct the count value including the transmission delay time between nodes and the overhead of the slave nodes 51b and 51c, thereby achieving highly accurate synchronization between nodes.

(Example of synchronization correction processing in Embodiment 2)

8 to 10 are sequence diagrams for explaining an example of synchronization correction processing in Embodiment 2, and are examples of synchronization of count values between the master node 51a and the slave node 51b. In addition, the reference value (processing cycle) in Embodiment 2 is set to 1000 μs as in Embodiment 1, and this reference value can be appropriately changed by the compiler device 55 .

In FIG. 8 , the first reference signal generation unit 61 of the master node 51 a counts. When the count value reaches the reference value at time (1) in FIG. 8 , a first reference signal is output. Then, the first computing unit 62 executes predetermined processing based on the first reference signal.

In addition, the second reference signal generator 71 of the slave node 51b counts. When the count value reaches the reference value at time (2) in FIG. 8 , a second reference signal is output. Then, the second computing unit 72 executes predetermined processing based on the second reference signal. Accordingly, in the master node 51a and the slave node 51b, predetermined processing is executed based on the independent first reference signal and second reference signal, respectively.

In addition, in the main processor module 51a, the interval counting unit 64 counts, and when the count value reaches the correction processing interval value ((3) in FIG. 8 ), a correction processing start signal is generated. The synchronization correction process in the master control node 51a is started in accordance with the correction process start signal.

After the start of the synchronization correction process, the transmission delay time notification unit 65 of the master node 51a transmits a transmission delay time request frame in order to calculate the transmission delay time ((4) in FIG. 8 ). When the reception completion notification unit 79 of the slave node 51b receives the transmission delay time request frame from the master control node 51a, it transmits a reception completion frame to the master control node 51a based on the transmission delay time request frame ((5) in FIG. 8 ).

Next, the transmission delay time notification unit 65 of the master node 51a calculates the round-trip transmission delay time between the master node 51a and the slave node 51b based on the received frame, and transmits transmission delay time notification frame ((6) of FIG. 8). When the frame reception unit 80 of the slave node 51b receives the transmission delay time notification frame, it saves the round-trip transmission delay time (value) included in the frame to the memory 45 or the like ((7) in FIG. 8 ).

After the start of the synchronization correction process, the synchronization frame notification unit 66 of the master node 51a transmits a synchronization frame as an interrupt signal to the slave node 51b ((8) in FIG. 8 ). Then, the slave node 51b receives the synchronization frame at the time of (9) in FIG. 8 via the one-way transmission delay time (200 μs) of the communication path 52, and starts the synchronization correction process by the software in the slave node 51b. In addition, when the synchronization frame is received, the hardware counter of the overhead counting unit 74 is cleared and restarted ((10) in FIG. 8 ).

Next, when preparations for the synchronous correction process are completed, at time (11) in FIG. The overhead counting unit 74 acquires a count value ((13) in FIG. 8 ).

Next, the count value acquiring unit 75 refers to the count value of the second reference signal generating unit 71 to perform time conversion to obtain 400 μs. Next, the synchronization judging unit 76 calculates a one-way transmission delay time of 200 μs from the round-trip transmission delay time (400 μs), adds the obtained transmission delay time to 200 μs obtained by converting the count value of the system overhead counting unit 74 over time, Thus, the integrated delay time of 400μs is obtained. Then, the synchronization determination unit 76 compares the total delay time of 400 μs with the time-converted 400 μs obtained by the count value acquisition unit 75 from the count value of the second reference signal generation unit 71. Since the two are equal, it is judged to be the second delay time. The 1st reference signal is synchronized with the 2nd reference signal.

Since the synchronization determination unit 76 determines that the first reference signal is synchronized with the second reference signal, the synchronization correction unit 77 sets a reference value of 1000 μs in the second reference signal generation unit 71 as usual (the second reference signal generation unit 71 Set the time without restarting). Then, since the count value reaches the reference value of 1000 μs at time (14) in FIG. 8 , the second reference signal generator 71 restarts.

FIG. 9 shows the case where the counter of the slave node 51b is delayed by 3 μs from the counter of the master node 51a.

In FIG. 9, after the count value of the interval counting unit 64 of the master node 51a reaches the correction processing interval value and the synchronization correction process is started, the frame receiving unit 80 of the slave node 51b notifies the round-trip transmission included in the transmission delay time frame. The processing until the delay time (value) is evacuated to the memory 45 and the like is substantially the same as the processing in FIG. 8 , and thus description thereof will be omitted here.

After the start of the synchronization correction process, the synchronization frame notifying unit 66 of the master node 51a transmits a synchronization frame as an interrupt signal to the slave node 51b at time point (1) of FIG. 9 . Then, the slave node 51b receives the synchronization frame at the time (2) of FIG. 9 via the one-way transmission delay time (200 μs) of the communication path 52, and starts the synchronization correction process by the software in the slave node 51b. In addition, the counter of the overhead counting unit 74 is cleared and restarted when the synchronization frame is received ((3) in FIG. 9 ).

Next, when preparations for the synchronous correction process are completed, at time (4) in FIG. The overhead counting unit 74 acquires a count value ((6) in FIG. 9 ).

Next, the count value acquiring unit 75 refers to the count value of the second reference signal generating unit 71 to perform time conversion to obtain 397 μs. Next, the synchronization judging unit 76 calculates a one-way transmission delay time of 200 μs from the round-trip transmission delay time (400 μs), adds the obtained transmission delay time to 200 μs obtained by converting the count value of the system overhead counting unit 74 over time, Thus, the integrated delay time of 400μs is obtained. Then, the synchronization judging unit 76 compares the total delay time of 400 μs with the count value of the second reference signal generating unit 71 obtained by the count value acquiring unit 75, which is 397 μs after time conversion, and since the two are not equal, it is judged as The first reference signal is not synchronized with the second reference signal.

Since the synchronization determination unit 76 determines that the first reference signal and the second reference signal are out of synchronization, the synchronization correction unit 77 sets a temporary reference value in the second reference signal generation unit 71 . Specifically, the synchronization correcting unit 77 obtains the restart value of the second reference signal generating unit 71 using the formula “reference value (processing cycle)−(total delay time−count value of the second reference signal generating unit 71)” ( reset value), and set the calculated count value in the second reference signal generation unit 71 as a temporary reference value. In the case of this example, the provisional reference value is 1000 μs−(400 μs−397 μs)=997 μs. Then, since the count value reaches the temporary reference value of 997 μs at time (7) in FIG. 9 , the second reference signal generation unit 71 restarts. That is, the value obtained by integrating the delay time - the count value of the second reference signal generating unit 71 is a synchronous correction value.

FIG. 10 shows the case where the counter of the slave node 51b is ahead of the counter of the master node 51a by 3 μs.

In FIG. 10, after the count value of the interval counting unit 64 of the master node 51a reaches the correction processing interval value and the synchronization correction process is started, the frame reception unit 80 of the slave node 51b notifies the transmission delay time to the round-trip transmission included in the frame. The processing until the delay time (value) is evacuated to the memory 45 and the like is substantially the same as the processing in FIG. 8 and FIG. 9 , and therefore description thereof will be omitted here.

After the start of the synchronization correction process, the synchronization frame notifying unit 66 of the master node 51a transmits a synchronization frame as an interrupt signal to the slave node 51b at time point (1) of FIG. 10 . Then, the slave node 51b receives the synchronization frame at the time (2) of FIG. 10 via the one-way transmission delay time (200 μs) of the communication path 52, and starts the synchronization correction process by the software in the slave node 51b. In addition, the counter of the overhead counting unit 74 is cleared and restarted when the synchronization frame is received ((3) in FIG. 10 ).

Next, when preparations for the synchronous correction process are completed, at time (4) in FIG. The overhead counting unit 74 acquires a count value ((6) in FIG. 10 ).

Next, the count value acquiring unit 75 refers to the count value of the second reference signal generating unit 71 to perform time conversion to obtain 403 μs. Next, the synchronization judging unit 76 obtains the one-way transmission delay time of 200 μs from the round-trip transmission delay time (400 μs), and converts the obtained one-way transmission delay time and the counted value of the system overhead counting unit 74 into 200 μs over time. Added together, the overall delay time of 400μs is obtained. Then, the synchronization judging unit 76 compares the total delay time of 400 μs with the time-converted count value of the second reference signal generating unit 71 acquired by the count value acquiring unit 75, which is 403 μs. Since the two are not equal, it is determined that The first reference signal is not synchronized with the second reference signal.

Since the synchronization determination unit 76 determines that the first reference signal and the second reference signal are out of synchronization, the synchronization correction unit 77 sets a temporary reference value in the second reference signal generation unit 71 . In the case of this example, the provisional reference value is 1000 μs−(400 μs−403 μs)=1003 μs. Then, since the count value reaches the temporary reference value of 1003 μs at time (7) in FIG. 10 , the second reference signal generation unit 71 restarts.

In addition, in the case of the example in FIG. 9 and FIG. 10 , in the third cycle, the counter on the master side is synchronized with the counter on the slave side, so after that, the synchronization correction unit 77 sets the original reference value 1000 μs to the second cycle. Reference signal generation unit 71 (the second reference signal generation unit 71 is not restarted at the set time). Then, the second reference signal generator 71 restarts when the count value reaches the reference value of 1000 μs. That is to say, in Embodiment 2, with respect to the third cycle, the counter on the slave side can be restarted at approximately the same timing as the restart of the counter on the master side in the next fourth cycle, so the counter on the master side can be reset. The value of matches the value of the counter on the slave side to an approximately equal value.

In addition, the synchronization correction processing includes the processing of the program of the counter value acquisition part 75, the synchronization determination part 76, and the synchronization correction part 77 similarly to Embodiment 1.

In addition, although the description has been made on the premise that the second reference signal generation unit 71 of the slave node 51b is incorporated in the CPU 43, the present invention is not limited thereto. That is, the second reference signal generation unit 71 may be realized separately from the CPU 43 . However, since the second reference signal generation unit 71 is built in the CPU 43 , the second reference signal generation unit 71 cannot be reset by hardware using a predetermined signal generated outside the CPU 43 . In other words, the second reference signal generator 71 is a counter in which a program controls its operation. Therefore, in the present embodiment, it is necessary to use a program to execute the reset processing (restart processing) of the second reference signal generation unit 71, and the system overhead is related to the synchronization error. Therefore, in the present embodiment, a configuration for measuring system overhead is required (the same applies to Embodiment 1).

In addition, in Embodiment 2, the synchronization correction process is an interrupt process that is started upon reception of a synchronization frame.

In addition, in the above description, the slave node 51b acquires and holds the round-trip delay time from, for example, the master node 51a, and effectively utilizes the held round-trip delay time in the synchronization correction process. In addition, there is a method in which the master node 51a includes the round-trip transmission delay time in the synchronization frame and sends it to the slave node 51b, and the slave node 51b that has received the synchronization frame uses the round-trip transmission time included in the synchronization frame. Accordingly, the master node 51a can appropriately notify the slave node 51b of the round-trip delay time according to the situation, and therefore the slave node 51b can appropriately use the round-trip delay time according to the situation.

In addition, although the case where the transmission delay time notification part 65 notifies the slave node 51b of the round-trip transmission delay time was demonstrated, it is not limited to this. For example, the transmission delay time notification unit 65 may divide the calculated round-trip transmission delay time by 2 to obtain the one-way transmission delay time, and notify the slave node 51b of the obtained one-way transmission delay time. In this case, the synchronization determination unit 76 of the slave node 51b may use the obtained one-way transmission delay time as it is to obtain the total delay time.

As described above, in Embodiment 2, it is possible to synchronize the first reference signal and the second reference signal including the signal propagation delay time caused by the communication path 52 .

(Procedure for notification of transmission delay time in synchronization correction processing)

Next, the notification procedure of the transmission delay time in the above-mentioned synchronization correction processing will be described. FIG. 11 is a diagram for explaining an example of a notification procedure of a transmission delay time in Embodiment 2. FIG. In addition, in the example of FIG. 11, the said master node 51a and slave nodes 51b and 51c are provided, and each node 51 is connected via the communication path 52 in the state which can transmit and receive a signal. In addition, in the following description, an example is shown in which the master control node 51 a acquires the transmission delay time of a signal generated by the communication path 52 between the nodes 51 .

The squares shown in FIG. 11 represent frames, the squares above the lines of the nodes 51 represent transmission frames, and the squares below the lines represent reception frames. In addition, the frame shown in FIG. 11 has: a transmission delay time request frame 81 (shown as "REQ*" in FIG. A reception completion frame 82 ("REC*" in FIG. 11), a transmission delay time notification frame 83 ("SET*" in FIG. 11), and a response frame 84 to the transmission delay time notification frame 83 ("SET*" in FIG. 11 ANS*").

In the example of FIG. 11 , the master node 51 a broadcasts a transmission delay time request frame 81 b (REQb) for the slave node 51 b onto the communication path 52 according to the master node synchronization reference. At this time, the transmission delay time request frame 81b includes information (target node information) indicating the content of the transmission delay time request to the slave node 51b.

The broadcast transmission delay time request frame 81b is received by each of the slave nodes 51b and 51c after a predetermined transmission delay time via the communication path 52 . Furthermore, in the example of FIG. 11 , the slave node 51b receives the transmission delay time request frame 81b at delay time D1 according to the master node synchronization reference, and the slave node 51c receives the transmission delay time request frame 81b at delay time D2 according to the master node synchronization reference .

Here, each of the slave nodes 51b and 51c confirms the above-mentioned target node information included in the transmission delay time request frame 81b. Thus, since the transmission delay time request frame 81b is a request for the slave node 51b, only the slave node 51b broadcasts the transmission reception completion frame 82b (RECb) to the master node 51a. In this case, the received frame 82b includes information (target node information) indicating the content of the received frame directed to the master node 51a.

The transmitted reception completion frame 82 b is received by the master node 51 a and the slave node 51 c via the communication path 52 . Next, the master node 51a and the slave node 51c confirm the above-mentioned target node information included in the received frame 82b. As described above, the reception completion frame 82b is a frame for the master control node 51a. Therefore, the master node 51a sets the transmission delay time for the slave node 51b based on the time information from the transmission of the transmission delay time request frame 81b transmitted according to the master node synchronization standard to the reception of the reception completion frame 82b. . In addition, the transmission delay time set here may be a round-trip transmission delay time for a predetermined signal to go back and forth between the master node 51 a and the slave node 51 b via the communication path 52 , or may be a one-way transmission delay time.

Also, the master node 51a generates a transmission delay time notification frame 83b (SETb) for notifying the slave node 51b of the set transmission delay time, and broadcasts the generated transmission delay time notification frame according to the master node synchronization standard. 83b. In addition, the above-mentioned target node information is included in the transmission delay time notification frame 83b.

The broadcast transmission delay time notification frame 83b is received by each of the slave nodes 51b and 51c after a predetermined transmission delay time via the communication path 52, similarly to the transmission delay time request frame 81b described above.

At this time, the slave node 51b determines from the received target node information of the transmission delay time notification frame 83b that it is information aimed at its own node, and then includes the transmission delay time included in the frame, the above-mentioned system overhead time, etc. Synchronization correction processing of Embodiment 2 within. Also, the master control node 51b generates a response frame 84b (ANSb) to the transmission delay time notification frame 83b, and broadcasts the generated response frame 84b. At this time, the response frame 84b includes information indicating the content of the frame directed to the master node 51a (target node information), information indicating that the synchronization correction process has been completed, and the like.

The transmitted response frame 84b is received by the master node 51a and the slave node 51c via the communication path 52 in the same way as the reception completion frame 82b described above. Next, the master node 51a and the slave node 51c confirm the above-mentioned target node information included in the response frame 84b. As described above, the response frame 84b is a frame for the master control node 51a. Therefore, the master node 51a can grasp the completion of the synchronization correction process by the response frame 84b from the slave node 51b. In addition, although the slave node 51c has received the transmission delay time request frame 81b (REQb), the reception completion frame 82b (RECb), the transmission delay time notification frame 83b (SETb), and the response frame 84b (ANSb), none of them are directed to the own node. frame, so the received frame is discarded.

The contents so far are all the steps of notifying the transmission delay time to the slave node 51b. Therefore, the master node 51a similarly notifies the slave node 51c of the transmission delay time.

Specifically, in the example of FIG. 11 , the master node 51 a broadcasts a transmission delay time request frame 81 c (REQc) for the slave node 51 c onto the communication path 52 according to the master node synchronization reference. The broadcasted transmission delay time request frame 81c is received by each of the slave nodes 51b, 51c at the predetermined transmission delay time (D1, D2) via the communication path 52 as described above.

Since the transmission delay time request frame 81c is a request for the slave node 51c, only the slave node 51c broadcasts the transmission reception completion frame 82c (RECc) to the master node 51a. The transmitted reception completion frame 82c is received by the master node 51a and the slave node 51c via the communication path 52 . The reception completion frame 82c is a frame for the master control node 51a. Therefore, the master node 51a sets the transmission delay time for the slave node 51c based on the time information from the transmission of the transmission delay time request frame 81c transmitted according to the master node synchronization standard to the reception of the reception completion frame 82c. . In addition, the transmission delay time set here may be a round-trip transmission delay time for a predetermined signal to go back and forth between the master node 51 a and the slave node 51 c via the communication path 52 , or may be a one-way transmission delay time.

Also, the master node 51a generates a transmission delay time notification frame 83c (SETc) for notifying the slave node 51c of the set transmission delay time, and broadcasts the generated transmission delay time notification frame according to the master node synchronization standard. 83c. The broadcasted transmission delay time request frame 83c is received by the slave nodes 51b, 51c via the communication path 52 at predetermined transmission delay times (D1, D2) like the above transmission delay time request frame 81c.

At this time, as described above, the slave node 51b judges from the target node information of the received transmission delay time notification frame 83c that it is the information for its own node, and compares the transmission delay time included in the frame with the overhead time mentioned above. Synchronization correction processing of Embodiment 2 including etc. Also, the slave node 51c generates a response frame 84c (ANSc) to the transmission delay time notification frame 83c, and broadcasts the generated response frame 84c. At this time, the response frame 84c includes information indicating the content of the frame directed to the master node 51a (target node information), information indicating that the synchronization correction process has been completed, and the like.

The transmitted response frame 84c is received by the master node 51a and the slave node 51c via the communication path 52 in the same way as the reception completion frame 82c described above. Next, the master node 51a and the slave node 51b confirm the above-mentioned target node information included in the response frame 84c. As described above, the response frame 84c is a frame for the master control node 51a. Therefore, the master node 51a can grasp the completion of the synchronization correction process by the response frame 84c from the slave node 51c. In addition, although the slave node 51b has received the transmission delay time request frame 81c (REQc), the reception completion frame 82c (RECc), the transmission delay time notification frame 83c (SETc), and the response frame 84c (ANSc), none of them are directed to the own node. frame, so the received frame is discarded.

In Embodiment 2, the transmission delay time can be notified by sequentially performing the above-described processing on each of the slave nodes 51b and 51c of the communication path 52 .

In addition, the notification step of the transmission delay time is not limited to the above-mentioned steps. For example, a sending counter can be set inside each of the above-mentioned nodes, and the sending counter can be used to control to send the response frame 84 at different times, so that on the communication path 52 and the master control node 51a, there will be no transmission delay time request due to, for example, broadcasting. frame 81, and the slave nodes 51b and 51c that received the transmission delay time request frame 81 transmit a response frame 84 to generate congestion.

In Embodiment 2 above, in a system having a star topology such as Ethernet (registered trademark), for a common memory network using a time-division multiplexing transmission method, the counters of each node can be synchronized, and the entire device can perform Synchronous control matching the moment of control. In addition, in Embodiment 2, the counter for synchronizing can be configured by a counter inside a microcomputer, or a counter based on hardware such as an FPGA. Therefore, in Embodiment 2, for example, a counter synchronized with the master control node 51a at the time of receiving a frame to be transmitted and received and a counter for measuring the processing time of the microcomputer are configured by using hardware such as an FPGA, and the counts are calculated by the microcomputer. value, so that processing errors can be corrected.

Here, in the above-mentioned example, as an example of the node synchronization system 50, the node synchronization between the master and slave nodes has been described, but in this embodiment, it is not limited to this, and it can also be applied to, for example, protection Sampling synchronization techniques in relays, etc.

(Network Transmission System: Schematic Configuration Example)

Here, in Embodiment 2 described above, nodes may be connected by a relay device such as a HUB (hub) such as IEEE802.3u (100BASE-TX) or IEEE802.3ab (1000BASE-T), for example. FIG. 12 is a diagram showing an example of a schematic configuration of a network transmission system including a node synchronization system 50 using a master node 51 a and slave nodes 51 b and 51 c in the second embodiment. The network transmission system 90 shown in FIG. 12 has as an example: the above-mentioned multiple nodes 51 (in the example of FIG. ~91e). In addition, the number, type, and connection method of nodes and relay devices are not limited thereto.

In the example of Fig. 12, the master control node of Fig. 7, i.e. node 51a is set as node A (master control station), and the slave nodes of Fig. 7, i.e. node 51b, node 51c are set as node B, node C (slave station ). In addition, as shown in FIG. 12 , the communication path of the network transmission system 90 is, for example, a star shape having a relay device between the master node 51 a and the slave node 51 b. In addition, the relay device uses a HUB as an example, but this embodiment is not limited thereto, and for example, a router, a repeater, an optical converter, etc. may be used.

In addition, the master control node 51a and the slave nodes 51b and 51c are, for example, programmable controllers (control devices or also called PLCs (Programmable Logic Controllers: Programmable Logic Controllers), and the communication path of the network transmission system 90 is programmable for these The data exchange bus that controller exchanges data between each other.The equipment that is connected to this data exchange bus for example also has PC, server, I/O module, driving device (such as inverter , servo mechanism, etc.) etc.

The network transmission system 90 shown in FIG. 12 is connected to the same HUB 91a as the node 51a and the node 51c, and the node 51b is connected to the node 51a and the node 51c via a fifth-level HUB (relay device).

Here, in a general Ethernet HUB, an interface method called store-and-forward is used. In this case, all transmitted frames are stored in the receive buffer in the HUB, and are transmitted after HUB internal processing (for example, abnormality judgment and destination judgment, etc.).

(Sequence example of node synchronization method)

FIG. 13 is a diagram showing an example of a rough procedure of a node synchronization method. In the example of FIG. 13 , for the convenience of explanation, the synchronization between the master control node 51a and the slave node 51b has been described, but this embodiment is not limited to this, and multiple slave nodes and one master node can Synchronize.

In the node synchronization process of FIG. 13, first, the first reference signal generator 61 of the master node 51a generates a first reference signal (S11), and the second reference signal generator 71 of the slave node 51b generates a second reference signal (S12). ). In addition, this process operates periodically by hardware.

In addition, the interval counting unit 64 of the master node 51a counts the correction processing interval, and when the count value reaches the correction processing interval value, generates a correction processing start signal, and starts the synchronous correction processing (S13).

When the count value of the interval counting unit 64 reaches the correction processing interval value, the synchronization correction process in the master control node 51a is started (S13), and the transmission delay time notification unit 65 of the master control node 51a sends A delay time request frame is transmitted (S14). In addition, the transmission delay time request frame is a frame obtained by changing only a predetermined part of the data contained in the synchronization frame, in other words, it can also be called a synchronization frame. Here, for convenience, it will be described as a "transmission delay time request frame". .

When the reception completion notification unit 79 of the slave node 51b receives the transmission delay time request frame, it generates a reception completion notification and notifies it to the master node 51a (S15).

The transmission delay time notification unit 65 of the master node 51a calculates, for example, a round-trip transmission delay time (S16) when receiving the reception completion notification, and generates a transmission delay time notification including the calculated round-trip transmission delay time, etc. frame (S17), and then transmits the generated transmission delay time notification frame to the slave node 51b via the communication path 52 (S18).

When the frame receiving unit 80 of the slave node 51b receives the transmission delay time notification frame, it saves the round-trip transmission delay time (value) included in the frame to the memory 45 or the like (S19). Then, the synchronization frame notification unit 66 of the master node 51a transmits a synchronization frame as an interrupt signal to the slave node 51b in synchronization with the first reference signal (S20). When the slave node 51b receives the synchronization frame (S21), it starts the synchronization correction process by software (S22), and restarts the overhead counting unit 74 (S23). Then, the count value acquisition unit 75 acquires two count values of the second reference signal generation unit 71 and the overhead count unit 74 (S24), and the synchronization determination unit 76 performs a synchronization determination based on the two count values (S25). When it is judged that it is out of synchronization, the overall delay time is calculated (S26). The overall delay time is, for example, a value obtained by adding the transmission delay time and the overhead value, but is not limited thereto. In addition, the synchronization correction unit 77 of the slave node 51b performs synchronization correction using the calculated total delay time (S27). In addition, in the processing shown in FIG. 13, the slave node 51b may transmit to the master node 51a a response frame indicating that synchronization correction has been completed. In addition, the master control node 51a may perform node synchronization processing on slave nodes other than the slave node 51b connected to the communication path 52 through the above steps.

Here, in this embodiment, a program (node synchronization program) for causing a computer to function as each unit included in the above-mentioned node 51 is generated, and by installing the generated program on a computer or the like, synchronization of the above-mentioned nodes is realized. deal with.

As described above, according to the present embodiment, it is possible to precisely synchronize predetermined signals while suppressing the processing load. Thereby, for example, stabilization of the data exchange period of each node 51 can be achieved. In addition, according to this embodiment, in a system having a star topology such as Ethernet, it is possible to synchronize the timers of each node 51 with respect to a common memory network using a time-division multiplexing transmission method, thereby realizing high-efficiency transmission and data transmission. Efficiency of exchange, stabilization of data exchange cycle, etc.

In addition, this embodiment can be applied to a synchronization method when a series of operations are performed using multiple operations in a large-scale facility such as a steel plant, and can also be widely applied to synchronization between devices in the entire Gigabit Ethernet network. Way.

As mentioned above, although preferred embodiment of this invention was described referring drawings, this invention is not limited to the said embodiment. Those skilled in the art can conceive of various modified examples and corrected examples within the scope described in the claims, and these naturally also belong to the technical scope of the present invention.

In addition, each step of the signal synchronization method and the node synchronization method in this specification does not necessarily have to be processed in time series along the order described in the sequence diagram, and parallel processing or processing using a subroutine may be included.

Industrial Applicability

The present invention relates to a signal synchronization system, a node synchronization system, a signal synchronization method, and a node synchronization method for synchronizing predetermined signals.

Label description

10 Signal Synchronization System

11 processor module

12 transfer bus

13. 53I/O (input and output) module

14, 54 External equipment

15, 55 compilation device

21, 61 1st reference signal generator

22, 62 1st Computing Department

23, 38, 63, 78 Storage

31, 71 Second reference signal generator

32, 72 2nd Computing Unit

34, 74 System overhead counting department

35, 75 Count value acquisition part

36, 76 Synchronous Judgment Unit

37, 77 synchronous correction department

41 Input section

42 output section

43 CPUs

44 FPGAs

45 memory

46 external interface

50 Node Synchronous System

51 nodes

52 communication path

65 Transmission Delay Time Notification Department

66 Synchronization frame notification unit

79 Receive Completion Notification Department

80 frame receiving unit

81 Transmission Delay Time Request Frame

82 Receive complete frame

83 Transmission delay time notification frame

84 Acknowledgment frame

90 network transmission system

91 HUB (relay device)

Claims (18)

1. a kind of signal synchronizing system, believes comprising the primary module acted according to the 1st reference signal and according to the 2nd benchmark Number slave module acted, and make the 2nd reference signal synchronous with the 1st reference signal, it is characterised in that

The primary module includes：1st reference signal generating section, the 1st reference signal generating section is by being counted, in count value When reaching a reference value set in advance, the 1st reference signal is generated, the slave module includes：

2nd reference signal generating section, the 2nd reference signal generating section reaches a reference value by being counted in count value When, generate the 2nd reference signal；

Gap count portion, the gap count portion is counted to the interval for synchronizing correcting process；

Overhead count section, the overhead count section reaches that the progress synchronization is repaiied in gap count portion count value After the correcting process spacing value just handled, the 1st reference signal is received, so as to restart, and is counted；

Count value acquisition unit, the count value acquisition unit reaches the correcting process spacing value in gap count portion count value Afterwards, opened according to the reception of the 1st reference signal to obtain the count value and the system of the 2nd reference signal generating section Sell the count value of count section；And

Synchronous correction portion, the synchronous correction portion will offset the count value and the overhead of the 2nd reference signal generating section The value of difference between the count value of count section is temporarily set in the 2nd reference signal generating section as a reference value.

2. signal synchronizing system as claimed in claim 1, it is characterised in that

The slave module includes the processor for performing the computing in the slave module,

2nd reference signal generating section is the counter that only described processor is able to access that.

3. signal synchronizing system as claimed in claim 2, it is characterised in that

The processor that the slave module is included plays a part of the count value acquisition unit, the synchronous correction portion.

4. signal synchronizing system as claimed any one in claims 1 to 3, it is characterised in that

The slave module also includes：Synchronous judging part, the synchronous judging part is as the institute accessed by the count value acquisition unit State the 2nd reference signal generating section count value it is different from the count value of the overhead count section when, be judged as the 1st base Calibration signal is asynchronous with the 2nd reference signal,

The synchronous correction portion only the synchronous judging part be judged as it is nonsynchronous in the case of, the value that will offset the difference is made On the basis of be worth and be temporarily set in the 2nd reference signal generating section.

5. signal synchronizing system as claimed in claim 4, it is characterised in that

The synchronous judging part to the count value of the 2nd reference signal generating section that is got by the count value acquisition unit with The count value of the overhead count section carries out time conversion, is judged as when both time is different asynchronous.

6. signal synchronizing system as claimed in claim 1, it is characterised in that

1st reference signal generating section periodically generates the 1st reference signal,

2nd reference signal generating section periodically generates the 2nd reference signal.

7. signal synchronizing system as claimed in claim 1, it is characterised in that

The a reference value can be set by the setting device of external connection.

8. a kind of node synchronization system, comprising the main controlled node acted according to the 1st reference signal and according to the 2nd base Calibration signal makes the 2nd reference signal synchronous with the 1st reference signal the slave node that is acted, it is characterised in that

The main controlled node includes：

1st reference signal generating section, the 1st reference signal generating section is reached set in advance by being counted in count value During a reference value, the 1st reference signal is generated；

Gap count portion, the gap count portion is counted to the interval for synchronizing correcting process；

Propagation delay time notification unit, the propagation delay time notification unit reaches progress institute in gap count portion count value After the correcting process spacing value for stating synchronous correcting process, the communication lines of the connection main controlled node and the slave node are calculated Propagation delay time in footpath, and notify to the slave node；And

Synchronized frame notification unit, the synchronized frame notification unit will be synchronous with the 1st reference signal using the communication path Synchronized frame is sent to the slave node,

The slave node includes：

2nd reference signal generating section, the 2nd reference signal generating section reaches a reference value by being counted in count value When, generate the 2nd reference signal；

Overhead count section, the overhead count section receives the synchronized frame, so as to restart, and is counted；

Count value acquisition unit, the count value acquisition unit obtains the 2nd reference signal generation according to the reception of the synchronized frame The count value of the count value in portion and the overhead count section；And

Synchronous correction portion, the synchronous correction portion will offset count value and the aggregate delay time of the 2nd reference signal generating section The value of difference between value is temporarily set in the 2nd reference signal generating section as a reference value, wherein, the synthesis is prolonged Slow time value is value sum of the count value of the overhead count section with representing the propagation delay time.

9. node synchronization system as claimed in claim 8, it is characterised in that

The propagation delay time notification unit sends propagation delay time claim frame to the slave node, and from the subordinate Node is received finishes receiving frame for the propagation delay time claim frame, prolongs at the time of according to during the reception with the transmission Difference between at the time of during the transmission of slow time claim frame calculates the propagation delay time.

10. node synchronization system as claimed in claim 8 or 9, it is characterised in that

The communication path is the star-like communication path between the main controlled node and the slave node with relay.

11. node synchronization system as claimed in claim 8, it is characterised in that

The slave node includes the processor for performing the computing in the slave node,

2nd reference signal generating section is the counter that only described processor is able to access that.

12. node synchronization system as claimed in claim 11, it is characterised in that

The processor that the slave node is included plays a part of the count value acquisition unit, the synchronous correction portion.

13. node synchronization system as claimed in claim 8, it is characterised in that

The slave node also includes：Synchronous judging part, the synchronous judging part is as accessed by the count value acquisition unit When the count value of 2nd reference signal generating section is different from the aggregate delay time, be judged as the 1st reference signal with 2nd reference signal is asynchronous,

The synchronous correction portion only the synchronous judging part be judged as it is nonsynchronous in the case of, the value that will offset the difference is made On the basis of be worth and be temporarily set in the 2nd reference signal generating section.

14. node synchronization system as claimed in claim 13, it is characterised in that

The synchronous judging part to the count value of the 2nd reference signal generating section that is got by the count value acquisition unit with The count value of the overhead count section carries out time conversion, is judged as when both time is different asynchronous.

15. node synchronization system as claimed in claim 8, it is characterised in that

1st reference signal generating section periodically generates the 1st reference signal,

2nd reference signal generating section periodically generates the 2nd reference signal.

16. node synchronization system as claimed in claim 8, it is characterised in that

The a reference value can be set by the setting device of external connection.

17. a kind of signal synchronizing method, using the primary module acted according to the 1st reference signal and according to the 2nd benchmark Signal is come the slave module that is acted, to make the 2nd reference signal synchronous with the 1st reference signal, it is characterised in that

The primary module is by being counted, when count value reaches a reference value set in advance, generates the 1st benchmark letter Number,

The slave module is by being counted, when count value reaches a reference value, generates the 2nd reference signal,

And the interval for synchronizing correcting process is counted,

Reached in count value after the correcting process spacing value for carrying out the synchronous correcting process, receive the 1st reference signal, So as to restart, and counted,

After representing that the count value at interval of the progress synchronous correcting process reaches the correcting process spacing value, obtain and use In the count value for generating the 2nd reference signal and receive the counting obtained after the 1st reference signal and restarting Value,

After the count value for being used for generating the 2nd reference signal will be offset and receive the 1st reference signal and restart To count value between the value of difference be temporarily set as a reference value based on generating the 2nd reference signal Number.

18. a kind of node synchronization method, using the main controlled node acted according to the 1st reference signal and according to the 2nd base Calibration signal is come the slave node that is acted, to make the 2nd reference signal synchronous with the 1st reference signal, it is characterised in that

The main controlled node is by being counted, when count value reaches a reference value set in advance, generates the 1st benchmark letter Number,

And the interval for synchronizing correcting process is counted,

Carrying out after the count value at interval of the synchronous correcting process reaches correcting process spacing value, calculating the connection master Node and the propagation delay time in the communication path of the slave node are controlled, and is notified to the slave node,

The synchronized frame synchronous with the 1st reference signal is sent to slave node using the communication path,

The slave node is by being counted, when count value reaches a reference value, generates the 2nd reference signal,

And the synchronized frame is received, so as to restart, and counted,

According to the reception of the synchronized frame, to obtain the count value for generating the 2nd reference signal and receive institute The count value obtained after synchronized frame and restarting is stated,

The value that counteracting is used to generate the difference between the count value and aggregate delay time value of the 2nd reference signal is used as base Quasi- value is temporarily set as the counting for generating the 2nd reference signal, wherein, the aggregate delay time value is to receive Value sum of the count value obtained after the synchronized frame and restarting with representing the propagation delay time.