CN104838615B - Signal synchronizing system, node synchronization system, signal synchronizing method and node synchronization method - Google Patents

Abstract

In the signal synchronizing system of the present invention, primary module is counted, when count value reaches a reference value set in advance, generate the 1st reference signal, slave module is counted, when count value reaches a reference value, generate the 2nd reference signal, the interval for synchronizing correcting process is counted, after count value reaches and synchronizes the correcting process spacing value of correcting process, receive the 1st reference signal and restart, counted, after the count value at the interval for representing to synchronize correcting process reaches correcting process spacing value, count value after obtaining the count value for generating the 2nd reference signal and receiving the 1st reference signal and restart, the count value for being used for generating the 2nd reference signal will be offset and receive the 1st reference signal and the value of difference between count value after restarting temporarily is set in counting for generating the 2nd reference signal as a reference value.

Description

Signal synchronizing system, node synchronization system, signal synchronizing method and node are synchronous Method

Technical field

The present invention relates to for making the synchronous signal synchronizing system of defined signal, node synchronization system, signal synchronization side Method and node synchronization method.

Background technology

In the past, performing regulated procedure under such circumstances using processor etc., for the extensive processing of reply or The purposes such as speed up processing, scatteredload, it is known to the multicomputer system of processing is performed using multiple processors.At this In the multicomputer system of sample, in order to realize the synchronization of counter (timer) among multiple processors, make primary processor pair Interrupt signal etc. is produced from the counter of processor, the synchronization of counter is realized according to the interrupt signal from processor.

In addition, in the industry networks such as existing factory's control Transmission system, constituting each equipment of system needs The data exchange of Large Copacity is mutually carried out on the basis of guarantee real-time.Therefore, it is equipped on answering for each equipment in such as basis With the generation of the access request of program, in the case of mutually accessing to event, network load depends on application program, so as to have Possibly real-time can not be ensured.

Therefore, in the past in the presence of following technology：Virtual shared memory (common storage) is set to each equipment, updated Regularly (timing) sends this node data to all nodes (station) on network.In the case of using above-mentioned technology, receive To each node accessed by updating its data, and for application program, so as to realize the data exchange side that ensure that real-time Formula.In addition, in the past, proposition has for when carrying out above-mentioned data exchange, realizing effective broadcast communication on network The method (for example, referring to patent document 1) of (BROADCAST COMMUNICATION).

In patent document 1, while using the TDMA Time Division Multiple Access mode of the built-in timer using each node, Yi Jiji In the built-in timer amendment of the slave node of the synchronized frame from main controlled node.In addition, in the method shown in patent document 1 In, it is configured to the network that transmission path is connected using bus or serial cable.

Prior art literature

Patent document

Patent document 1：Japanese Patent Laid-Open 2005-159754 publications

The content of the invention

The technical problems to be solved by the invention

However, in above-mentioned primary processor and the counter synchronisation correcting process carried out between processor etc., preferably Primary processor directly (from hardware) makes the counter resets from processor.But, because the counter is as internally entering The counter of the executions standard of capable multiple programs processing, if therefore optionally can be rewritten by outside, other processing can It can produce problem.In addition, being built in CPU (the Central Processing Unit from processor in counter：Centre Manage device) etc. in the case of, it is impossible to from primary processor directly to being resetted from the counter of processor.Therefore, in the past, once Interrupt signal is sent from primary processor to from processor, then receives the signal from processor, and using defined software come indirectly Ground (from software) performs the reset processing of counter.

In the case of above-mentioned, from processor after interrupt signal is received from primary processor, until performing and the signal phase During untill the reset processing of corresponding counter, time delay is produced due to overhead (overhead) etc..Cause , in the past, even if having carried out reset processing, primary processor and there is counter synchronisation error from being remained between processor in this.

In addition, for the synchronization of the counter between the node with master slave relation between network, it is considered to for example same by receiving Stepization frame resets the methods such as timer.However, it is same as described above, if making to determine via firmware after synchronized frame is received When device reset, then error can be produced in counter due to time delays such as the overheads.

Therefore, for the synchronous method between the node as the utilization synchronized frame of existing method, in consolidating using microcomputer , can be due to the processing of microcomputer in the case of measure amendment of the part to carry out the lock in time between main controlled node and each slave node Time and produce error.

Therefore, in order to suppress the influence to other processing brought by the rewriting of counter, it is considered to following methods：From hard Counted on part to being sent from primary processor to from the interrupt signal of processor, based on between the counter in processor Difference, to adjust the counting target (a reference value) from the counter of processor, thus realize primary processor with from processor it Between synchronization.

Counter due to primary processor is different from the respective electrical characteristic of the counter from processor, and therefore, it is difficult to estimate Primary processor and from how many deviation of counter between processor.Therefore, if be adjusted in each interrupt signal it is above-mentioned from The synchronous correcting process of a reference value of the counter of processor, then can ensure that primary processor with from synchronous between processor.So And, if continually synchronizing correcting process, it handles load increase, it is possible to which the other processing to be performed originally are produced Influence.

The present invention in view of the above and be accomplished, it is synchronous its object is to provide a kind of signal synchronizing system, node System, signal synchronizing method and node synchronization method, can suppress processing load and accurately make defined signal synchronous.

Solve the technical scheme that technical problem is used

In order to solve the above problems, signal synchronizing system of the invention includes the master acted according to the 1st reference signal Module and the slave module acted according to the 2nd reference signal, and make the 2nd reference signal and the 1st reference signal same Step, it is characterised in that primary module includes：1st reference signal generating section, the 1st reference signal generating section by being counted, When count value reaches a reference value set in advance, the 1st reference signal is generated, slave module includes：2nd reference signal generating section, should 2nd reference signal generating section is by being counted, when count value reaches a reference value, generates the 2nd reference signal；Gap count Portion, the gap count portion is counted to the interval for synchronizing correcting process；Overhead count section, the overhead is counted Portion receives the 1st benchmark letter after gap count portion count value reaches and synchronizes the correcting process spacing value of correcting process Number, so as to restart, and counted；Count value acquisition unit, the count value acquisition unit reaches in gap count portion count value To after correcting process spacing value, obtain the count value of the 2nd reference signal generating section according to the reception of the 1st reference signal and be The count value for expense count section of uniting；And synchronous correction portion, the synchronous correction portion will offset the counting of the 2nd reference signal generating section The value of difference between the count value of value and overhead count section is temporarily set in the life of the 2nd reference signal as a reference value Into portion.

In addition, the present invention is also included is applied to side by any combination of the inscape of the present invention, performance or inscape Technical scheme obtained from method, device, system, computer program, recording medium, data structure etc..

Invention effect

In accordance with the invention it is possible to which signal as defined in accurately making while processing load is suppressed is synchronous.

Brief description of the drawings

Fig. 1 is the figure of an example of the general configuration for the signal synchronizing system for representing embodiment 1.

Fig. 2 is the figure of an example of the hardware configuration for representing processor module.

Fig. 3 be for illustrate the synchronous correcting process in embodiment 1 example timing diagram (one of).

Fig. 4 is the timing diagram (two) for illustrating the example of the synchronous correcting process in embodiment 1.

Fig. 5 is the timing diagram (three) for illustrating the example of the synchronous correcting process in embodiment 1.

Fig. 6 is the figure of the example for the general sequence for representing signal synchronizing method.

Fig. 7 is the figure of an example of the general configuration for representing the node synchronization system in embodiment 2.

Fig. 8 be for illustrate the synchronous correcting process in embodiment 2 example timing diagram (one of).

Fig. 9 is the timing diagram (two) for illustrating the example of the synchronous correcting process in embodiment 2.

Figure 10 is the timing diagram (three) for illustrating the example of the synchronous correcting process in embodiment 2.

Figure 11 is the figure for illustrating the notifying process in the propagation delay time in embodiment 2 example.

Figure 12 is to represent to include the node synchronization system for having used main controlled node and slave node in embodiment 2 The figure of one example of the general configuration of network transmission system.

Figure 13 is the figure of the example for the general sequence for representing node synchronization method.

Embodiment

Below, the preferred embodiment of the present invention is described in detail referring to the drawings.Institute in involved embodiment Size, material, other concrete numerical values for showing etc. are only to should be readily appreciated that the example of the invention enumerated, except what is explicitly indicated that Outside situation, the example shown by the present invention is not limited to.In addition, in this specification and accompanying drawing, on substantive phase With function, the key element of structure, omit repeat specification by marking same label, in addition, pair with the present invention without direct relation Omitting elements diagram.

(on present embodiment)

In present embodiment, such as in multiple processor modules, at least multiple sections comprising processor module respectively In the case of entering linage-counter (timer) synchronization between the such module with master slave relation of point, device, substrate, for coming The interrupt signal (counter reset signal) of autonomous module side obtains the overhead value of slave module side.In addition, in this embodiment party In formula, correcting process is synchronized with the counter of slave module side based on the overhead value obtained.

If however, continually performing the synchronous correcting process, processing load can increase, therefore in the present embodiment, The interval for synchronizing correcting process is counted, comes regularly (intermittently) to perform by defined correcting process spacing value Synchronous correcting process.

In addition, in the present embodiment, the device with master slave relation to be set to the feelings of main controlled node and slave node Under condition, the time delay (propagation delay time) on communication path is taken into account to synchronize correcting process.

Below, be preferable to carry out side of the accompanying drawing to the signal synchronizing system in present embodiment and node synchronization system is utilized Formula is illustrated.

(embodiment 1：Signal synchronizing system)

Fig. 1 is the figure of an example of the general configuration for the signal synchronizing system for representing embodiment 1.Letter shown in Fig. 1 In number synchronization system 10, as an example, show in multiple processor modules as module (in Fig. 1 example For processor module 11a~11c) between, carry out an example of the multiprocessor of counter synchronisation.

Signal synchronizing system 10 shown in Fig. 1 has：Multiple processor module 11a~11c (are referred to as below according to needs " processor module 11 "), transfer bus 12, I/O (input and output) module 13 (being shown in figure with 13a~13d), external equipment 14 (being shown in Fig. 1 with 14a~14d) and compilation device 15.Herein, in the example of fig. 1, for convenience of description, it will locate Reason device module 11a is set to main processor modules, processor module 11b, 11c is set to from processor module, to each processor The primary structure of module is illustrated.Wherein, from quantity of processor module etc. be not limited to Fig. 1 in such two.

In addition, in present embodiment, it is not limited to said structure, single processor module is respectively provided with identical structure, with So that it can both turn into main processor modules 11a, it can turn into from processor 11b, 11c again.In addition, each processor module 11 It is connected by transfer bus 12.In addition, in embodiment 1, being set to that time delay will not be produced because of transfer bus 12.

Herein, main processor modules 11a has the 1st reference signal generating section 21, the 1st operational part 22 and storage part 23. In addition, in the example of fig. 1, the 1st reference signal generating section 21 is built in CPU described later, but is not limited thereto, the such as the 1st Reference signal generating section 21 and CPU can also be separately constructed.In addition, above-mentioned " built-in " for example represents each function in only CPU Portion's (the 1st reference signal generating section 21, the 1st operational part 22) can conduct interviews to the 1st reference signal generating section 21.

In addition, there is the 2nd reference signal generating section 31, the 2nd operational part 32, gap count from processor module 11b, 11c Portion 33, overhead count section 34, count value acquisition unit 35, synchronous judging part 36, synchronous correction portion 37 and storage part 38. In addition, in the example of fig. 1, the 2nd reference signal generating section 31 is built in CPU, but is not limited thereto, such as the 2nd benchmark letter Number generating unit 31 and CPU can also be separately constructed.

1st reference signal generating section 21 makes count value reach a reference value set in advance by being counted, so as to generate 1st reference signal.In addition, the counter that the 1st reference signal generating section 21 plays hardware is (also referred to as " fixed below according to needing When device ") function.Periodically above-mentioned count value is counted based on a reference value.In Fig. 1, it is indicated with dashed lines above-mentioned hard The counter of part.

1st operational part 22 performs (computing) storage according to the 1st reference signal generated by the 1st reference signal generating section 21 Defined application program in storage part 23 etc..In addition, the 1st reference signal is passed through as interrupt signal (counter reset signal) (transmission) is provided extremely from processor module 11b, 11c by transfer bus 12.

Storage part 23 is stored in defined application program (the Sequence Program that the 1st operational part 22 carries out computing：It is suitable Prologue).In addition, the defined application program that the 1st operational part 22 carries out computing is to being for example connected with main processor modules 11a I/O modules 13a send instruction, and the processing being controlled using I/O modules 13a to external equipment 14a.Therefore, storage part Main be stored with performs predetermined processing for couple the I/O modules 13a, the external equipment 14a that are connected with present processor module 11a in 23 Program.

That is, main processor modules 11a generates the 1st reference signal in each specified period, the 1st operational part 22 passes through (computing) application program (sequential programme) is performed according to the 1st reference signal, to be controlled to defined equipment, periodically held The row application program (sequential programme).

Then, to being illustrated from processor module 11b, 11c, but due to the structure phase from processor module 11b, 11c Together, therefore in the following description, illustrated using from processor module 11b, omit the explanation from processor module 11c.

2nd reference signal generating section 31 is counted, and set by setting and above-mentioned 1st reference signal generating section 21 A reference value identical a reference value, and by making count value reach a reference value, so as to generate the 2nd reference signal.In addition, the 2nd benchmark Signal generation portion 31 plays the function of the counter of hardware.Periodically above-mentioned count value is counted based on a reference value. In addition, the 1st reference signal generating section 21 and the respective counter of the 2nd reference signal generating section 31 are self-operating counter (free- Running counter), voluntarily promoted.

2nd operational part 32 performs (computing) storage according to the 2nd reference signal generated by the 2nd reference signal generating section 31 Defined application program in storage part 38 etc..

In addition, the 2nd reference signal generating section 31 is the counting for being only capable of conducting interviews from the 2nd operational part 32 in such as CPU Device, and (counter built in CPU) is built in CPU.That is, the 2nd reference signal generating section 31 is can not be from primary processor The counter of hardware type reset is carried out outside module 11a etc..

In addition, the 2nd operational part host processor module in 32 future 11a the 1st reference signal (synchronizing datum signal) conduct Interrupt signal is received, and starts synchronous correcting process described later.

Gap count portion 33 is counted, and is preset with the amendment suitable with the correcting process interval for synchronizing processing Spacing value is handled, in the case where count value reaches correcting process spacing value, generation represents that the correcting process of the situation starts letter Number.

In addition, correcting process spacing value is set by following calculating.For example, will be in order to meet the signal synchronizing system Required machining accuracy and the main processor modules 11a that is allowed and it is set to from the synchronous error between processor module 11b 10μs.In this case, in present embodiment, calculating the shortest time untill synchronous error is 1~5 μ s.Herein, will If synchronous error is set to 1 μ s above is due to also shorter than 1 μ s, the frequency of synchronous correcting process is uprised, processing load increase, And be set to synchronous error then to allow for the allowance relative to 10 μ s below 5 μ s.

Now, main processor modules 11a and the oscillator used from processor module 11b frequency are set to 50MHz, Vibration precision is set to 50ppm.Under the conditions of being somebody's turn to do, the shortest time that synchronous error is changed into 1 μ s is that time × synchronization of a clock is permitted Perhaps the number of oscillation that error deviates, i.e. 20ns × ((1 μ s/20ns) × (1/50ppm))=20ms.Equally, synchronous error is changed into 5 μ s shortest time is 100ms.Therefore, correction time spacing value is set to 20ms~100ms being converted into what is obtained after count value Value.By the way that correcting process spacing value is set within the above range, and synchronous correcting process is intermittently performed, so as to While processing load is suppressed, realize higher machining accuracy, improve the quality of production.

Overhead count section 34 is counted, and after correcting process commencing signal is received, i.e. in gap count portion 33 count value is reached after correcting process spacing value, is measured and is received as starting point, until performing with above-mentioned 1st reference signal Overhead value untill synchronous correcting process.Specifically, overhead count section 34, which is played, receives after the 1st reference signal The function of the counter (timer) of the hardware of restarting.

Because overhead count section 34 is the counter that is made up of hardware, therefore directly the 1st reference signal is made instead Should, and synchronous correcting process before reading being ready to complete of count value for example for needing the cost time.Based on reading this Time as overhead needed for before being ready to complete of numerical value.In addition, overhead represents that some event is played from generation Time delay untill the actual processing (software) performed for the event, and overhead is from overhead meter in this example Time of the starting point restarted for several 34 untill actually correcting process is synchronized, but be not limited thereto.

Count value acquisition unit 35 is after correcting process commencing signal is received, i.e. the count value in gap count portion 33 reaches To after correcting process spacing value, according to the reception of the 1st reference signal, (opened at the time of obtaining actual execution synchronization correcting process Begin the moment) the 2nd reference signal generating section 31 count value and the count value of overhead count section 34.

Synchronous judging part 36 the count value as the 2nd reference signal generating section 31 accessed by count value acquisition unit 35 with When the count value of overhead count section 34 is identical, it is judged as that the 1st reference signal is synchronous with the 2nd reference signal.In addition, synchronous sentence Disconnected portion 36 is in the count value as the 2nd reference signal generating section 31 accessed by count value acquisition unit 35 and overhead count section When 34 count value is different, it is judged as that above-mentioned 1st reference signal is asynchronous with the 2nd reference signal.

In addition, synchronous judging part 36 can be to as the 2nd reference signal generating section 31 accessed by count value acquisition unit 35 The count value of count value and overhead count section 34 carry out time conversion, when both time is equal, be judged as synchronization, In addition, when both time is different, being judged as asynchronous.That is, in embodiment 1, throughout managing device module 11 Between, the unit interval of each clock of each counter may be unequal.Therefore, in this case, each count value is converted Into the time, and synchronized using the time after conversion/nonsynchronous judged.

Synchronous correction portion 37, will in the case where synchronous judging part 36 judges that the 1st reference signal is synchronous with the 2nd reference signal Reference value is in the 2nd reference signal generating section 31.In addition, synchronous correction portion 37 is judged as the 1st benchmark in synchronous judging part 36 In the case of signal and the 2nd reference signal are nonsynchronous, the count value and overhead meter with the 2nd reference signal generating section 31 are obtained The value that difference between the count value of several 34 is offseted.Specifically, synchronous correction portion 37 will be by the institute of count value acquisition unit 35 The count value of the 2nd reference signal generating section 31 got subtracts the count value of overhead count section 34 to obtain synchronous amendment Value.Then, synchronous correction portion 37 subtracts calculated synchronous correction value from a reference value, and the value obtained after subtracting each other is used as new base Quasi- value is set in the 2nd reference signal generating section 31.The new a reference value refers to, when being judged as synchronous relative to synchronous judging part 36 The timer a reference value (a reference value of acquiescence) used, the timer that synchronous judging part 36 is temporarily used when being judged as asynchronous A reference value.

In addition, if synchronous judging part 36 is judged as that the 1st reference signal is asynchronous with the 2nd reference signal, and must after subtracting each other To value be set in the 2nd reference signal generating section 31 as new a reference value, and using this subtract each other after the obtained meter of value Count up into, then synchronous correction portion 37 is promptly by reference value in the 2nd reference signal generating section 31.Thus, can temporarily it make A reference value changes the amount of synchronous correction value.Herein, the example for performing the once amendment of amount corresponding with synchronous correction value has been enumerated, But it is not limited thereto, can also divides several times to perform.In this case, synchronous correction portion 37 is completed in synchronous correcting process Afterwards, by reference value in the 2nd reference signal generating section 31.

If in addition, synchronous judging part 36 is judged as synchronous between the 1st reference signal and the 2nd reference signal, synchronous amendment Portion 37 can set a reference value of above-mentioned acquiescence to the 2nd reference signal generating section 31 again and again, but it is also possible to keep same In the case of step, set after a reference value once given tacit consent to, without any further action.

In addition, in the present embodiment, due to performing synchronous correcting process, therefore the 2nd benchmark every correcting process interval The count value of signal generation portion 31 possibility different from the count value of overhead count section 34 is higher, and synchronous judging part 36 is big It is judged as that the 1st reference signal is asynchronous with the 2nd reference signal in the case of many.It therefore, it can not utilize synchronous judging part 36 to hold Row judges, i.e. no matter whether the 1st reference signal is synchronous with the 2nd reference signal, can be obtained by synchronous correction portion 37 and the The value that difference between the count value of 2 reference signal generating sections 31 and the count value of overhead count section 34 is offseted, and will The value is set in the 2nd reference signal generating section 31 as new a reference value.

Thus, by omitting the structure of synchronous judging part 36, handled without judgement, needed for can mitigating and judging Treating capacity handles load accordingly.

Storage part 38 is stored in the defined application program (sequential programme) that the 2nd operational part 32 carries out computing.In addition, the 2nd The defined application program that operational part 32 carries out computing is for example to I/O modules 13b, 13c being connected to from processor module 11b Send instruction, and the processing being controlled using I/O modules 13b, 13c to external equipment 14b, 14c.Therefore, in storage part 38 Main be stored with performs regulation for couple the I/O modules 13b, 13c, external equipment 14b, the 14c that are connected with present processor module 11b The program of processing.

I/O modules 13 carry out the input and output processing between the grade of external equipment 14.For example, I/O modules 13 will be from connecting Data of the grade acquisition of external equipment 14 connect etc. export (transmission) to processor module 11, or will be by the computing of processor module 11 The result handled out is exported to external equipment 14 etc., or it is stored.That is, processor module 11, which is utilized, applies journey Sequence carrys out the input data that computing is obtained from I/O modules 13, and is provided the operation result as output data to I/O modules 13, So as to be controlled to external equipment 14.

External equipment 14 is, for example, various sensors, motor, tape deck etc..External equipment 14 is based on coming from I/O moulds Control signal of block 13 etc., detection or driving, input and output of data to carry out data etc..

Herein, a reference value can be pre-set in processor module 11a, processor module 11b, processor module respectively 11c, can also be set by the compilation device 15 (setting device) of external connection respectively.

Compilation device 15 can be by PC (Personal Computer used in user etc.：PC) etc. increase Plus communicated with processor module 11 and set the function of a reference value to realize, but be not limited thereto or special Setting device.Thereby, it is possible to arbitrarily adjust a reference value (process cycle) for each user.

Herein, in the examples described above, multiprocessor is illustrated as an example of signal synchronizing system 10, and As long as signal system synchronization signal 10 includes the 1st reference signal generating section 21, the 2nd reference signal generating section 31, overhead meter Several 34, count value acquisition unit 35, synchronous judging part 36 and synchronous correction portion 37.

In addition, the application examples on signal synchronizing system 10, it is not limited to multiprocessor, it can also be applied to for example such as Lower timer synchronization system：Master device side is set to send to the dispatching station of the data signal of the date/time information of atomic clock, and Electronic clock will be set to from device side.

(the hardware configuration example of processor module 11)

Then, the hardware configuration example of processor module 11 is illustrated using accompanying drawing.Fig. 2 is to represent processor module 11 Hardware configuration an example figure.Processor module 11 shown in Fig. 2 have input unit 41, output section 42, CPU43, FPGA44, memory 45 and external interface 46, these parts are connected by shared bus B.

Input unit 41 inputs various operation signals, the execution of the program such as from user.In addition, input unit 41 can be with With pointing devices such as keyboard, mouse, the touch panels operated such as user, inputted by voice etc. In the case of, it is possible to have voice-input device.

Output section 42 has display, needed for being operated to the processor module 11 for carrying out the processing in present embodiment Various windows, data etc. shown, and show implementation procedure, result of control program performed by CPU43 etc..

CPU43 is based on OS (Operating System：Operating system) etc. control program, be stored in memory 45 Configuration processor, is controlled by the processing to whole processor module 11, to realize each processing in present embodiment, for example Input and output of data between various computings and each hardware constituting portion etc..In addition, CPU43 is linked with memory 45, it is real Above-mentioned 1st operational part 22, the 2nd operational part 32, count value acquisition unit 35, synchronous judging part 36, synchronous correction portion 37 are played in matter Function, and built-in 1st reference signal generating section 21, the 2nd reference signal generating section 31.In addition, institute during configuration processor Various information needed etc. can also be obtained from memory 45, and implementing result etc. is stored in memory 45.

FPGA(Field-Programmable Gate Array：Field programmable gate array) 44 it is rewritable logic electricity The integrated circuit on road.FPGA44 is made up of the various logic circuit of aiding CPU 43, in present embodiment, especially plays interval meter Several 33, the effect of overhead count section 34.Wherein, gap count portion 33 can also be handled by software.

Memory 45 is preserved by CPU43 configuration processors read out etc..In addition, memory 45 is by ROM (Read Only Memory：Read-only storage), RAM (Random Access Memory：Random access memory) etc. constitute.In addition, memory 45 can also have the memory cell such as hard disk, to be used as auxilary unit.In addition, in the storage present embodiment of memory 45 Configuration processor, the control program being arranged in computer etc., carry out input and output as needed.In addition, the correspondence of memory 45 In above-mentioned storage part 23,38 etc..

External interface 46 carries out data, the receipts of control signal between the grade of transfer bus 12 and other processor modules 11 Hair.In addition, external interface 46 also carries out data, transmitting-receiving of control signal etc. between the I/O modules 13 being connected.

By above-mentioned hardware configuration, the synchronous correcting process in present embodiment is able to carry out.In addition, being performed by installing Program, so as to realize the synchronous correcting process in present embodiment easily with general personal computer etc..

Next, the following synchronous correcting process example in embodiment 1 is illustrated.

(the synchronous correcting process example in embodiment 1)

Fig. 3~Fig. 5 is the timing diagram one of (~three) for illustrating the example of the synchronous correcting process in embodiment 1. In example shown in Fig. 3~Fig. 5, main processor modules 11a is shown and from the same of the count value between processor module 11b Walk example.In addition, a reference value (process cycle) in embodiment 1 is set to 1000 μ s, but it is not limited thereto, for example can also profit Suitably change setting with above-mentioned compilation device 15.

In Fig. 3, main processor modules 11a the 1st reference signal generating section 21 is counted.If its count value is in figure 3 (1) moment reach a reference value, then export the 1st reference signal.Then, the 1st operational part 22 is performed according to the 1st reference signal Predetermined processing.In Fig. 3, the change of the region representation count value of hatched triangle, count value increase as time goes by, if reaching To target (such as a reference value) is counted, then reset.

In addition, being counted from processor module 11b the 2nd reference signal generating section 31.If its count value is in figure 3 (2) moment reaches a reference value, then exports the 2nd reference signal.Then, the 2nd operational part 32 performs rule according to the 2nd reference signal Fixed processing.Thus, main processor modules 11a and from processor module 11b, respectively according to the 1st independent reference signal and the 2nd Reference signal performs defined processing.

In addition, from processor module 11b, gap count portion 33 is counted, between count value reaches correcting process In the case of value (Fig. 3 (3)), correcting process commencing signal is generated.Started according to the correcting process commencing signal same Walk the preparation of correcting process.

The 1st reference signal generated in main processor modules 11a is sent to from processor module as interrupt signal 11b.Receive the 1st reference signal as interruption from processor module 11b, and started using software synchronous correcting process (Fig. 3's (4)).At the same time, from processor module 11b overhead count section 34 by the count value for the counter being made up of the hardware Reset, and restart (Fig. 3 (5)).Then, in the case of being ready to complete of synchronous correcting process, at Fig. 3 (6) moment, count It is worth acquisition unit 35 and obtains count value (Fig. 3 (7)) from the 2nd reference signal generating section 31, and is obtained from overhead count section 34 Count value (Fig. 3 (8)).

The count value provided by count value acquisition unit 35 is converted into the time by synchronous judging part 36.Herein, for example according to the 2nd The counting of reference signal generating section 31 is worth to 300 μ s, and 300 μ s are worth to according to the counting of overhead count section 34.Thus, It can measure since the starting point of the interruption of the 1st reference signal, untill getting count value into synchronous correcting process is System expense, and the count value of the 2nd reference signal generating section 31 at the moment can be got.In the 1st reference signal and the 2nd benchmark In the case of signal synchronization, the count value should be equal.

Synchronous judging part 36 is by the count value (300 of the 2nd reference signal generating section 31 got by count value acquisition unit 35 μ s) it is compared with the count value (300 μ s) of overhead count section 34.In this case, because two values are equal, therefore it is synchronous Judging part 36 is judged as that the 1st reference signal is synchronous with the 2nd reference signal.

Because synchronous judging part 36 is judged as that the 1st reference signal is synchronous with the 2nd reference signal, therefore synchronous correction portion 37 is such as Generally equally by the μ s of a reference value 1000 be set in the 2nd reference signal generating section 31 (this when inscribe the 2nd reference signal generating section 31 Do not restart).Then, due to reaching the μ s of a reference value 1000, therefore the 2nd reference signal generating section 31 in Fig. 3 (9) moment count value Restart.

In addition, the 2nd reference signal generating section 31 is built in above-mentioned CPU43, and in present embodiment, it is not limited to This, can also be provided separately with CPU43.

In addition, first referring to, in the synchronous correcting process shown in Fig. 3, count value acquisition unit 35, synchronous judging part are included 36th, the processing of the program of synchronous correction portion 37.

Fig. 4 is shown from processor module 11b counter delay 3 μ s of the counter compared to main processor modules 11a Situation.

In Fig. 4, counted from processor module 11b gap count portion 33, correcting process interval is reached in count value In the case of value (Fig. 4 (1)), correcting process commencing signal is generated.Synchronization is started according to the correcting process commencing signal The preparation of correcting process.

Because count value reaches a reference value, therefore primary processor 11a the 1st reference signal generating section 21 is defeated every 1000 μ s Go out the 1st reference signal.From processor module 11b after generation correcting process commencing signal, the 1st reference signal is received in It is disconnected, and start using software synchronous correcting process (Fig. 4 (2)).At the same time, from processor module 11b overhead Count section 34 resets the count value for the counter being made up of the hardware, and restarts (Fig. 4 (3)).Then, in synchronous Corrections Division In the case of being ready to complete of reason, at Fig. 4 (4) moment, count value acquisition unit 35 is obtained from the 2nd reference signal generating section 31 and counted Numerical value (Fig. 4 (5)), and obtain count value (Fig. 4 (6)) from overhead count section 34.

The count value provided by count value acquisition unit 35 is converted into the time by synchronous judging part 36.Herein, for example according to the 2nd The counting of reference signal generating section 31 is worth to 297 μ s, and 300 μ s are worth to according to the counting of overhead count section 34.It is synchronous Two count values are compared by judging part 36, due to two count value differences, therefore are judged as the 1st reference signal and the 2nd base Calibration signal is asynchronous.

Due to synchronous judging part 36 be judged as it is asynchronous, therefore synchronous correction portion 37 by interim reference value in the 2nd Reference signal generating section 31, to cause the count value of the 2nd reference signal generating section 31 and the count value of overhead count section 34 Between difference be cancelled.Specifically, synchronous correction portion 37 utilizes " a reference value (process cycle)-(overhead count section The count value of 34 reference signal generating section 31 of count value-the 2) " this formula obtains the meter of the 2nd reference signal generating section 31 Numerical value restarts value (reset values), and calculated count value is set in into the life of the 2nd reference signal as interim a reference value Into portion 31.In the case of the example, interim a reference value is 1000 μ s- (300 μ s-297 μ s)=997 μ s.Then, due to Fig. 4 (7) moment count value reaches the interim μ s of a reference value 997, therefore the 2nd reference signal generating section 31 is restarted.That is, The value obtained after the count value of the reference signal generating section 31 of count value-the 2 of overhead count section 34 is synchronous correction value.

Thus,, can be in the output with the 1st reference signal of the next 3rd circulation for the 2nd circulation in embodiment 1 Restart the 2nd reference signal generating section 31 at the time of moment is roughly the same.Therefore, embodiment 1 can make the 1st reference signal with 2nd reference signal is synchronous.In addition, in the case of Fig. 4, a reference value is set to 1000 μ s after the 3rd circulation.

Fig. 5, which is shown from processor module 11b counter of the counter compared to main processor modules 11a, does sth. in advance 3 μ s' Situation.

In Fig. 5, counted from processor module 11b gap count portion 33, correcting process interval is reached in count value In the case of value (Fig. 5 (1)), correcting process commencing signal is generated.Synchronization is started according to the correcting process commencing signal The preparation of correcting process.

Because count value reaches a reference value, thus main processor modules 11a the 1st reference signal generating section 21 every 1000 μ s export the 1st reference signal.From processor module 11b after correcting process commencing signal is generated, the 1st reference signal is received As interruption, and start using software synchronous correcting process (Fig. 5 (2)).At the same time, it is from processor module 11b Expense of uniting count section 34 resets the count value for the counter being made up of the hardware, and restarts (Fig. 5 (3)).Then, in synchronization In the case of being ready to complete of correcting process, at Fig. 5 (4) moment, count value acquisition unit 35 is from the 2nd reference signal generating section 31 Count value (Fig. 5 (5)) is obtained, and count value (Fig. 5 (6)) is obtained from overhead count section 34.

The count value provided by count value acquisition unit 35 is converted into the time by synchronous judging part 36.Herein, for example according to the 2nd The counting of reference signal generating section 31 is worth to 303 μ s, and 300 μ s are worth to according to the counting of overhead count section 34.It is synchronous Two count values are compared by judging part 36, due to two count value differences, therefore are judged as the 1st reference signal and the 2nd base Calibration signal is asynchronous.

Because synchronous judging part 36 is judged as asynchronous, therefore synchronous 37 pair of the 2nd reference signal generating section 31 of correction portion set Fixed interim a reference value, with cause the count value of the 2nd reference signal generating section 31 and overhead count section 34 count value it Between difference be cancelled.Specifically, synchronous correction portion 37 is calculated identically with Fig. 4 explanation, obtains interim benchmark Value, and by the interim reference value in the 2nd reference signal generating section 31.In the case of the example, interim a reference value is 1000 μ s- (300 μ s-303 μ s)=1003 μ s.Then, because (7) moment count value in Fig. 4 reaches interim a reference value 1003 μ s, therefore the 2nd reference signal generating section 31 restarts.That is, the benchmark of count value-the 2 of overhead count section 34 The value obtained after the count value of signal generation portion 31 is synchronous correction value.

Thus,, can be in the output with the 1st reference signal of the next 3rd circulation for the 2nd circulation in embodiment 1 Restart the 2nd reference signal generating section 31 at the time of moment is roughly the same.Therefore, the signal synchronizing system of present embodiment can The 1st reference signal is set to be synchronised with the 2nd reference signal.In addition, after Fig. 5 the 3rd circulation, a reference value is set to 1000 μ s. As described above, in embodiment 1, no matter in the counter (timer) from processor module 11b relative to main processor modules 11a counter (timer) delay situation or ahead of time in the case of, can be appropriately carried out counter synchronisation.

(the order example of signal synchronizing method)

Fig. 6 is the figure of the example for the general sequence (sequence) for representing signal synchronizing method.In the example of fig. 6, it is Explanation is convenient, to being illustrated using main processor modules 11a and from processor module 11b synchronization, but this embodiment party Formula is not limited thereto, and can make multiple from processor module with a main processor modules to be synchronised.

In Fig. 6 counter synchronisation processing, first, main processor modules 11a the 1st reference signal generating section 21 is generated 1st reference signal (S01), the 2nd reference signal (S02) is generated from processor module 11b the 2nd reference signal generating section 31.This Outside, the processing is periodically operated in hardware.In addition, main processor modules 11a will also be obtained in S01 processing The 1st reference signal send to from processor module 11b.Therefore, the 1st base can be received by being in all the time from processor module 11b The state of calibration signal.

In addition, being counted from processor module 11b gap count portion 33 to correcting process interval, reached in count value In the case of correcting process spacing value, correcting process commencing signal is generated, starts the preparation (S03) of synchronous correcting process.

If after the count value in gap count portion 33 reaches correcting process spacing value, being received from processor module 11b The 1st reference signal (S04) transmitted by main processor modules 11a, then start synchronous correcting process (S05) using software, and Overhead count section 34 is set to restart (S06) simultaneously.Then, count value acquisition unit 35 obtain the 2nd reference signal generating section 31 with Two count values (S07) of overhead count section 34, synchronous judging part 36 is sentenced based on described two count values to synchronize Disconnected (S08), be judged as it is nonsynchronous in the case of, synchronous correction portion 37 synchronizes amendment (S09).

Thereby, it is possible to accurately make defined signal synchronous while processing load is suppressed.

(embodiment 2：Node synchronization system)

2nd embodiment is characterised by, the time delay produced by the transfer bus 12 in above-mentioned embodiment 1 is wrapped Synchronous correcting process is performed containing inside.Fig. 7 is one of the general configuration for representing the node synchronization system in embodiment 2 and shown The figure of example.Node synchronization system 50 shown in Fig. 7 is the progress counter synchronisation between multiple nodes such as node 51a~51c One example.

Node synchronization system 50 has：Multiple node 51a~51c (below according to needing to be referred to as " node 51 "), communication lines Footpath (communication network) 52, I/O (input and output) module 53 (being shown in Fig. 7 with 53a~53d), external equipment 54 (in Fig. 7 with 54a~54d is shown) and compilation device 55.That is, node synchronization system 50 is via the communication lines as communication network Footpath 52 is connected by main controlled node 51a, with slave node 51b, 51c.

Herein, for convenience of description, to using node 51a as main controlled node, using node 51b, 51c as slave node, The intrinsic structure of its each node is illustrated, but is not limited thereto, and each node can both have the structure of main controlled node Also there is the structure of slave node, make it that each node can turn into main controlled node and can turn into slave node.In addition, in reality Apply in mode 2, the propagation delay time can be produced by being set to communication path 52.

Herein, first the difference of embodiment 2 (Fig. 7) and embodiment 1 (Fig. 1) is illustrated.Main controlled node 51a phases As the main processor modules 11a in embodiment 1, slave node 51b, 51c equivalent in embodiment 1 from processor die Block 11b, 11c.In addition, compilation device 55 is equal with the essence of compilation device 15 in embodiment 1, in addition, I/O modules 53a~ 53d is substantially equal with I/O modules 13a~13d in embodiment 1.In addition, in external equipment 54a~54d and embodiment 1 External equipment 14a~14d it is substantially equal.Thus, in illustrating below, the explanation with the identical structure of embodiment 1 is omitted.

Main controlled node 51a has：(the 1st reference signal for corresponding to embodiment 1 is generated 1st reference signal generating section 61 Portion 21), the 1st operational part 62 (the 1st operational part 22 for corresponding to embodiment 1), storage part 63 (correspond to depositing for embodiment 1 Storage portion 23), the gap count portion 64 gap count portion 33 of embodiment 1 (correspond to), propagation delay time notification unit 65 and Synchronized frame notification unit 66.

The main difference between main processor modules 11a in main controlled node 51a and embodiment 1 is possess reality Apply and the gap count portion 33 from processor module 11b is arranged in mode 1 as gap count portion 64, and also newly with the addition of transmission Time delay notification unit 65, synchronized frame notification unit 66.Thus, in illustrating below, the major part to embodiment 2 is said It is bright, omit the description and acted with the identical of embodiment 1.

Hereinafter, an example to embodiment 2 is illustrated.In embodiment 2, gap count portion 64 is counted, And the correcting process spacing value suitable with the correcting process interval for synchronizing processing is preset with, reach amendment in count value In the case of handling spacing value, generation represents the correcting process commencing signal of the situation.Further, since correcting process spacing value with The essence of embodiment 1 is equal, therefore omission is described herein.

In addition, this, which is in main controlled node 51a sides, determines correcting process interval, but it is also possible in slave node 51b sides Determine correcting process interval.If in this case, reaching correcting process spacing value in slave node 51b count values, will correct Processing commencing signal is sent to main controlled node 51a, and starts synchronous correcting process.

After correcting process commencing signal is received, main controlled node 51a propagation delay time notification unit 65 is in order to count Calculate the propagation delay time and send propagation delay time claim frame to slave node 51b, 51c.The propagation delay time please Ask the form of frame and synchronized frame described later substantially identical, and with the data of the established part (such as instruction department) in synchronized frame It is different.The 1st reference signal that the propagation delay time claim frame and the 1st reference signal generating section 61 are generated synchronizedly by Send.

Then, propagation delay time notification unit 65 is received from having carried out the subordinate of response to propagation delay time claim frame Node finishes receiving frame.Then, prolong at the time of when propagation delay time notification unit 65 is received according to acknowledgement frame with sending transmission Difference between at the time of during slow time claim frame, to calculate coming and going between main controlled node 51a and slave node 51b, 51c Propagation delay time.Then, propagation delay time notification unit 65 will include the biography including the round-trip transmission time delay calculated Defeated time delay notification frame and next 1st reference signal are synchronizedly sent to slave node 51b, 51c, so as to subordinate section Point 51b, 51c were notified as the time delay produced by communication path 52.

After round-trip transmission time delay is notified of, main controlled node 51a is based on the 1st reference signal (with the 1st reference signal It is synchronised), pre-prepd synchronized frame is sent to slave node 51b, 51c via communication path 52.In addition, the processing by Synchronized frame notification unit 66 is performed.It is discussed in greater detail later, synchronized frame is for making the 2nd of slave node 51b, 51c It is same that the count value of reference signal generating section 71 and the count value of main controlled node 51a the 1st reference signal generating section 61 match Walk reference signal.

Then, slave node 51b, 51c are illustrated.Slave node 51b, 51c have：2nd reference signal generating section 71 (the 2nd reference signal generating sections 31 for corresponding to embodiment 1), the 2nd operational part 72 (correspond to the 2nd computing of embodiment 1 Portion 32), the overhead count section 74 overhead count section 34 of embodiment 1 (correspond to), (correspondence of count value acquisition unit 75 In the count value acquisition unit 35 of embodiment 1), it is synchronous judging part 76 (the synchronous judging part 36 for corresponding to embodiment 1), synchronous The correction portion 77 synchronous correction portion 37 of embodiment 1 (correspond to), storage part 78 (storage part 38 for corresponding to embodiment 1), Reception completion notice portion 79 and frame acceptance division 80.In addition, CPU43 is built-in with the 2nd reference signal generating section 71.Due to subordinate section Point 51b, 51c structure are identical, therefore in the following description, are illustrated using slave node 51b, omit slave node 51c explanation.

It is with the processor module 11b of embodiment 1 main difference, synchronous judging part 76 and embodiment 1 Synchronous judging part 36 is different, and with the addition of reception completion notice portion 79 and frame acceptance division 80.Wherein, because other compositions will Element is equal with the essence of embodiment 1, therefore omission is described herein.Hereinafter, the transmission comprising communication path 52 is prolonged The synchronous correcting process of slave node 51b including the slow time is illustrated.

Reception completion notice portion 79 receives above-mentioned propagation delay time claim frame from main controlled node 51a, and according to the transmission Time delay claim frame will finish receiving frame and send to main controlled node 51a.

Frame acceptance division 80 receives the above-mentioned propagation delay time notification frame transmitted by main controlled node 51a, and the frame is wrapped The round-trip transmission time delay (value) contained retreats to above-mentioned memory 45 etc..Thus, slave node 51b is obtained from main controlled node 51a Get the round-trip transmission time delay between main controlled node 51a and slave node 51b.

Synchronized frame is received from the main controlled node 51a slave node 51b for obtaining round-trip transmission time delay, in the 2nd computing Portion 72 produces interruption.The 2nd operational part 72 for receiving interruption starts synchronous correcting process described later.In addition, in present embodiment In, synchronized frame is received in the case of round-trip transmission time delay is not obtained, also it is of course possible to round-trip transmission is prolonged The slow time is set to zero (0) to start synchronous correcting process.If in addition, being sent out after synchronized frame will be received, to the 2nd operational part 72 Send the speed of interruption to take into account, then although not shown, but preferably use the hardware logics such as FPGA44 and be used as connecing for synchronized frame Receive unit.

In addition, overhead count section 74 is measured is received as starting point, until performing synchronous repair with above-mentioned synchronized frame Overhead value untill positive processing.Specifically, overhead count section 74 is played to receive and restarted after synchronized frame Hardware counter (timer) function.

Count value acquisition unit 75 is obtained according to the reception of synchronized frame and carved at the beginning of synchronous correcting process is actually performed The 2nd reference signal generating section 71 count value and the count value of overhead count section 74.

Synchronous judging part 76 is by above-mentioned round-trip transmission time delay divided by 2, come the transmission of the one way of obtaining communication path 52 Time delay, and further obtain the count value process of the propagation delay time of the one way and said system expense count section 74 The aggregate delay time obtained from the value obtained after time conversion is added.Then, synchronous judging part 76 prolongs calculated synthesis After the count value elapsed time conversion of the 2nd reference signal generating section 71 accessed by slow time and count value acquisition unit 75 To value be compared.When its comparative result is equal for both, synchronous judging part 76 judges the 1st reference signal and the 2nd benchmark Signal is synchronous, and when both are unequal, synchronous judging part 76 judges that the 1st reference signal is asynchronous with the 2nd reference signal.Herein, So-called synchronization means that the count value of the 1st reference signal generating section 61 is equal with the count value of the 2nd reference signal generating section 71.

In addition, synchronous judging part 76 can certainly judging part 36 synchronous with embodiment 1 it is identical, by being counted each The count value of device is converted into the time to be compared, so as to judge synchronous/asynchronous.

In embodiment 2, if every correcting process interval, the 1st reference signal and the 2nd base are judged as by synchronous judging part 76 Calibration signal is synchronous, then synchronous correction portion 77 by reference value in the 2nd reference signal generating section 71.In addition, being judged as the 1st base In the case of calibration signal and the 2nd reference signal are nonsynchronous, obtain the count value and aggregate delay of the 2nd reference signal generating section 71 The value that difference between time value is offseted.Specifically, synchronous correction portion 77 is by as accessed by count value acquisition unit 75 The count value of 2nd reference signal generating section 71 subtracts aggregate delay time value to obtain synchronous correction value.Then, synchronous correction portion 77 subtract calculated synchronous correction value from a reference value, and the value obtained after subtracting each other as new reference value in the 2nd base Calibration signal generating unit 71.The new a reference value is to be judged as being set in the 2nd reference signal during synchronization relative to synchronous judging part 76 The a reference value (a reference value of acquiescence) of generating unit 71 and (the interim a reference value) temporarily set, for amendment the 2nd benchmark letter The timing value of number generating unit 71.

In addition, present embodiment can certainly by the reference value of acquiescence in the 2nd reference signal generating section 71, and In the case of being synchronously maintained, a reference value of acquiescence is not rewritten afterwards.

Thus, in the present embodiment, synchronizing datum signal (synchronized frame) can will be notified via communication path 52 When the influence in propagation delay time synchronize correcting process with taking into account.That is, in embodiment 2, can Being modified containing the propagation delay time node and the count value of slave node 51b, 51c overhead, so as to Enough realize the synchronization between high-precision node.

(the synchronous correcting process example in embodiment 2)

Fig. 8~Figure 10 is the timing diagram for illustrating the example of the synchronous correcting process in embodiment 2, is main controlled node 51a The synchronous example of count value between slave node 51b.In addition, a reference value (process cycle) and embodiment party in embodiment 2 Formula 1 is identical, is set to 1000 μ s, and a reference value can suitably be changed using compilation device 55.

In Fig. 8, main controlled node 51a the 1st reference signal generating section 61 is counted.If the count value is at Fig. 8 (1) Reach a reference value quarter, then export the 1st reference signal.Then, as defined in the 1st operational part 62 is performed according to the 1st reference signal Processing.

In addition, slave node 51b the 2nd reference signal generating section 71 is counted.If the count value is at Fig. 8 (2) Reach a reference value quarter, then export the 2nd reference signal.Then, as defined in the 2nd operational part 72 is performed according to the 2nd reference signal Processing.Thus, in main controlled node 51a and slave node 51b, respectively according to the 1st independent reference signal and the 2nd reference signal To perform defined processing.

In addition, in main processor modules 51a, gap count portion 64 is counted, correcting process interval is reached in count value In the case of value (Fig. 8 (3)), correcting process commencing signal is generated.Master control is started according to the correcting process commencing signal Synchronous correcting process in node 51a.

After synchronous correcting process starts, main controlled node 51a propagation delay time notification unit 65 is in order to calculate biography Defeated time delay and the propagation delay time of transmission claim frame (Fig. 8 (4)).If slave node 51b reception completion notice portion 79 Propagation delay time claim frame is received from main controlled node 51a, then frame will be finished receiving according to the propagation delay time claim frame Send to main controlled node 51a (Fig. 8 (5)).

Then, main controlled node 51a propagation delay time notification unit 65 calculates main controlled node according to frame is finished receiving Round-trip transmission time delay between 51a and slave node 51b, send containing round-trip transmission time delay (400 μ calculated S) the propagation delay time notification frame (Fig. 8 (6)) including.If slave node 51b frame acceptance division 80 receives transmission delay Time announcement frame, then retreat to the grade of memory 45 (Fig. 8 (7)) by the round-trip transmission time delay (value) that the frame is included.

After synchronous correcting process starts, main controlled node 51a synchronized frame notification unit 66 is using synchronized frame in Break signal is sent to slave node 51b (Fig. 8 (8)).Then, transmission of the slave node 51b by the one way of communication path 52 Time delay (200 μ s) receives synchronized frame at the time of Fig. 8 (9), is started using the software in slave node 51b same Walk correcting process.In addition, along with the reception of synchronized frame, the counter being made up of hardware of overhead count section 74 is clear Zero and restart (Fig. 8 (10)).

Then, in the case of being ready to complete of synchronous correcting process, at Fig. 8 (11) moment, count value acquisition unit 75 Count value (Fig. 8 (12)) is obtained from the 2nd reference signal generating section 71, and count value (Fig. 8 is obtained from overhead count section 74 (13)).

Then, count value acquisition unit 75 carries out time conversion with reference to the count value of the 2nd reference signal generating section 71, so that Obtain 400 μ s.Then, synchronous judging part 76 obtains the propagation delay time 200 of one way from round-trip transmission time delay (400 μ s) μ s, the 200 μ s that will be obtained after calculated propagation delay time and the conversion of the count value elapsed time of overhead count section 74 It is added, so as to try to achieve the μ s of aggregate delay time 400.Then, synchronous judging part 76 obtains the μ s of aggregate delay time 400 with count value The 400 μ s obtained after the count value elapsed time conversion for taking the 2nd reference signal generating section 71 accessed by portion 75 are compared, Because both are equal, therefore it is judged as that the 1st reference signal is synchronous with the 2nd reference signal.

Because synchronous judging part 76 is judged as that the 1st reference signal is synchronous with the 2nd reference signal, therefore synchronous correction portion 77 is pressed Generally such, the μ s of a reference value 1000 are set in into the 2nd reference signal generating section 71, and (the 2nd reference signal generating section 71 is in setting Carve without restarting).Then, due to reaching the μ s of a reference value 1000, therefore the 2nd reference signal in Fig. 8 (14) moment count value Generating unit 71 is restarted.

Fig. 9 shows a case that counter delay 3 μ s of the slave node 51b counter than main controlled node 51a.

In Fig. 9, the count value in main controlled node 51a gap count portion 64 reaches correcting process spacing value, and starts same After walking correcting process, to the slave node 51b round-trip transmission that is included propagation delay time notification frame of frame acceptance division 80 Time delay (value) retreat to the grade of memory 45 untill processing and Fig. 8 processing it is substantially identical, therefore omit the description herein.

After synchronous correcting process starts, at Fig. 9 (1) moment, main controlled node 51a synchronized frame notification unit 66 will be same Stepization frame is sent to slave node 51b as interrupt signal.Then, biographies of the slave node 51b by the one way of communication path 52 Defeated time delay (200 μ s) receives synchronized frame at the time of Fig. 9 (2), is started using the software in slave node 51b Synchronous correcting process.In addition, along with the reception of synchronized frame, the counter of overhead count section 74 is cleared and restarted (Fig. 9 (3)).

Then, in the case of being ready to complete of synchronous correcting process, at Fig. 9 (4) moment, count value acquisition unit 75 from 2nd reference signal generating section 71 obtain count value (Fig. 9 (5)), and from overhead count section 74 obtain count value (Fig. 9's (6))。

Then, count value acquisition unit 75 carries out time conversion with reference to the count value of the 2nd reference signal generating section 71, so that Obtain 397 μ s.Then, synchronous judging part 76 obtains the propagation delay time 200 of one way from round-trip transmission time delay (400 μ s) μ s, the 200 μ s that will be obtained after calculated propagation delay time and the conversion of the count value elapsed time of overhead count section 74 It is added, so as to try to achieve the μ s of aggregate delay time 400.Then, synchronous judging part 76 obtains the μ s of aggregate delay time 400 with count value The 397 μ s obtained after the count value elapsed time conversion for taking the 2nd reference signal generating section 71 accessed by portion 75 are compared, Due to both, therefore it is judged as that the 1st reference signal is asynchronous with the 2nd reference signal.

Because synchronous judging part 76 judges that the 1st reference signal is asynchronous with the 2nd reference signal, therefore synchronous correction portion 77 will Interim reference value is in the 2nd reference signal generating section 71.Specifically, synchronous correction portion 77 utilizes " a reference value (processing week Phase)-(count value of m- 2nd reference signal generating section 71 during aggregate delay) " this formula obtain the 2nd reference signal generation Value (reset values) is restarted in portion 71, and calculated count value is set in into the life of the 2nd reference signal as interim a reference value Into portion 71.In the case of the example, interim a reference value is 1000 μ s- (400 μ s-397 μ s)=997 μ s.Then, due to Fig. 9 (7) moment count value reaches the interim μ s of a reference value 997, therefore the 2nd reference signal generating section 71 is restarted.That is, The value obtained during aggregate delay after the count value of m- 2nd reference signal generating section 71 is synchronous correction value.

Figure 10 shows a case that slave node 51b counter of the counter than main controlled node 51a shifts to an earlier date 3 μ s.

In Figure 10, the count value in main controlled node 51a gap count portion 64 reaches correcting process spacing value, and starts same After walking correcting process, to the slave node 51b round-trip transmission that is included propagation delay time notification frame of frame acceptance division 80 Time delay (value) retreat to the grade of memory 45 untill processing and Fig. 8, Fig. 9 processing it is substantially identical, therefore herein omit say It is bright.

After synchronous correcting process starts, at Figure 10 (1) moment, main controlled node 51a synchronized frame notification unit 66 will Synchronized frame is sent to slave node 51b as interrupt signal.Then, slave node 51b is by the one way of communication path 52 Propagation delay time (200 μ s) receives synchronized frame at the time of Figure 10 (2), using the software in slave node 51b come Start synchronous correcting process.In addition, along with the reception of synchronized frame, the counter of overhead count section 74, which is cleared, lays equal stress on Open (Figure 10 (3)).

Then, in the case of being ready to complete of synchronous correcting process, at Figure 10 (4) moment, count value acquisition unit 75 Count value (Figure 10 (5)) is obtained from the 2nd reference signal generating section 71, and count value (figure is obtained from overhead count section 74 10 (6)).

Then, count value acquisition unit 75 carries out time conversion with reference to the count value of the 2nd reference signal generating section 71, so that Obtain 403 μ s.Then, synchronous judging part 76 obtains the propagation delay time 200 of one way from round-trip transmission time delay (400 μ s) μ s, and by the propagation delay time of calculated one way with being obtained after the count value elapsed time conversion of overhead count section 74 200 μ s be added, so as to obtain the μ s of aggregate delay time 400.Then, synchronous judging part 76 by the μ s of aggregate delay time 400 with The 403 μ s obtained after the count value elapsed time conversion of the 2nd reference signal generating section 71 accessed by count value acquisition unit 75 It is compared, due to both, therefore is judged as that the 1st reference signal is asynchronous with the 2nd reference signal.

Because synchronous judging part 76 judges that the 1st reference signal is asynchronous with the 2nd reference signal, therefore synchronous correction portion 77 will Interim reference value is in the 2nd reference signal generating section 71.In the case of the example, interim a reference value is 1000 μ s- The μ s of (400 μ s-403 μ s)=1003.Then, because (7) moment count value in Figure 10 reaches the interim μ s of a reference value 1003, Therefore the 2nd reference signal generating section 71 is restarted.

In addition, in the case of Fig. 9 and Figure 10 example, in the 3rd circulation, the counter of master control side and the counting of subordinate side Device is synchronised, therefore afterwards, original μ s of a reference value 1000 are set in the 2nd reference signal generating section 71 by synchronous correction portion 77 (the 2nd reference signal generating section 71 is at the setting moment without restarting).Then, the 2nd reference signal generating section 71 reaches in count value Restart during to 1000 μ s of a reference value.That is, in embodiment 2, relative to the 3rd circulation, can be circulated with the next 4th The counter for making subordinate side at the time of restarting roughly the same of counter of master control side restart, therefore, it is possible to make the meter of master control side The value of number device matches into roughly equal value with the value of the counter of subordinate side.

It is identical with embodiment 1 in addition, in synchronous correcting process, comprising count value acquisition unit 75, synchronous judging part 76, The processing of the program of synchronous correction portion 77.

In addition, by slave node 51b the 2nd reference signal generating section 71 be built in CPU43 premised on be illustrated, but It is not limited thereto.That is, the 2nd reference signal generating section 71 can also be implemented separately with CPU43.But, due to the 2nd base Calibration signal generating unit 71 is built in CPU43, therefore the specified signal in CPU43 outside generation can not be utilized to make from hardware 2nd reference signal generating section 71 resets.In other words, the 2nd reference signal generating section 71 there are program to control it to act Counter.Therefore, present embodiment needs the reset processing for performing the 2nd reference signal generating section 71 using program (to restart place Reason), its overhead is relevant with synchronous error.Thus, it is necessary to the structure (embodiment party of measuring system expense in present embodiment It is also identical in formula 1).

In addition, in embodiment 2, at the interruption that synchronous correcting process is the reception by synchronized frame to be started Reason.

In addition, in the above description, slave node 51b is for example obtained from main controlled node 51a and is kept round-trip transmission to postpone Time, and effectively utilize kept round-trip transmission time delay in synchronous correcting process.In addition, also, there are as below methods：It is main Round-trip transmission time delay is contained in synchronized frame and sent to slave node 51b by control node 51a, receives the synchronization The round-trip transmission time that the slave node 51b of frame is included using synchronized frame.Thus, main controlled node 51a can be according to situation Round-trip transmission time delay suitably is notified to slave node 51b, therefore can in time be used and shape in slave node 51b Condition corresponding round-trip transmission time delay.

In addition, on propagation delay time notification unit 65, to round-trip transmission time delay is notified to slave node 51b's Situation is illustrated, but is not limited thereto.For example, propagation delay time notification unit 65 can also be by the past back pass calculated Defeated time delay divided by 2 obtain propagation delay time of one way, and by the propagation delay time of calculated one way notify to Slave node 51b.In this case, slave node 51b synchronous judging part 76 is directly using the transmission delay of the one way acquired Time, to obtain the aggregate delay time.

As is noted above, in embodiment 2, when can be by the signal transmission delay produced by communication path 52 Between the 1st reference signal is synchronised with the 2nd reference signal with being included.

(notifying process on the propagation delay time in synchronous correcting process)

Then, the notifying process to the propagation delay time in above-mentioned synchronous correcting process is illustrated.Figure 11 is to be used for Illustrate the figure of an example of the notifying process in propagation delay time in embodiment 2.In addition, in the example of fig. 11, tool Have above-mentioned main controlled node 51a and slave node 51b, 51c, and each node 51 via communication path 52 with being capable of receiving and transmitting signal State be connected.In addition, in the following description, showing that main controlled node 51a is obtained because of the communication path between each node 51 52 and produce signal propagation delay time example.

In addition, the square shown in Figure 11 represents that the square above frame, the line of each node 51 represents to send below frame, line Square represent receiving frame.In addition, the frame shown in Figure 11 has：Propagation delay time claim frame 81 (is expressed as in Figure 11 " REQ* " (* for example represents the identifier (being, for example, b, c) (same as below) of each slave node), finish receiving the (Figure 11 of frame 82 In " REC* "), propagation delay time notification frame 83 (" SET* " in Figure 11) and for propagation delay time notification frame 83 acknowledgement frame 84 (" ANS* " in Figure 11).

In Figure 11 example, main controlled node 51a prolongs the transmission for slave node 51b according to main controlled node synchronous base On slow time claim frame 81b (REQb) broadcast transmission to communication path 52.Now, included in propagation delay time claim frame 81b There is the information (Object node information) for the content for being expressed as asking for slave node 51b propagation delay time.

The propagation delay time claim frame 81b of institute's broadcast transmission is via communication path 52, in the defined propagation delay time Afterwards, received by each slave node 51b, 51c.In addition, in the example of fig. 11, slave node 51b is same according to main controlled node Walk benchmark and receive propagation delay time claim frame 81b in time delay D1, slave node 51c exists according to main controlled node synchronous base Time delay D2 receives propagation delay time claim frame 81b.

Herein, the above-mentioned Object node information that each slave node 51b, 51c are included to propagation delay time claim frame 81b Confirmed.Thus, because propagation delay time claim frame 81b is the request for slave node 51b, therefore only slave node 51b finishes receiving frame 82b (RECb) to main controlled node 51a broadcast transmissions.Now, finish receiving and include expression in frame 82b and be For the information (Object node information) of the main controlled node 51a content for finishing receiving frame.

Transmitted finishes receiving frame 82b via communication path 52, is connect by main controlled node 51a and slave node 51c Receive.Then, main controlled node 51a and slave node 51c docking harvest the above-mentioned Object node information that framing 82b included carry out it is true Recognize.As described above, it is the frame for main controlled node 51a to finish receiving frame 82b.Therefore, main controlled node 51a is based on from according to master control Node synchronous base and the propagation delay time claim frame 81b that sends transmission, untill receiving this and finishing receiving frame 82b Temporal information, to set the propagation delay time for slave node 51b.In addition, the set propagation delay time can herein Postponed with the round-trip transmission that to be defined signal come and go via communication path 52 between main controlled node 51a and slave node 51b Time or the propagation delay time of one way.

In addition, main controlled node 51a is generated for the set propagation delay time to be notified to the transmission to slave node 51b Time delay notification frame 83b (SETb), and the propagation delay time generated according to main controlled node synchronous base broadcast transmission is logical Know frame 83b.In addition, including above-mentioned Object node information in propagation delay time notification frame 83b.

The propagation delay time notification frame 83b of institute's broadcast transmission is identical with above-mentioned propagation delay time claim frame 81b, via Communication path 52, after the defined propagation delay time, is received by each slave node 51b, 51c.

Now, slave node 51b sentences according to received propagation delay time notification frame 83b Object node information Break to be the information for this node, so as to enter to be about to propagation delay time that frame in includes, with the said system overhead time etc. The synchronous correcting process for the embodiment 2 being included.In addition, main controlled node 51b generations are directed to propagation delay time notification frame 83b acknowledgement frame 84b (ANSb), and broadcast transmission is carried out to the acknowledgement frame 84b generated.Now, include in acknowledgement frame 84b Expression is the information (Object node information) of the content of the frame for main controlled node 51a and represents that synchronous correcting process has been completed The information of content etc..

Transmitted acknowledgement frame 84b is identical with the above-mentioned frame 82b that finishes receiving, via communication path 52, by main controlled node 51a And slave node 51c is received.Then, what main controlled node 51a and slave node 51c was included to acknowledgement frame 84b is above-mentioned right As nodal information is confirmed.As described above, acknowledgement frame 84b is the frame for main controlled node 51a.Therefore, main controlled node 51a energy It is enough to have completed this case by holding synchronous correcting process from slave node 51b acknowledgement frame 84b.In addition, subordinate section Point 51c although receive propagation delay time claim frame 81b (REQb), finish receiving frame 82b (RECb), the propagation delay time lead to Know frame 83b (SETb), acknowledgement frame 84b (ANSb), but due to being not the frame for this node, therefore abandon received Frame.

Content so far is the propagation delay time notifying process to slave node 51b.Therefore main controlled node 51a Similarly to slave node 51c notification transmission time delays.

Specifically, in Figure 11 example, main controlled node 51a will be directed to slave node according to main controlled node synchronous base On 51c propagation delay time claim frame 81c (REQc) broadcast transmission to communication path 52.The propagation delay time of institute's broadcast transmission Between claim frame 81c as described above via communication path 52, at defined propagation delay time (D1, D2), by each slave node 51b, 51c are received.

Because propagation delay time claim frame 81c is the request for slave node 51c, thus only slave node 51c to Main controlled node 51a broadcast transmissions finish receiving frame 82c (RECc).Transmitted finishes receiving frame 82c via communication path 52, quilt Main controlled node 51a and slave node 51c are received.It is the frame for main controlled node 51a to finish receiving frame 82c.Therefore, master control Node 51a is based on the transmission from the propagation delay time claim frame 81c sent according to main controlled node synchronous base, to receiving This finishes receiving the temporal information untill frame 82c, to set the propagation delay time for slave node 51c.In addition, this place The propagation delay time of setting can be defined signal via communication path 52 main controlled node 51a and slave node 51c it Between come and go round-trip transmission time delay or one way propagation delay time.

In addition, main controlled node 51a is generated for the set propagation delay time to be notified to the transmission to slave node 51c Time delay notification frame 83c (SETc), and the propagation delay time generated according to main controlled node synchronous base broadcast transmission is logical Know frame 83c.The propagation delay time claim frame 83c of institute's broadcast transmission is identical with above-mentioned propagation delay time claim frame 81c, via Communication path 52, at defined propagation delay time (D1, D2), is received by each slave node 51b, 51c.

Now, slave node 51b as described above, according to received propagation delay time notification frame 83c object Nodal information is judged as YES the information for this node, enters to be about to propagation delay time that frame in includes, opens with said system The synchronous correcting process for the embodiment 2 that pin time etc. is included.In addition, slave node 51c generations are directed to propagation delay time Between notification frame 83c acknowledgement frame 84c (ANSc), and broadcast transmission is carried out to the acknowledgement frame 84c that is generated.Now, acknowledgement frame 84c In include and represent to be the information (Object node information) of the content of frame for main controlled node 51a and represent synchronous Corrections Division Manage information of completed content etc..

Transmitted acknowledgement frame 84c is identical with the above-mentioned frame 82c that finishes receiving, via communication path 52, by main controlled node 51a And slave node 51c is received.Then, what main controlled node 51a and slave node 51b was included to acknowledgement frame 84c is above-mentioned right As nodal information is confirmed.As described above, acknowledgement frame 84c is the frame for main controlled node 51a.Therefore, main controlled node 51a energy It is enough to have completed this case by holding synchronous correcting process from slave node 51c acknowledgement frame 84c.In addition, subordinate section Point 51b although receive propagation delay time claim frame 81c (REQc), finish receiving frame 82c (RECc), the propagation delay time lead to Know frame 83c (SETc), acknowledgement frame 84c (ANSc), but due to being not the frame for this node, therefore abandon received Frame.

In embodiment 2, above-mentioned processing is implemented by each slave node 51b, 51c to communication path 52 successively, so that Can notification transmission time delay.

In addition, the notifying process in propagation delay time is not limited to above-mentioned steps.For example, can be in above-mentioned each node Portion sets transmitting counter, and is that acknowledgement frame 84 is sent different at the time of using transmitting counter control, to cause communication Will not be due to such as broadcast transmission propagation delay time claim frame 81, and receive the transmission on path 52, on main controlled node 51a Slave node 51b, 51c of time delay claim frame 81 send acknowledgement frame 84 and produce congestion.

It is right for example with the system of star topology as Ethernet (registration mark) in above-mentioned embodiment 2 In the common memory network using time multiplexed transmission mode, the counter synchronisation of each node can be made, in whole device Carry out the Synchronization Control matched at the time of with control.In addition, in embodiment 2, the counter synchronized can be utilized Counter inside microcomputer, or utilize based on the counter of the hardware such as FPGA to constitute.Therefore, in embodiment 2, pass through The counting synchronous with main controlled node 51a for example in the time of reception for the frame received and dispatched is constituted using the hardware such as FPGA The counter of the processing time of device and measurement microcomputer, and missed using microcomputer come its count value of computing so as to correcting process Difference.

Herein, in the examples described above, as an example of node synchronization system 50, the section master control-slave node Point is synchronous to be illustrated, but in the present embodiment, it is not limited to this, in can also apply to such as protective relay Sample-synchronous technology.

(network transmission system：General configuration example)

Herein, in above-mentioned embodiment 2, exist for example using IEEE802.3u (100BASE-TX) or The situation that the relay such as HUB (hub) as IEEE802.3ab (1000BASE-T) etc. will be connected between each node. Figure 12 is the node synchronization system 50 for representing to include the main controlled node 51a and slave node 51b, 51c that make use of in embodiment 2 The figure of one example of the general configuration of network transmission system inside.Network transmission system 90 shown in Figure 12 shows as one Example has：Above-mentioned multiple nodes 51 (being node 51a~51c in Figure 12 example), it is used as one or more relays HUB91 (being HUB91a~91e in Figure 12 example).In addition, the quantity of node, relay, species, connection method not office It is limited to this.

In Figure 12 example, Fig. 7 main controlled node, i.e. node 51a are set to node A (master station), by Fig. 7 subordinate section Point, i.e. node 51b, node 51c are set to node B, node C (slave station).In addition, as shown in figure 12, network transmission system 90 Communication path is, for example, star-like with relay between main controlled node 51a and slave node 51b.In addition, relay HUB is used as an example, but present embodiment is not limited thereto, for example, router, repeater, light can also be used to turn Parallel operation etc..

In addition, main controlled node 51a and slave node 51b, 51c are, for example, that (control device is also referred to as programmable controller PLC(Programmable Logic Controller：Programmable logic controller (PLC)), the communication path of network transmission system 90 It is the data exchange bus that the data of these programmable controllers to each other are swapped.It is connected to the data exchange bus Equipment for example in addition to above-mentioned programmable controller, also PC, server, I/O modules, drive device (be, for example, inverter, Servo control mechanism etc.) etc..

Network transmission system 90 shown in Figure 12 is connected to and node 51a and node 51c identical HUB91a, node 51b It is connected via 5 grades of HUB (relay) with node 51a and node 51c.

Herein, in the HUB of general Ethernet, using the interface mode for being referred to as storage forwarding.In this case, sending Frame be stored entirely in the order caching in HUB, it is (such as abnormal to judge or sending destination is sentenced carrying out HUB inter-process Break) it is transmitted afterwards.

(the order example of node synchronization method)

Figure 13 is the figure of an example of the general sequence for representing node synchronization method.In Figure 13 example, in order to illustrate It is convenient, to using main controlled node 51a and slave node 51b synchronously be illustrated, but not office in the present embodiment It is limited to this, multiple slave nodes can be made synchronous with a main controlled node.

In Figure 13 node synchronization process, first, main controlled node 51a the 1st reference signal generating section 61 generates the 1st base Calibration signal (S11), slave node 51b the 2nd reference signal generating section 71 generates the 2nd reference signal (S12).In addition, the processing Periodically it is operated in hardware.

In addition, main controlled node 51a gap count portion 64 is counted to correcting process interval, amendment is reached in count value In the case of handling spacing value, correcting process commencing signal is generated, starts synchronous correcting process (S13).

In the case where the count value in gap count portion 64 reaches correcting process spacing value, start in main controlled node 51a Synchronous correcting process (S13), main controlled node 51a propagation delay time notification unit 65 is sent out to calculate the propagation delay time Send propagation delay time claim frame (S14).In addition, propagation delay time claim frame is only to change the regulation that synchronized frame is included The frame obtained after partial data, in other words can also be referred to as synchronized frame, here for convenient, so that " propagation delay time asks Frame " is illustrated.

If slave node 51b reception completion notice portion 79 receives propagation delay time claim frame, generation has been received Into notice, notified (S15) to main controlled node 51a.

Main controlled node 51a propagation delay time notification unit 65 is calculated in the case where receiving reception completion notice Such as round-trip transmission time delay (S16), and generate the transmission delay for containing calculated round-trip transmission time delay etc. Time announcement frame (S17), then sends the propagation delay time notification frame generated to slave node via communication path 52 51b(S18)。

If slave node 51b frame acceptance division 80 receives propagation delay time notification frame, by the frame included it is past Returning the propagation delay time (value) retreats to the grade of memory 45 (S19).Then, main controlled node 51a synchronized frame notification unit 66 with 1st reference signal is synchronously sent synchronized frame as interrupt signal to slave node 51b (S20).Slave node 51b is connecing In the case of receiving synchronized frame (S21), start the synchronous correcting process (S22) based on software, and make overhead count section 74 restart (S23).Then, count value acquisition unit 75 obtains the 2nd reference signal generating section 71 and the two of overhead count section 74 Individual count value (S24), synchronous judging part 76 is synchronized judgement (S25) based on described two count values, is being judged as difference In the case of step, the aggregate delay time (S26) is calculated.The aggregate delay time is such as propagation delay time and overhead value The value obtained after addition, but be not limited thereto.In addition, slave node 51b synchronous correction portion 77 utilizes calculated comprehensive Time delay is closed to synchronize amendment (S27).In addition, in the processing shown in Figure 13, slave node 51b will can also be represented The acknowledgement frame that synchronous amendment has completed this case is sent to main controlled node 51a.In addition, main controlled node 51a also can be by above-mentioned Slave node beyond the slave node 51b that step pair is connected with communication path 52 carries out node synchronization process.

Herein, in present embodiment, generate for making computer play a part of each unit that above-mentioned node 51 has Program (node synchronisation procedure), by the way that the program generated is installed on into computer etc., so as to realize that above-mentioned each node is synchronous Processing.

As described above, according to present embodiment, can accurately make defined signal while processing load is suppressed It is synchronous.Thus, the stabilisation of the throughput of each node 51 can for example be realized.In addition, according to present embodiment, with For example in the system of star topology as Ethernet, for the common memory network using time multiplexed transmission mode, energy Enough make the timer synchronization of each node 51, realize the high efficiency, the high efficiency of data exchange, the stabilization of throughput of transmission Change etc..

In addition, present embodiment can be entered using multiple operations suitable for large-scale equipment etc. such as steel factory Synchronous method during a series of action of row, moreover it is possible to be widely used in same between each device in whole gigabit Ethernet Step mode.

More than, the preferred embodiment of the present invention is illustrated referring to the drawings, implemented the invention is not limited in described Mode.In category described in scope of the those skilled in the art in claim, alternatively it is conceivable to various modifications example or amendment Example, it falls within the technical scope of the present invention certainly.

In addition, the signal synchronizing method of this specification and each step of node synchronization method are not necessarily to along order Scheme described order to be handled in temporal sequence, parallel processing or the processing using subprogram can also be included.

Industrial practicality

The present invention relates to for making the synchronous signal synchronizing system of defined signal, node synchronization system, signal synchronization side Method and node synchronization method.

Label declaration

10 signal synchronizing systems

11 processor modules

12 transfer bus

13rd, 53I/O (input and output) module

14th, 54 external equipment

15th, 55 compilation device

21st, 61 the 1st reference signal generating section

22nd, 62 the 1st operational part

23rd, 38,63,78 storage part

31st, 71 the 2nd reference signal generating section

32nd, 72 the 2nd operational part

34th, 74 overhead count section

35th, 75 count value acquisition unit

36th, 76 synchronous judging part

37th, 77 synchronous correction portion

41 input units

42 output sections

43 CPU

44 FPGA

45 memories

46 external interfaces

50 node synchronization systems

51 nodes

52 communication paths

65 propagation delay time notification units

66 synchronized frame notification units

79 reception completion notice portions

80 frame acceptance divisions

81 propagation delay time claim frames

82 finish receiving frame

83 propagation delay time notification frames

84 acknowledgement frames

90 network transmission systems

91 HUB (relay)

Claims (18)

1. a kind of signal synchronizing system, believes comprising the primary module acted according to the 1st reference signal and according to the 2nd benchmark Number slave module acted, and make the 2nd reference signal synchronous with the 1st reference signal, it is characterised in that

The primary module includes：1st reference signal generating section, the 1st reference signal generating section is by being counted, in count value When reaching a reference value set in advance, the 1st reference signal is generated, the slave module includes：

2nd reference signal generating section, the 2nd reference signal generating section reaches a reference value by being counted in count value When, generate the 2nd reference signal；

Gap count portion, the gap count portion is counted to the interval for synchronizing correcting process；

Overhead count section, the overhead count section reaches that the progress synchronization is repaiied in gap count portion count value After the correcting process spacing value just handled, the 1st reference signal is received, so as to restart, and is counted；

Count value acquisition unit, the count value acquisition unit reaches the correcting process spacing value in gap count portion count value Afterwards, opened according to the reception of the 1st reference signal to obtain the count value and the system of the 2nd reference signal generating section Sell the count value of count section；And

Synchronous correction portion, the synchronous correction portion will offset the count value and the overhead of the 2nd reference signal generating section The value of difference between the count value of count section is temporarily set in the 2nd reference signal generating section as a reference value.

2. signal synchronizing system as claimed in claim 1, it is characterised in that

The slave module includes the processor for performing the computing in the slave module,

2nd reference signal generating section is the counter that only described processor is able to access that.

3. signal synchronizing system as claimed in claim 2, it is characterised in that

The processor that the slave module is included plays a part of the count value acquisition unit, the synchronous correction portion.

4. signal synchronizing system as claimed any one in claims 1 to 3, it is characterised in that

The slave module also includes：Synchronous judging part, the synchronous judging part is as the institute accessed by the count value acquisition unit State the 2nd reference signal generating section count value it is different from the count value of the overhead count section when, be judged as the 1st base Calibration signal is asynchronous with the 2nd reference signal,

The synchronous correction portion only the synchronous judging part be judged as it is nonsynchronous in the case of, the value that will offset the difference is made On the basis of be worth and be temporarily set in the 2nd reference signal generating section.

5. signal synchronizing system as claimed in claim 4, it is characterised in that

The synchronous judging part to the count value of the 2nd reference signal generating section that is got by the count value acquisition unit with The count value of the overhead count section carries out time conversion, is judged as when both time is different asynchronous.

6. signal synchronizing system as claimed in claim 1, it is characterised in that

1st reference signal generating section periodically generates the 1st reference signal,

2nd reference signal generating section periodically generates the 2nd reference signal.

7. signal synchronizing system as claimed in claim 1, it is characterised in that

The a reference value can be set by the setting device of external connection.

8. a kind of node synchronization system, comprising the main controlled node acted according to the 1st reference signal and according to the 2nd base Calibration signal makes the 2nd reference signal synchronous with the 1st reference signal the slave node that is acted, it is characterised in that

The main controlled node includes：

1st reference signal generating section, the 1st reference signal generating section is reached set in advance by being counted in count value During a reference value, the 1st reference signal is generated；

Gap count portion, the gap count portion is counted to the interval for synchronizing correcting process；

Propagation delay time notification unit, the propagation delay time notification unit reaches progress institute in gap count portion count value After the correcting process spacing value for stating synchronous correcting process, the communication lines of the connection main controlled node and the slave node are calculated Propagation delay time in footpath, and notify to the slave node；And

Synchronized frame notification unit, the synchronized frame notification unit will be synchronous with the 1st reference signal using the communication path Synchronized frame is sent to the slave node,

The slave node includes：

2nd reference signal generating section, the 2nd reference signal generating section reaches a reference value by being counted in count value When, generate the 2nd reference signal；

Overhead count section, the overhead count section receives the synchronized frame, so as to restart, and is counted；

Count value acquisition unit, the count value acquisition unit obtains the 2nd reference signal generation according to the reception of the synchronized frame The count value of the count value in portion and the overhead count section；And

Synchronous correction portion, the synchronous correction portion will offset count value and the aggregate delay time of the 2nd reference signal generating section The value of difference between value is temporarily set in the 2nd reference signal generating section as a reference value, wherein, the synthesis is prolonged Slow time value is value sum of the count value of the overhead count section with representing the propagation delay time.

9. node synchronization system as claimed in claim 8, it is characterised in that

The propagation delay time notification unit sends propagation delay time claim frame to the slave node, and from the subordinate Node is received finishes receiving frame for the propagation delay time claim frame, prolongs at the time of according to during the reception with the transmission Difference between at the time of during the transmission of slow time claim frame calculates the propagation delay time.

10. node synchronization system as claimed in claim 8 or 9, it is characterised in that

The communication path is the star-like communication path between the main controlled node and the slave node with relay.

11. node synchronization system as claimed in claim 8, it is characterised in that

The slave node includes the processor for performing the computing in the slave node,

2nd reference signal generating section is the counter that only described processor is able to access that.

12. node synchronization system as claimed in claim 11, it is characterised in that

The processor that the slave node is included plays a part of the count value acquisition unit, the synchronous correction portion.

13. node synchronization system as claimed in claim 8, it is characterised in that

The slave node also includes：Synchronous judging part, the synchronous judging part is as accessed by the count value acquisition unit When the count value of 2nd reference signal generating section is different from the aggregate delay time, be judged as the 1st reference signal with 2nd reference signal is asynchronous,

The synchronous correction portion only the synchronous judging part be judged as it is nonsynchronous in the case of, the value that will offset the difference is made On the basis of be worth and be temporarily set in the 2nd reference signal generating section.

14. node synchronization system as claimed in claim 13, it is characterised in that

The synchronous judging part to the count value of the 2nd reference signal generating section that is got by the count value acquisition unit with The count value of the overhead count section carries out time conversion, is judged as when both time is different asynchronous.

15. node synchronization system as claimed in claim 8, it is characterised in that

1st reference signal generating section periodically generates the 1st reference signal,

2nd reference signal generating section periodically generates the 2nd reference signal.

16. node synchronization system as claimed in claim 8, it is characterised in that

The a reference value can be set by the setting device of external connection.

17. a kind of signal synchronizing method, using the primary module acted according to the 1st reference signal and according to the 2nd benchmark Signal is come the slave module that is acted, to make the 2nd reference signal synchronous with the 1st reference signal, it is characterised in that

The primary module is by being counted, when count value reaches a reference value set in advance, generates the 1st benchmark letter Number,

The slave module is by being counted, when count value reaches a reference value, generates the 2nd reference signal,

And the interval for synchronizing correcting process is counted,

Reached in count value after the correcting process spacing value for carrying out the synchronous correcting process, receive the 1st reference signal, So as to restart, and counted,

After representing that the count value at interval of the progress synchronous correcting process reaches the correcting process spacing value, obtain and use In the count value for generating the 2nd reference signal and receive the counting obtained after the 1st reference signal and restarting Value,

After the count value for being used for generating the 2nd reference signal will be offset and receive the 1st reference signal and restart To count value between the value of difference be temporarily set as a reference value based on generating the 2nd reference signal Number.

18. a kind of node synchronization method, using the main controlled node acted according to the 1st reference signal and according to the 2nd base Calibration signal is come the slave node that is acted, to make the 2nd reference signal synchronous with the 1st reference signal, it is characterised in that

The main controlled node is by being counted, when count value reaches a reference value set in advance, generates the 1st benchmark letter Number,

And the interval for synchronizing correcting process is counted,

Carrying out after the count value at interval of the synchronous correcting process reaches correcting process spacing value, calculating the connection master Node and the propagation delay time in the communication path of the slave node are controlled, and is notified to the slave node,

The synchronized frame synchronous with the 1st reference signal is sent to slave node using the communication path,

The slave node is by being counted, when count value reaches a reference value, generates the 2nd reference signal,

And the synchronized frame is received, so as to restart, and counted,

According to the reception of the synchronized frame, to obtain the count value for generating the 2nd reference signal and receive institute The count value obtained after synchronized frame and restarting is stated,

The value that counteracting is used to generate the difference between the count value and aggregate delay time value of the 2nd reference signal is used as base Quasi- value is temporarily set as the counting for generating the 2nd reference signal, wherein, the aggregate delay time value is to receive Value sum of the count value obtained after the synchronized frame and restarting with representing the propagation delay time.