CN104115450B - Signal synchronization system, multiprocessor and node synchronization system - Google Patents

Abstract

A reference value is set, and by means of a count value reaching the reference value, a first reference signal and a second reference signal are generated by a first reference signal generation unit and a second reference signal generation unit. The generated first reference signal is received and a specified process is executed. The first reference signal is received and a restart is performed. An overhead until the specified process is executed is measured, with the point in time of the restart as the starting point. A count value is acquired, said count value being for the point in time at which the specified process is executed after the overhead has elapsed. When the acquired count value is different from the overhead value, an assessment is made that the first reference signal and the second reference signal are not synchronous. A synchronization correction value is determined by subtracting the count value from the overhead value. A value obtained by subtracting the determined synchronization correction value from the reference value is set as a provisional reference value in the second reference signal generation unit.

Description

Synchronization system, multiprocessor and node synchronization system

Technical field

The present invention relates to a kind of for making the synchronous signal synchronizing system of prearranged signalss, multiprocessor and the node be synchronously System.

Background technology

In prior art, in the case of using the execution preset program such as processor, in order to realize processing on a large scale, at a high speed Change process and load dispersion etc. purpose, using the multicomputer system that multiple processors are processed be known to.In many places In reason device, in order to enter the synchronization of linage-counter (intervalometer) among multiple processors, by processing to subordinate from primary processor The enumerator of device sends interrupt signal consistent with primary processor etc., realizes the synchronization of enumerator.

In addition, in the industry network of existing factory control Transmission system etc., constituting each machinery requirement of system Carry out jumbo data exchange each other on the basis of ensureing real-time.So, such as in response to institute on each machine The visiting demand of application program installed and in the case of carrying out the mutual access of event, offered load depends on application journey Sequence is it is impossible to ensure real-time.

Then, there is one kind in the prior art makes each machine have virtual shared memory (common memory), and more Send the technology of this node data to the full node (website) on network when new.In the case of using this technology, received Each node its data is updated, and pass through access application, the data exchange that achievable real-time is guaranteed Mode.In addition, in the prior art it is also proposed that a kind of when carrying out above-mentioned data exchange can achieve network on efficiently wide Broadcast the method (for example, referring to patent documentation 1) of communication (broadcast communication).

In method described in patent documentation 1, the time division multiple acess being simultaneously used the built-in timer based on each node is visited Ask the correction of the built-in timer of mode and the slave node based on the synchronized frame carrying out autonomous node.In addition, in patent documentation 1 In described method, transmission path is configured to the network being connected by bus or string line.

[prior art literature]

[patent documentation]

[patent documentation 1] JP 2005-159754 publication

Content of the invention

[inventing problem to be solved]

Need exist for illustrating, at the counter synchronisation between primary processor as above and slave processor etc. In reason, preferably primary processor directly carries out (hardware) reset to the enumerator of slave processor.However, due to this enumerator It is the enumerator of the execution benchmark as the multiple routine processes performed by inside, so, if at random entered to it from outside Row rewrites, then other process occur problem.In addition, being built in the CPU (central as slave processor in enumerator Processing unit) etc. in the case of, primary processor can not directly reset to the enumerator of slave processor.So, In the prior art, send after interrupt signal to slave processor from primary processor, slave processor receives this signal, and uses Predetermined software, carries out (software) reset processing indirectly to enumerator.

In this case, receive interrupt signal in slave processor from primary processor to start to execution and this signal phase Period till the reset processing of corresponding enumerator, the time delay based on expense etc. can be produced.For this reason, in prior art In, even if having carried out reset processing, there is also the counter synchronisation error of primary processor and slave processor.

In addition, for the synchronization of enumerator between the internetwork node with main membership relation, for example, it is also possible to examine The method considered using reception synchronization frame and intervalometer is purged etc..However, as described above, after receiving synchronization frame, such as Fruit enters the removing of linage-counter via firmware, then enumerator also can be made the time delay that its expense etc. is led to produce error.

So, even if for the synchronous method between the existing node employing synchronized frame, by microprocessor In the case that firmware is maked corrections to the mensure of host node and the lock in time of each slave node, also can produce based on microprocessor The error of the process time of device.

The present invention is in view of above-mentioned and propose, and its object is to provide one kind to make prearranged signalss accurately synchronize Signal synchronizing system, multiprocessor and node synchronization system.

[means for solving the problems]

In order to solve above-mentioned problem, the signal synchronizing system of the present invention is characterized by：1st reference signal generates Portion, wherein sets reference value, generates the 1st reference signal when count value reaches described reference value；2nd reference signal generates Portion, wherein sets described reference value, generates the 2nd reference signal when count value reaches described reference value；And calculating part, receive Described 1st reference signal that described 1st reference signal generating unit is generated simultaneously executes predetermined process.In addition, signal synchronizing system Have：Expense determination part, receives described 1st reference signal and is restarted, and measures with the described time point restarted as starting point extremely Described predetermined process be performed till expense；Count value obtaining section, after have passed through described expense, obtains described predetermined process quilt The count value of described 2nd reference signal generating unit of execution time point；And synchronization detection unit, when acquired by described count value obtaining section Count value different with the value of described expense when, be judged to that described 1st reference signal and described 2nd reference signal are asynchronous.Separately Outward, described signal synchronizing system also has synchronous correcting section, is judged to described 1st reference signal and institute in described synchronous detection unit State the 2nd reference signal asynchronous after, the count value acquired by described count value obtaining section is deducted by the value from described expense, asks Go out synchronous compensating value, and will from described reference value deduct the value after calculated synchronous compensating value as temporal reference value set to Described 2nd reference signal generating unit.

Need exist for illustrating, the present invention also comprises the element of the present invention, performance or element is any Combination application is to the rear obtained various forms such as method, device, system, computer program, recording medium, data structure.

[The effect of invention]

According to the present invention, prearranged signalss can be made accurately to synchronize.

Summary of drawings

The schematic diagram of of the signal synchronizing system schematic configuration of [Fig. 1] the 1st embodiment.

The schematic diagram of of the hardware configuration of [Fig. 2] processor.

[Fig. 3] is used for the time diagram (one) that the counter synchronisation example of the 1st embodiment is illustrated.

[Fig. 4] is used for the time diagram (its two) that the counter synchronisation example of the 1st embodiment is illustrated.

[Fig. 5] is used for the time diagram (its three) that the counter synchronisation example of the 1st embodiment is illustrated.

The schematic diagram of the outline sequence example that [Fig. 6] counter synchronisation is processed.

The schematic diagram of of the node synchronization system schematic configuration of [Fig. 7] the 2nd embodiment.

[Fig. 8] is used for the time diagram (one) that the counter synchronisation example of the 2nd embodiment is illustrated.

[Fig. 9] is used for the time diagram (its two) that the counter synchronisation example of the 2nd embodiment is illustrated.

[Figure 10] is used for the time diagram (its three) that the counter synchronisation example of the 2nd embodiment is illustrated.

[Figure 11] is used for a figure illustrating of the propagation delay time notifying process to the 2nd embodiment.

[Figure 12] comprises to employ the host node of the 2nd embodiment and the network transmission of the node synchronization system of slave node The schematic diagram of of the schematic configuration of system.

The schematic diagram of the outline sequence example of [Figure 13] node synchronization process.

Embodiments of the present invention

＜ is with regard to ＞ of the present invention

In the present invention, for example, in the case of having between the device of master slave relation and entering linage-counter (intervalometer) synchronization, With respect to the interrupt signal (counter reset signal) from master control set side, try to achieve the overhead value of slave unit side.In addition, In the present invention, according to the count value of the overhead value tried to achieve and slave unit side, synchronize asynchronous judgement, and non- In the case of synchronization, synchronize correction and process.

In addition, in the present invention, in the case that the device with master slave relation is host node and slave node, carry out same The time delay (propagation delay time) on communication path is also contemplated during the asynchronous judgement of step, and in asynchronous situation Under, synchronize correction and process.

Preferable embodiment party to the signal synchronizing system of the present invention, multiprocessor and node synchronization system referring to the drawings Formula illustrates.

＜ the 1st embodiment ＞

＜ signal synchronizing system：Schematic configuration example ＞

Fig. 1 is the schematic diagram of of the signal synchronizing system schematic configuration of the 1st embodiment.Signal shown in Fig. 1 is same Step system 10 shows as one between multiple processors (in the example of Fig. 1, processor 11-1～11-3) Carry out one of multiprocessor of counter synchronisation.

Signal synchronizing system 10 shown in Fig. 1 has：Multiple processor 11-1～11-3 (below, are also referred to as needed For " processor 11 ")；Transfer bus 12；I/O (input and output) module 13-1～13-4 (below, is also referred to as " I/ as needed O module 13 ")；External mechanical 14-1～14-4 (below, is also referred to as " external mechanical 14 ") as needed；And programmer 15. Need exist for explanation, in the example of Fig. 1, for convenience of description, using processor 11-1 as primary processor, by processor 11-2,11-3 are as slave processor, and the main composition of each processor is illustrated, but, to slave processor Quantity etc. for, be not limited to this.

Need exist for illustrating, in the present invention, be not limited to this, 1 processor can have identical structure, that is, Can be primary processor, alternatively slave processor.In addition, each processor 11 connects by transfer bus 12.Need exist for explanation , it is assumed that transfer bus 12 do not produce time delay in the 1st embodiment.

Here, primary processor 11-1 has the 1st calculating part (CPU) 21 and storage part 22.Need exist for illustrating, In the example of Fig. 1, built-in 1st reference signal generating unit 21-1 of the 1st calculating part 21, but it is not limited to this, and for example, the 1st calculating Portion 21 and the 1st reference signal generating unit 21-1 also can be made up of part respectively.In addition, above-mentioned built-in refer to, for example, quilt The 1st built-in reference signal generating unit 21-1 only can be conducted interviews by the 1st calculating part 21.

In addition, slave processor 11-2,11-3 have the 2nd calculating part (CPU) 31, synchronous correction processing unit 32 and storage Portion 33.Need exist for illustrating, in the example of Fig. 1, built-in 2nd reference signal generating unit 31-1 of the 2nd calculating part 31, but It is not limited to this, for example, the 2nd calculating part 31 and the 2nd reference signal generating unit 31-1 also can be made up of part respectively.Separately Outward, synchronous correction processing unit 32 has expense determination part 32-1, count value obtaining section 32-2, synchronous detection unit 32-3, synchronization Correcting section 32-4 and storage part 33.

1st reference signal generating unit 21-1 generates the 1st reference signal when count value reaches reference value set in advance. Need exist for illustrating, the 1st reference signal generating unit 21-1 has enumerator and (below, is also referred to as needed " regularly Device ").Above-mentioned count value is value according to obtained from reference value carries out cycle count.

The 1st reference signal that 1st calculating part 21 and the 1st reference signal generating unit 21-1 are generated is synchronous, and is stored The execution (calculating) of the predetermined application being stored in portion 22 etc..In addition, the 1st reference signal is also assigned via transfer bus 12 Give (transmission) to slave processor 11-2,11-3.

Storage part 22 preserves the predetermined application (sequence (sequence) program) that the 1st calculating part 21 is calculated.Here It should be noted that the predetermined application that the 1st calculating part 21 is calculated is e.g. to the I/O being connected with primary processor 11-1 Module 13-1 sends instruction, and process external mechanical 14-1 being controlled by I/O module 13-1.For this reason, storage part 22 In mainly save journey for I/O module 13-1 being connected with present processor or external mechanical 14-1 are carried out with predetermined process Sequence.

That is, primary processor 11-1 each cycle ground output the 1st reference signal, the 1st calculating part 21 is by carrying out application program The execution (calculating) of (sequencer program) is controlled to predetermined machine, and this application program (sequencer program) is each cycle execution.

Next, illustrating to slave processor 11-2,11-3, because slave processor 11-2,11-3 have Identical structure, so, in the following description, only slave processor 11-2 is illustrated.

Set set with above-mentioned 1st reference signal generating unit 21-1 in 2nd reference signal generating unit 31-1 Reference value identical reference value, and the 2nd reference signal is generated when count value reaches this reference value.Need exist for illustrating, 2nd reference signal generating unit 31-1 has enumerator.Above-mentioned count value carries out cycle count according to reference value and obtains Value.Additionally, the 1st reference signal generating unit 21-1 and the respective enumerator of the 2nd reference signal generating unit 31-1 are Free-running operation enumerator, carries out certainly walking.

The 2nd reference signal that 2nd calculating part 31 and the 2nd reference signal generating unit 31-1 are generated is synchronous, carries out storage part The execution (calculating) of the predetermined application being stored in 33 etc..

Need exist for illustrating, the 2nd reference signal generating unit 31-1 e.g. only can be visited by the 2nd calculating part 31 The enumerator asked, and be the enumerator (the built-in enumerator of CPU) being built in the 2nd calculating part 31.That is, the 2nd reference signal generating unit 31-1 is the enumerator that can not carry out hard reset outside primary processor 11-1 etc..

In addition, the 2nd calculating part (CPU) 31 future host processor 11-1 the 1st reference signal (synchronous reference signal) connect Receive as interrupt signal, and (predetermined process) is processed to synchronous correction described later and start.

Next, for synchronous correction processing unit 32, expense determination part 32-1 is by the reception of above-mentioned 1st reference signal As starting point, and the overhead value processing to synchronous correction being performed is measured.Specifically, expense determination part 32- 1 comprises the enumerator (intervalometer) that the 1st reference signal is received and restarted and to the value of this enumerator in synchronization What correction was processed starts the process that time point is read in.

Need exist for illustrating, expense (overhead) refers to, occur to start at for this event from certain event Manage the time delay till (software) is actually executed；In this example, it is from the beginning of the starting point that expense determination part 32-1 is restarted To the time starting time point of predetermined process, but it is not limited to this.

Count value obtaining section 32-2 acquisition predetermined process is actually carried out the 2nd reference signal generating unit 31-1 of time point Count value.That is, the beginning time point that count value obtaining section 32-2 is processed in synchronous correction reads in the 2nd reference signal generating unit 31-1 Count value.

Count value acquired by count value obtaining section 32-2 for the synchronous detection unit 32-3 and expense determination part 32-1 are counted When the count value of the overhead value of number is equal, it is judged to that the 1st reference signal and the 2nd reference signal are synchronous.In addition, synchronous detection unit 32-3, when the count value that count value obtaining section 32-2 is obtained is different with the count value of above-mentioned overhead value, is judged to above-mentioned 1 reference signal and the 2nd reference signal are asynchronous.

In addition, synchronous detection unit 32-3 also can be to the count value acquired by count value obtaining section 32-2 and expense determination part The count value of the overhead value that 32-1 is measured carries out time conversion, and is judged to synchronization when both time is equal, in addition, It is judged to asynchronous when both time is different.That is, in the 1st embodiment, throughout between reason device, there is also each meter The situation that the unit interval of every 1 clock (clock) of number device is not waited.So, in this case, when each Counter Value is carried out Between convert, and using conversion after time synchronize/asynchronous judgement.

Synchronous correcting section 32-4 after synchronous detection unit 32-3 is judged to the 1st reference signal and the 2nd reference signal synchronization, Reference value is set to the 2nd reference signal generating unit 31-1.In addition, synchronous correcting section 32-4 is sentenced in synchronous detection unit 32-3 Be set to the 1st reference signal and the 2nd reference signal asynchronous after, obtain the count value acquired by from count value obtaining section 32-2 and subtract Go the synchronous compensating value after overhead value.Next, synchronous correcting section 32-4 deducts calculated synchronous compensating value from reference value, And difference is set as the new reference value of the 2nd reference signal generating unit.This new reference value refers to, with respect to synchronous detection unit For 32-3 determined the intervalometer reference value (default reference value) being used during synchronization, synchronous detection unit 32-3 determined non- The interim intervalometer reference value being used when synchronous.

Need exist for illustrating, if synchronous detection unit 32-3 determined the 1st reference signal and the 2nd reference signal is same Step, then synchronous correcting section 32-4 the reference value of above-mentioned acquiescence can be set to the 2nd reference signal generating unit 31-1, separately every time Outward, in the case of synchronous being kept, as long as setting a default reference value.

The predetermined application (sequencer program) that storage part 33 is calculated to the 2nd calculating part 31 stores.Need exist for Illustrate, the predetermined application that the 2nd calculating part 31 is calculated is, for example, to the I/O mould being connected with slave processor 12-2 Block 13-2,13-3 give and indicating, and by I/O module 13-2,13-3, external mechanical 14-2,14-2 is controlled Reason.For this reason, storage part 33 is mainly preserved for I/O module 13-2,13-3 being connected with present processor and external mechanical 14-2,14-3 carry out the program of predetermined process.

I/O module 13 carries out processing with the input and output of external mechanical 14 grade.For example, I/O module 13 can be by from being connected The output such as the data of external mechanical 14 grade acquisition (transmission) to processor 11, can be by the calculating result output of processor 11 To external mechanical 14 etc., also it can be stored.That is, processor 11 passes through by application programs to from I/O module 13 The input data obtaining is calculated, and this result of calculation is given to I/O module 13 as output data, to external mechanical 14 It is controlled.

External mechanical 14 is, for example, various sensors, monitor and recording medium etc..External mechanical 14 is according to from I/O Control signal of module 13 etc., carries out the detection of data and the input and output of driving and data etc..

Here, reference value can be set in advance in processor 11-1 respectively, in processor 11-2, processor 11-3, also may be used Set from the programmer 15 (setting device) having carried out external connection with them respectively.Programmer 15 can by Add in PC (personal computer) that user etc. is used etc. and communicated with processor 11 and reference value can be set Function is realizing, but is not limited to this, alternatively special setting device.Accordingly, each user (can be processed to reference value Cycle) arbitrarily it is adjusted.

Here, in upper example, as one of signal synchronizing system 10, multiprocessor is illustrated, but, as Signal synchronizing system 10, as long as comprise the 1st reference signal generating unit 21-1, the 2nd reference signal generating unit 31-1, the 2nd calculating Portion 31, expense determination part 32-1, count value obtaining section 32-2, synchronous detection unit 32-3 and synchronous correcting section 32-4.

Need exist for illustrating, for the application examples of signal synchronizing system 10, be not limited to multiprocessor, example As, the transmitting station of the digital signal as the date-time information sending atomic clock alternatively using master control set side, and will Slave unit side is as the timer synchronization systematic difference example of radio wave clock.

Hardware configuration example ＞ of ＜ processor 11

Next, illustrating to the hardware configuration example of processor 11 referring to the drawings.Fig. 2 is the hardware configuration of processor The schematic diagram of one.Processor 11 shown in Fig. 2 has input unit 41, output section 42, CPU43, internal memory 44 and external interface 45, These are attached by common bus B.

Input unit 41 for example inputs to the various operation signals of the execution of the program from user etc. etc..Need exist for Illustrate, input unit 41 for example can have the instruction device of the keyboard being operated by user etc. and mouse etc., by sound In the case that sound etc. is inputted, also can have acoustic input device.

Output section 42 have to execution present embodiment process processor operated needed for various window sums According to etc. the display that shown, the implementation procedure to the control program performed by CPU43 and result etc. show.

The configuration processor that CPU43 is preserved according to the control programs such as OS (operating system) and internal memory 44, to The process of processor 11 entirety of the various data input outputs calculating and each hardware configuration between etc. is controlled, accordingly, real Each process of existing present embodiment.Need exist for illustrating, in program performing, required various information etc. can obtain from internal memory 44 Take, and implementing result etc. can be preserved.

Internal memory 44 preserves to configuration processor read-out by CPU43 etc..Need exist for illustrate, internal memory 44 by ROM (read-only memory) and RAM (random-access memory) etc. form.In addition, internal memory 44 is deposited as auxiliary Storage device can also have the memory element of hard disk etc..In addition, the control of the configuration processor to the present invention for the internal memory 44 and computer Program etc. is stored, and is inputted as needed and export.Need exist for explanation, internal memory 44 and above-mentioned storage part 22nd, 33 etc. is corresponding.

External interface 45 via the transmission carrying out data and control signal between transfer bus 12 grade and other processors and Receive.In addition, external interface 45 also carries out sending and receiving of data and control signal and the I/O module 13 being connected between Deng.

By above-mentioned hardware configuration, the counter synchronisation that can carry out the present invention is processed.In addition, by entering to configuration processor Row is installed, and the counter synchronisation being also easily achieved present embodiment on general purpose personal computer etc. is processed.

Next, being described below to the counter synchronisation example of the 1st embodiment.

Counter synchronisation example ＞ of ＜ the 1st embodiment

Fig. 3～Fig. 5 be for the counter synchronisation example of the 1st embodiment is illustrated time diagram (one～its Three).Master control side (master control set side) CPU (processor) and subordinate side (slave unit side) is shown in the example of Fig. 3～Fig. 5 The synchronous example of the Counter Value between CPU (processor).Need exist for illustrating, the reference value of the 1st embodiment (processes week Phase) it is 1000 μ s, but the present invention is not limited to this, for example can be to being set for suitable change by above-mentioned programmer 15 More.

In the example of Fig. 3～Fig. 5, the 1st reference signal that primary processor 11-1 is exported is recited as master control side synchronous base (reference signal), and the 1st reference signal generating unit 21-1 is recited as the enumerator of master control side CPU1.In addition, Fig. 3～Fig. 5 In example, also the 2nd reference signal generating unit 31-1 is recited as the enumerator 1 of subordinate side CPU2, and by expense determination part 32-1 The enumerator being had is recited as enumerator 2.

In the time point of (1) of Fig. 3, because Counter Value reaches reference value, the master control side of primary processor 11-1 The enumerator of CPU1 exports the 1st reference signal.Slave processor 11-2 receives the 1st reference signal as interruption (signal), and rises Dynamic synchronization correction processes ((2) of Fig. 3).Meanwhile, the expense determination part 32-1 of slave processor 11-2 is to this enumerator The Counter Value of (enumerator 2) is purged and makes it restart ((3) of Fig. 3).Next, expense determination part 32-1 is Fig. 3's (4) time point is the beginning time point that synchronous correction is processed, and the value with reference to this enumerator (enumerator 2) simultaneously gives this value to synchronization Detection unit 32-3.Synchronous detection unit 32-3 will be scaled the time by the Counter Value that expense determination part 32-1 is given, and obtains 200μs.Accordingly, the 1st embodiment has carried out starting to synchronous correction to process the expense being performed from the starting point interrupted Measure.

Next, the time point of (5) in Fig. 3, count value obtaining section 32-2 is with reference to the meter of the enumerator 1 of subordinate side CPU2 Number device value, and this value is given to synchronous detection unit 32-3.Synchronous detection unit 32-3 will be assigned by count value obtaining section 32-2 The Counter Value giving is scaled the time, obtains 200 μ s.Next, synchronous detection unit 32-3 is to from count value obtaining section 32-2 The Counter Value (200 μ s) being obtained and above-mentioned overhead value (200 μ s) are compared.In this case, synchronous detection unit 32-3 Because both are identical value, it is determined that being the 1st reference signal and the synchronization of the 2nd reference signal.

Because synchronous detection unit 32-3 determined synchronization, synchronous correcting section 32-4 by reference value 1000 μ s set to The enumerator 1 (in this time point, the enumerator 1 of subordinate side CPU2 is not also restarted) of subordinate side CPU2.Afterwards, subordinate side CPU2 (6) in Fig. 3 for the enumerator 1 time point because Counter Value reaches reference value 1000 μ s, restarted.

Accordingly, in the 1st embodiment, with respect to the existing cycle, can be in the output with the 1st reference signal in next cycle Machine roughly the same opportunity restarts to the enumerator 1 of subordinate side CPU2, and can make the counting of the enumerator of master control side CPU1 The Counter Value of the enumerator 1 of device value and subordinate side CPU2 becomes roughly equal value.

Need exist for illustrating, the enumerator 1 of subordinate side CPU2 is built among above-mentioned CPU, but in present embodiment In, this is simultaneously not limited, may be alternatively located at outside CPU.

In addition, additionally, during the synchronization correction shown in Fig. 3 is processed, contain count value obtaining section 32-2, The process of the program of synchronous detection unit 32-3, synchronous correcting section 32-4 and expense determination part 32-1.

Fig. 4 shows the enumerator of the slave processor 11-2 feelings of 200 μ ss slower than the enumerator of primary processor 11-1 Condition.

In the 1st cycle (cycle in left side) of Fig. 4, in the time point of (1) of Fig. 4, the master control side CPU1 of primary processor 11-1 Enumerator because Counter Value reaches reference value, output the 1st reference signal.Slave processor 11-2 receives the 1st Reference signal is as interruption (signal), and starts synchronous correction process ((2) of Fig. 4).Meanwhile, slave processor 11-2 Expense determination part 32-1 the Counter Value of this enumerator (enumerator 2) is purged and makes it restart ((3) of Fig. 4).Connect Get off, expense determination part 32-1 is in (4) time point of Fig. 4, i.e. the beginning time point processing in synchronous correction, with reference to this enumerator The value of (enumerator 2), and this value is given to synchronous detection unit 32-3.Synchronous detection unit 32-3 will be by expense determination part 32- 1 Counter Value being given is scaled the time, obtains 200 μ s.

Next, the time point of (5) in Fig. 4, count value obtaining section 32-2 is with reference to the meter of the enumerator 1 of subordinate side CPU2 Number device value, and this value is given to synchronous detection unit 32-3.Synchronous detection unit 32-3 will be assigned by count value obtaining section 32-2 The Counter Value giving is scaled the time, obtains 0 μ s.Next, synchronous detection unit 32-3 is to from count value obtaining section 32-2 institute The Counter Value (0 μ s) obtaining and above-mentioned overhead value (200 μ s) are compared.In this case, synchronous detection unit 32-3 because Both be different value, it is determined that for the 1st reference signal and the 2nd reference signal asynchronous.

Because synchronous detection unit 32-3 determined asynchronous, synchronous correcting section 32-4 is by the counting of subordinate side CPU2 Device 1 is set as temporal reference value.Specifically, synchronous correcting section 32-4 is according to " reference value (process cycle)-(" enumerator 2 "-" enumerator 1 ") " formula, that tries to achieve " enumerator 1 " restarts value (reset values), and using the Counter Value tried to achieve as Temporal reference value sets to " enumerator 1 ".In the case of this example, temporal reference value is 1000 μ s- (200 μ s-0))=800 μ s, and it is set to " enumerator 1 ".Afterwards, the time point of (6) in Fig. 4 for the enumerator 1 of subordinate side CPU2, because Counter Value Reach temporal reference value 800 μ s, so being restarted.Here incidentally, " enumerator 2 "-" enumerator 1 " It is worth for synchronous compensating value.

Accordingly, in the 1st embodiment, with respect to the existing cycle (the 1st cycle), can with (the 2nd cycle in next cycle：Figure Center cycle) roughly the same opportunity on output opportunity of the 1st reference signal the enumerator 1 of subordinate side CPU2 is carried out with weight Open.So, in the 1st embodiment, the 1st reference signal and the 2nd reference signal can be made synchronous.Need exist for illustrating, In the case of Fig. 4, because in the 2nd cycle, the 1st reference signal and the 2nd reference signal are changed into synchronous, so synchronous correcting section 32- 4 pass through to execute the process shown in above-mentioned Fig. 3, and original reference value 1000 μ s is set to the enumerator 1 (here of subordinate side CPU2 Time point, the enumerator 1 of subordinate side CPU2 is not also restarted).Afterwards, the enumerator 1 of subordinate side CPU2 reaches reference in Counter Value Restarted during value 1000 μ s.

Fig. 5 shows the enumerator of the slave processor 11-2 feelings of 200 μ ss faster than the enumerator of primary processor 11-1 Condition.

In the 1st cycle (cycle in left side) of Fig. 5, in the time point of (1) of Fig. 5, the master control side CPU1 of primary processor 11-1 Enumerator because Counter Value reaches reference value, export the 1st reference signal.Slave processor 11-2 receives the 1st ginseng Examine signal as interruption (signal), and start synchronous correction and process ((2) of Fig. 5).Meanwhile, slave processor 11-2 Expense determination part 32-1 is purged to the Counter Value of this enumerator (enumerator 2) and makes it restart ((3) of Fig. 5).Connect down Come, expense determination part 32-1 is in (4) time point of Fig. 5, i.e. the beginning time point processing in synchronous correction, with reference to this enumerator (meter Number devices 2) value, and this value is given to synchronous detection unit 32-3.Synchronous detection unit 32-3 will be by expense determination part 32-1 institute The Counter Value giving is scaled the time, obtains 200 μ s.

Next, the time point of (5) in Fig. 5, count value obtaining section 32-2 is with reference to the meter of the enumerator 1 of subordinate side CPU2 Number device value, and this value is given to synchronous detection unit 32-3.Count value obtaining section 32-2 is given by synchronous detection unit 32-3 Counter Value be scaled the time, obtain 400 μ s.Next, synchronous detection unit 32-3 is to from count value obtaining section 32-2 institute The Counter Value (400 μ s) obtaining and above-mentioned overhead value (200 μ s) are compared.In this case, synchronous detection unit 32-3 because For two Counter Values be different value, it is determined that for the 1st reference signal and the 2nd reference signal asynchronous.

Because synchronous detection unit 32-3 determined asynchronous, synchronous correcting section 32-4 is by the meter of subordinate side CPU2 Number device 1 is set as temporal reference value.Specifically, synchronous correcting section 32-4 is carried out and the same calculating illustrated by Fig. 4, asks Obtain temporal reference value, and be set to " enumerator 1 ".In the case of this example, temporal reference value is 1000 μ s- (200 μ S-400 μ s))=1200 μ s, and it is set to " enumerator 1 ".Afterwards, the enumerator 1 of subordinate side CPU2 (6) of Fig. 4 when Point, because Counter Value reaches temporal reference value 1200 μ s, is restarted.Here incidentally, " enumerator The value of 2 "-" enumerator 1 " is synchronous compensating value.

Accordingly, in the 1st embodiment, with respect to the existing cycle (the 1st cycle), can with (the 2nd cycle in next cycle：Just In cycle) roughly the same opportunity on output opportunity of the 1st reference signal the enumerator 1 of subordinate side CPU2 is restarted. So, the present invention can make the 1st reference signal and the 2nd reference signal synchronous.Need exist for illustrating, because the 2nd cycle of Fig. 5 Explanation and Fig. 4 same, so illustrating to be given up what one treasures to it.So, in the 1st embodiment, either process in subordinate The enumerator (intervalometer) of the device situation slower than the enumerator (intervalometer) of primary processor or fast in the case of, all can be real The synchronization of existing enumerator.Need exist for illustrating, above-mentioned synchronous correction processes and intermittently can execute in the resting period, also may be used To be consecutively carried out in each cycle.

Sequence (sequence) example ＞ that ＜ counter synchronisation is processed

Fig. 6 is the schematic diagram of the outline sequence example that counter synchronisation is processed.In the example of Fig. 6, for convenience of description, to making It is illustrated with the synchronization of primary processor 11-1 and slave processor 11-2, but be not limited to this in the present invention, Multiple slave processors can also be made to synchronize with respect to 1 primary processor.

In the counter synchronisation of Fig. 6 is processed, first, primary processor 11-1 generates the 1st reference signal (S01), at subordinate Reason device 11-2 generates the 2nd reference signal (S02).Need exist for illustrating, this process is the process being carried out by the hardware cycle.

Here, primary processor 11-1 is transmitted (S03) to the 1st reference signal being obtained by the process of S01.Sent out The 1st reference signal sent is sent to slave processor 11-1 (S04) via transfer bus.

Slave processor 11-2 receives after the 1st reference signal (S05), expense is measured (S06), and carries out as above Described synchronization judges (S07), in the case of asynchronous, synchronizing correction (S08).

＜ the 2nd embodiment ＞

＜ node synchronization system：Schematic configuration example ＞

2nd embodiment is characterised by, when execution comprises the delay of communication path 12 based on above-mentioned 1st embodiment Between synchronization correction process.Fig. 7 is the schematic diagram of of the node synchronization system schematic configuration of the 2nd embodiment.Shown in Fig. 7 Node synchronization system 50 be carry out counter synchronisation between multiple nodes of node 51-1～51-3 etc. one.

Node synchronization system 50 has multiple node 51-1～51-3 (below, being also referred to as " node 51 " as needed), leads to Communication network (communication path) 52, I/O (input and output) module 53, external mechanical 54 and programmer 55.That is, node synchronization system 50 are the host node 51-1 comprising the 1st calculating part (CPU) 61 and comprise the 2nd calculating part (CPU) 71 and synchronous correction processing unit 72 The system that connected via the communication network 52 as communication path of slave node 51-2,51-3.

Here, for convenience's sake, using node 51-1 as host node, using node 51-2,51-3 as subordinate section Point, and the inherent structure of each node is illustrated, but it is not limited to this in the present invention, each node also can have Can be two kinds of structures of slave node for host node again.Need exist for illustrating, it is assumed that communication lines in the 2nd embodiment Footpath 52 leads to create the propagation delay time.

Here, the 2nd embodiment (Fig. 7) and the 1st embodiment (Fig. 1) difference are illustrated.Host node 51-1 phase When in the processor 11-1 of the 1st embodiment, slave node 51-2,51-3 are equivalent to the processor 11- of the 1st embodiment 2nd, 11-3.In addition, programmer 55 is identical with the programmer 15 of the 1st embodiment, further, I/O module 53-1～53-4 Identical with the I/O module 13-1～13-4 of the 1st embodiment.External mechanical 54-1～54-4 and the 1st embodiment outer Portion machine 14-2～14-4 is identical.So, in the following description, to the portion having with the 1st embodiment identical structure The explanation dividing is given up what one treasures.

Host node 51-1 has the 1st calculating part 61 (corresponding with the 1st calculating part 21 of the 1st embodiment), storage part 62 (corresponding with the storage part 22 of the 1st embodiment), synchronized frame notification unit 63 and propagation delay time notification unit 64.Here need It is noted that built-in 1st reference signal generating unit 61-1 (the 1st reference with the 1st embodiment in the 1st calculating part 61 Signal generation portion 21-1 is corresponding).

Host node 51-1 is with the main difference of the processor 11-1 of the 1st embodiment, has added synchronized frame Notification unit 63 and propagation delay time notification unit 64.So, in the following description, the major part of the 2nd embodiment is entered Go explanation, and the explanation to action in a same manner as in the first embodiment has been given up what one treasures.

Below of the 2nd embodiment is illustrated.In the 2nd embodiment, the transmission delay of host node 51-1 Time announcement portion 64, for the calculated transmission delay time, sends propagation delay time requirement frame.This frame and synchronized frame described later Roughly the same, the data of the predetermined portions (for example, instruction part) in synchronized frame is sent after being changed again.That is, transmission delay Sent after time requirement frame and the 1st reference signal synchronization being generated by the 1st reference signal generating unit 61.

Next, propagation delay time notification unit 64 receive to the propagation delay time require frame carried out response come since Belong to node finishes receiving frame.Afterwards, moment when propagation delay time notification unit 64 receives according to acknowledgement frame and transmission delay The difference between moment when time requirement frame sends, counted to the reciprocal propagation delay time between host node and slave node Calculate.Afterwards, the propagation delay time containing the reciprocal propagation delay time having calculated is notified by propagation delay time notification unit 64 Frame is synchronized with next the 1st reference signal, and sends it to slave node, accordingly, carries out based on communication to slave node The notice of the time delay in path 52.

After having carried out the notice in reciprocal propagation delay time, host node 51-1 is according to the 1st reference signal (with the 1st with reference to letter Number synchronization), preprepared synchronized frame is sent to slave node via communication path 52.Need exist for illustrating, At this, reason synchronized frame notification unit 63 is executing.Although being described in detail below, here incidentally, synchronized frame be for Make the Counter Value of the slave node synchronous reference signal consistent with the Counter Value of host node 51-1.

Next, illustrating to slave node 51-2,51-3.Slave node 51-2,51-3 have the 2nd calculating part 71st, synchronous correction processing unit 72, storage part 73, reception completion notice portion 74 and frame acceptance division 75.Need exist for illustrating, the 2 calculating parts 71 are built in the 2nd reference signal generating unit 71-1.In addition, synchronous correction processing unit 72 has expense determination part 72-1, count value obtaining section 72-2, synchronous detection unit 72-3 and synchronous correcting section 72-4.Because slave node 51-2, 51-3 is identical structure, so, only illustrated using slave node 51-2 in the following description.

It is with the main difference of the processor 11-2 of the 1st embodiment, synchronous detection unit 72-3 and the 1st embodiment party The synchronous detection unit 32-3 of formula is different, has also added reception completion notice portion 74 and frame acceptance division 75.In other words, the 2nd with reference to letter Number generating unit 71-1 is identical with the 2nd reference signal generating unit 31-1 of the 1st embodiment, the 2nd calculating part 71 and the 1st embodiment party 2nd calculating part 31 of formula is identical.In addition, expense determination part 72-1 is identical with the expense determination part 32-1 of the 1st embodiment, meter Numerical value obtaining section 72-2 is identical with count value obtaining section 32-2 of the 1st embodiment.Further, storage part 73 and the 1st embodiment party The storage part 33 of formula is identical.So, in the following description, to the explanation having with the mutually isostructural part of the 1st embodiment Given up what one treasures.Below, the synchronization correction to the slave node 51-2 in the propagation delay time containing communication path 52 is processed Illustrate.

Reception completion notice portion 74 passes through to receive above-mentioned propagation delay time requirement frame from host node 51-1, will receive Framing sends to host node 51-1.

Frame acceptance division 75 receives the above-mentioned propagation delay time notification frame being sent by host node 51-1, and by this frame The reciprocal propagation delay time (value) being comprised is saved in above-mentioned internal memory 44 grade.So, slave node can be from host node 51-1 The reciprocal propagation delay time between obtaining between host node 51-1 and slave node.

The slave node 51-2 obtaining the reciprocal propagation delay time from host node 51-1 receives synchronized frame, and makes the 2 calculating parts (CPU) 71 produce and interrupt (signal).The 2nd calculating part 71 receiving interrupt signal starts at synchronous correction described later Reason (predetermined process).Need exist for illustrating, in the present invention, only have received there is no the reciprocal propagation delay time In the case of synchronized frame naturally it is also possible to the reciprocal propagation delay time be set to zero (0) and start synchronous correction process (predetermined Process).Furthermore, it is contemplated that starting, from receiving synchronized frame, the speed that interrupt signal enters the 2nd calculating part 71, although in figure is not entered Row represents, as the reception means of synchronized frame, it is preferable to use FPGA (field-programmable gate array) etc. Logic hardware.

In addition, in synchronous correction processing unit 72, expense determination part 72-1 is carried out from being received as of above-mentioned synchronized frame Point to synchronous correction processes the mensure of the overhead value being performed.Specifically, contain reception in expense determination part 72-1 Synchronized frame the enumerator (intervalometer) restarted and the time point that starts processing in synchronous correction read in this enumerator The process of the program of value.That is, expense determination part 72-1 receives synchronized frame and is restarted, and restarts time point as starting point with this, Process to above-mentioned synchronous correction being performed, expense is measured.

Count value obtaining section 72-2 obtains the 2nd reference signal life of the beginning time point processing in the synchronous correction of actual execution The count value of one-tenth portion 71-1.

Synchronous detection unit 72-3 passes 1/2nd of the above-mentioned reciprocal propagation delay time as the one way of communication path 52 Defeated time delay, then this one way propagation delay time is added in the hope of total delay time with above-mentioned expense.Afterwards, synchronous judgement The counting to the 2nd reference signal generating unit acquired by the total delay time tried to achieve and count value obtaining section 72-2 for the portion 72-3 Value is compared.When this result of the comparison is that both are equal, synchronous detection unit 72-3 is judged to the 1st reference signal and the 2nd reference Signal is synchronous, when both are different, judges that the 1st reference signal and the 2nd reference signal are asynchronous.Here, synchronously refer to, the 1st ginseng Examine the equal meaning of the Counter Value of the Counter Value of signal generation portion and the 2nd reference signal generating unit.

Need exist for illustrating, synchronous detection unit 72-3 can certainly be with the synchronous detection unit of the 1st embodiment The Counter Value of each enumerator is similarly scaled the time and is compared by 32-3, and then synchronizes/asynchronous sentences Fixed.

In the 2nd embodiment, determined after synchronization by synchronous detection unit 72-3, synchronous correcting section 72-4 is by reference value Set to the 2nd reference signal generating unit 71-1, and determined asynchronous after, by from acquired by count value obtaining section 72-2 The count value of the 2nd reference signal generating unit deducts above-mentioned total delay time value, obtains difference, and as synchronous compensating value. Next, synchronous correcting section 72-4 deducts the synchronous compensating value tried to achieve from reference value, and difference is set as the 2nd reference The new reference value of signal generation portion 71-1.This new reference value refers to, determined synchronization with respect to synchronous detection unit 72-3 When for the reference value (default reference value) set by the 2nd reference signal generating unit, in order to carry out the 2nd reference signal generating unit The correction of timer value and (the temporal reference value) that set temporarily.

Need exist for illustrating, in the present invention, if default reference value is set to the 2nd reference signal generating unit 71-1 simultaneously keeps synchronous, then later it is of course possible to without the rewriting carrying out default reference value；But when being judged to synchronous every time, Also default reference value can be set to the 2nd reference signal generating unit 71-1, also can intermittently be set.

So, can also to have accounted for synchronous reference signal (synchronized frame) notified via communication path 52 for the present invention When the impact in propagation delay time synchronization correction process.That is, in the 2nd embodiment, can carry out containing between node Propagation delay time and slave node the Counter Value of expense correction, thus can realize between high-precision node Synchronous.

Counter synchronisation example ＞ of ＜ the 2nd embodiment

Fig. 8～Figure 10 be for the counter synchronisation example of the 2nd embodiment is illustrated time diagram (one～its Three), be Counter Value between host node 51-1 and slave node 51-2 synchronous example.These figures are for passing to from reciprocal Defeated time delay (600 μ s, i.e. the one way propagation delay time is 300 μ s) has been calculated by host node 51-1 and has had been notified that The figure that the synchronization process of the Counter Value starting to the state after slave node 51-2 illustrates.Need exist for explanation It is that the reference value (process cycle) of the 2nd embodiment is 1000 μ s in a same manner as in the first embodiment, and this reference value can be filled by programming Put 55 and carry out suitable change.

In the example of Fig. 8～Figure 10, the synchronized frame transmission opportunity of host node 51-1 is recited as " home site synchronization base Accurate ", the 1st reference signal generating unit 61-1 is recited as " enumerator of master control side ".In addition, in the example of Fig. 8～Figure 10, will 2nd reference signal generating unit 71-1 is recited as " enumerator 1 of subordinate side ", the enumerator that expense determination part 72-1 is had It is recited as " enumerator 2 ".

In the time point of (1) of Fig. 8, host node 51-1, because the value of the enumerator of master control side reaches reference value, sends out Send synchronized frame.Afterwards, in the time point of (2), the synchronized frame that slave node 51-2 is sent to the time point of (1) have passed through logical Received after the one way propagation delay time (300 μ s) in letter path 52, and started synchronous correction and processed.In addition, with synchronous Change the reception of frame, the enumerator (enumerator 2) of expense determination part 72-1 is eliminated and is restarted ((3) of Fig. 8).

Next, the time point of (4) in Fig. 8, after synchronous correction process is actually carried out, expense determination part 72-1 reference What synchronous correction was processed starts the value of this enumerator (enumerator 2) of time point and is scaled the time, obtains 200 μ s.Accordingly, Expense determination part 72-1 carry out from synchronized frame be received as starting point to synchronous correction process be performed (beginning time point) The mensure of expense.

Next, the time point of (5) in Fig. 8, the value of enumerator 1 of count value obtaining section 72-2 reference subordinate side simultaneously will It is scaled the time, obtains 500 μ s.Then, synchronous detection unit 72-3 tries to achieve list according to the reciprocal propagation delay time (600 μ s) Journey propagation delay time 300 μ s, and the propagation delay time tried to achieve is added with above-mentioned expense 200 μ s, in the hope of total delay Time 500 μ s.Afterwards, synchronous detection unit 72-3 is to 500 acquired by total delay time 500 μ s and count value obtaining section 72-2 μ s is compared, because both are equal, it is determined that being the 1st reference signal and the synchronization of the 2nd reference signal.Because synchronous detection unit 72-3 determined synchronization, so, synchronous correcting section 72-4 sets reference value 1000 μ s to the enumerator 1 of subordinate side.(setting Timing point, the enumerator 1 of subordinate side is not also restarted).Afterwards, the time point of (6) in Fig. 8 for the enumerator 1 of subordinate side, because Counter Value has reached reference value 1000 μ s, so being restarted.

Fig. 9 shows a case that the enumerator of slave node 51-2 200 μ ss slower than the enumerator of host node 51-1.

In the 1st cycle (cycle in left side) of Fig. 9, in the time point of (1) of Fig. 9, host node 51-1 because the meter of master control side The value of number device reaches reference value, so sending synchronized frame.Afterwards, in the time point of (2), slave node 51-2 to (1) when Received after the one way propagation delay time (300 μ s) that the sent synchronized frame of point have passed through communication path 52, and started Synchronous correction is processed.In addition, with the reception of synchronized frame, the enumerator (enumerator 2) of expense determination part 72-1 is eliminated simultaneously Restarted ((3) of Fig. 9).

Next, the time point of (4) in Fig. 9, after synchronous correction processes actual execution, expense determination part 72-1 is in synchronization The beginning time point that correction is processed with reference to the value of this enumerator (enumerator 2) and is scaled the time, obtains 200 μ s.

Next, the time point of (5) in Fig. 9, the value of enumerator 1 of count value obtaining section 72-2 reference subordinate side simultaneously will It is scaled the time, obtains 300 μ s.Then, synchronous detection unit 72-3 tries to achieve list according to the reciprocal propagation delay time (600 μ s) Journey propagation delay time 300 μ s, and the propagation delay time tried to achieve is added with above-mentioned expense 200 μ s, in the hope of always prolonging Time 500 μ s late.Afterwards, synchronous detection unit 72-3 is to acquired by total delay time 500 μ s and count value obtaining section 72-2 300 μ s are compared because both are different, it is determined that for the 1st reference signal and the 2nd reference signal asynchronous.

Because synchronous detection unit 72-3 determined asynchronous, the enumerator 1 to subordinate side for synchronous correcting section 72-4 Set temporal reference value.Specifically, synchronous correcting section 72-4 according to " reference value (process cycle)-(" enumerator 2 "-" from Belong to the enumerator 1 of side ") " formula, that tries to achieve " enumerator 1 of subordinate side " restarts value (reset values), and by the counting tried to achieve Device value sets to " enumerator 1 of subordinate side " as temporal reference value.In the case of this example, temporal reference value is 1000 μ s- (500 μ s-300 μ s))=800 μ s, and it is set to " enumerator 1 of subordinate side ".Afterwards, the enumerator 1 of subordinate side is in Figure 10 (6) time point because Counter Value reaches temporal reference value 800 μ s, restarted.Here incidentally It is, enumerator 2 "-the value of " enumerator 1 of subordinate side " is synchronous compensating value.

Figure 10 shows a case that the enumerator of slave node 51-2 200 μ ss faster than the enumerator of host node 51-1. In the 1st cycle (cycle in left side) of Figure 10, in the time point of (1) of Figure 10, host node 51-1 is because of the enumerator of master control side Value reaches reference value, so the transmission of synchronizing frame.Afterwards, in the time point of (2), slave node 51-2 to (1) when Received after the one way propagation delay time (300 μ s) that the sent synchronized frame of point have passed through communication path 52, and started Synchronous correction is processed.In addition, with the reception of synchronized frame, the enumerator (enumerator 2) of expense determination part 72-1 is eliminated simultaneously Restarted ((3) of Figure 10).

Next, the time point of (4) in Figure 10, after synchronous correction processes actual execution, expense determination part 72-1 is in synchronization The beginning time point that correction is processed with reference to the value of this enumerator (enumerator 2) and is scaled the time, obtains 200 μ s.

Next, the time point of (5) in Figure 10, the value of enumerator 1 of count value obtaining section 72-2 reference subordinate side simultaneously will It is scaled the time, obtains 700 μ s.Then, synchronous detection unit 72-3 tries to achieve list according to the reciprocal propagation delay time (600 μ s) Journey propagation delay time 300 μ s, and the one way the tried to achieve propagation delay time is added with above-mentioned expense 200 μ s, in the hope of total Time delay 500 μ s.Afterwards, synchronous detection unit 72-3 is to acquired by total delay time 500 μ s and count value obtaining section 72-2 700 μ s be compared because both are different, it is determined that for the 1st reference signal and the 2nd reference signal asynchronous.

Because synchronous detection unit 72-3 determined asynchronous, the enumerator 1 to subordinate side for synchronous correcting section 72-4 Set temporal reference value.In the case of this example, temporal reference value is 1000 μ s- (500 μ s-700 μ s))=1200 μ s, and It is set to " enumerator 1 of subordinate side ".Afterwards, the time point of (6) in Figure 10 for the enumerator 1 of subordinate side, because Counter Value Reach temporal reference value 1200 μ s, so being restarted.

Need exist for illustrating, in the case of the example of Fig. 9 and Figure 10, in the 2nd cycle (cycle of the center of figure), because The enumerator 1 of the enumerator for master control side and subordinate side is changed into synchronous, and synchronous correcting section 72-4 is passed through to execute shown in above-mentioned Fig. 8 Process, original reference value 1000 μ s is set and (is setting time point, the enumerator 1 of subordinate side is simultaneously to the enumerator 1 of subordinate side Do not restarted).Afterwards, the enumerator 1 of subordinate side is restarted when Counter Value reaches reference value 1000 μ s.That is, the 2nd In embodiment, roughly the same opportunity can be restarted in the enumerator of the master control side with next cycle with respect to the existing cycle, The enumerator 1 of subordinate side is restarted, so, the value that can make the value of the enumerator of master control side and the enumerator 1 of subordinate side is Roughly equal value.

Need exist for illustrating, synchronous correction processes and contains count value obtaining section in a same manner as in the first embodiment 72-2, the process of the program of synchronous detection unit 72-3, synchronous correcting section 72-4 and expense determination part 72-1.

Although in addition, being to carry out premised on the 2nd reference signal generating unit 71-1 is built in CPU by the enumerator 1 of subordinate side Explanation, but it is not limited to this.That is, the 2nd reference signal generating unit 71-1 also can be implemented within outside CPU.However, When the 2nd reference signal generating unit 71-1 is built in CPU, can not be to the 2nd by the prearranged signalss that the outside of CPU is generated Reference signal generating unit 71-1 carries out hard reset.In other words, the 2nd reference signal generating unit 71-1 is to its action via program The enumerator being controlled.For this reason, in the present invention, need to carry out the reset of the 2nd reference signal generating unit 71-1 by program Process (reboot process), its expense is related to synchronous error.So, in the present invention, need to have expense is measured Structure () in the 1st embodiment similarly.

In addition, in the 2nd embodiment, it is the interrupt processing being started by the reception of synchronized frame that synchronous correction is processed.

In addition, in the above description, slave node 51-2 for example obtains the reciprocal propagation delay time from host node 51-1 And it is kept (preservation), and the reciprocal propagation delay time being kept is entered to exercise when the synchronous correction of execution is processed With.In addition, also have：Host node 51-1 is included in synchronized frame and sends it in the reciprocal propagation delay time Slave node 51-2, and have received the slave node 51-2 of this synchronized frame to during reciprocal transmission included in synchronized frame Between the method that used.Accordingly, because the reciprocal propagation delay time can suitably be led to by host node 51-1 as the case may be Know to slave node, so in slave node, the reciprocal propagation delay time based on concrete condition can be used in time.

Although in addition, to propagation delay time notification unit 64 to notify the reciprocal propagation delay time to slave node 51- 2 mode is illustrated, but is not limited to this.For example, propagation delay time notification unit 64 also can be by the reciprocal biography calculating / 2nd of defeated time delay ask as the one way propagation delay time, and the one way the tried to achieve propagation delay time notified to from Belong to node 51-2.In the case, as long as the synchronous detection unit 72-3 of slave node 51-2 is designed as former state using institute The one way propagation delay time giving tries to achieve total delay time.

In the 2nd embodiment as above, signal transmission delay time based on communication path can be comprised 1st reference signal and the synchronization of the 2nd reference signal.

Propagation delay time notifying process ＞ that ＜ is processed with regard to synchronous correction

Next, the propagation delay time notifying process that above-mentioned synchronization correction is processed illustrates.Figure 11 be for One of the propagation delay time notifying process of the 2nd embodiment is illustrated figure.Need exist for illustrating, Figure 11 Example in there is above-mentioned host node 51-1 and slave node 51-2,51-3, each node be configured to via communication path 52 are connected in the state of can carrying out the sending and receiving of signal.In addition, in the following description, show host node 51- 1 example obtaining the signal transmission delay time based on communication path 52 between each node.

In addition, the tetragon shown in Figure 11 represents frame, represent transmission frame, line with respect to the tetragon above the line of each node Following tetragon represents reception frame.In addition, the frame shown in Figure 11 has：Propagation delay time requires the frame 81 (" REQ of Figure 11 S* " (* represent for example be used for identifying each slave node and allocated numbering (same below))；Finish receiving frame 82 (Figure 11 " S*」)；Propagation delay time notification frame 83 (" the SET S* " of Figure 11)；And the response with respect to propagation delay time notification frame 83 Frame 84 (" the ANS S* " of Figure 11).

In the example of Figure 11, host node 51-1 requires frame to the propagation delay time with respect to slave node 51-2 (S1) 81-1 (REQ S1), according to the synchronous base of host node, carries out broadcast transmission on communication path 52.Now, propagation delay time Between require to contain to represent it is information (the object section that the propagation delay time with respect to slave node 51-2 requires in frame 81-1 Point information).

The propagation delay time being broadcasted transmission requires frame 81-1 via communication path 52 after scheduled transmission time delay Received by each slave node 51-2,51-3.Need exist for illustrating, in the example of Figure 11, slave node 51-1 is based on The synchronous base of host node requires frame 81-1 to receive the propagation delay time in time delay at D1, slave node 51-3 Synchronous base based on host node requires frame 81-1 to receive the propagation delay time in time delay at D2.

Here, each slave node 51-2,51-3 require the above-mentioned object included in frame 81-1 to the propagation delay time Nodal information is confirmed.As described above, because it is with respect to slave node 51-2 that the propagation delay time requires frame 81-1 Require, so, the broadcast that only slave node 51-2 carries out finishing receiving frame 82-1 (S1) with respect to host node 51-1 is sent out Send.Now, finish receiving and in frame 82-1, contain the information (object finishing receiving frame that expression is with respect to host node 51-1 Nodal information).

The frame 82-1 that finishes receiving being sent is connect by host node 51-1 and slave node 52-3 via communication path 52 Receive.Next, host node 51-1 and slave node 51-3 docking harvests the above-mentioned Object node letter included in framing 82-1 Breath is confirmed.As described above, finishing receiving the frame that frame 82-1 is with respect to host node 51-1.For this reason, host node 51-1 root Start to it to completing frame according to the transmission that propagation delay time of being sent from the synchronous base according to host node requires frame 81-1 82-1 received till temporal information, carry out the setting in the propagation delay time with respect to slave node 51-2.Here It should be noted that here, set propagation delay time can for prearranged signalss via communication path 52 in host node 51-1 Carry out reciprocal reciprocal propagation delay time, alternatively one way propagation delay time and slave node 51-2 between.

In addition, host node 51-1 generates for notifying the set propagation delay time to the biography of slave node 51-2 Defeated notification frame 83-1 time delay (SET S1), and by the propagation delay time being generated notification frame 83-1 according to host node Synchronous base carries out broadcast transmission.Need exist for illustrating, it is above-mentioned right to contain in propagation delay time notification frame 83-1 As nodal information.

It is broadcasted propagation delay time notification frame 83-1 of transmission and the above-mentioned propagation delay time requires frame 81-1 same Ground have passed through via communication path 52 and received by each slave node 51-2,51-3 after scheduled transmission time delay.

Now, slave node 51-2 sentences according to the Object node information of propagation delay time notification frame 83-1 being received Break as being the information with respect to this node, and carry out containing propagation delay time and the above-mentioned overhead time contained by frame in etc. The synchronization correction of the 2nd embodiment is processed.In addition, slave node 51-2 generates with respect to propagation delay time notification frame 83-1 Acknowledgement frame 84-1 (ANS S1), and broadcast transmission is carried out to the acknowledgement frame 84-1 being generated.Now, in acknowledgement frame 84-1 Contain and represent and be the information (Object node information) of frame with respect to host node 51-1 and represent that synchronous correction is processed and complete Information etc..

The acknowledgement frame 84-1 being sent with above-mentioned finish receiving frame 82-1 in the same manner as via communication path 52 by host node 51-1 and slave node 52-3 is received.Next, host node 51-1 and slave node 51-3 is to the acknowledgement frame receiving In 84-1, contained above-mentioned Object node information is confirmed.As described above, acknowledgement frame 84-1 is with respect to host node 51-1 Frame.For this reason, host node 51-1 is by the acknowledgement frame 84-1 from slave node 51-2, synchronous correction can be processed and complete Held.Need exist for illustrating, although slave node 51-3 have received the propagation delay time and requires frame 81-1 (REQ S1), finish receiving frame 82-1 (S1), propagation delay time notification frame 83-1 (SET S1) and acknowledgement frame 84-1 (ANS S1), but, because not being the frame for this node, the frame being received is abandoned.

To the above, it is the notifying process in the propagation delay time being carried out to slave node 51-2.Accordingly, Host node 51-1 similarly also can carry out the notice in the propagation delay time with respect to slave node 51-3.

Specifically, in the example of Figure 11, host node 51-1 is to the propagation delay time with respect to slave node 51-3 (S2) Between require frame 81-2 (REQ S2), according to the synchronous base of host node, broadcast transmission is carried out on communication path 52.It is broadcasted The propagation delay time that have sent require frame 81-2 as mentioned above via communication path 52 scheduled transmission time delay (D1, D2) place is received by each slave node 51-2,51-3.

Because the propagation delay time requires the requirement that frame 81-2 is with respect to slave node 51-3, only subordinate Node 51-3 carries out the broadcast transmission finishing receiving frame 82-2 (S2) with respect to host node 51-1.The reception being sent is complete Framing 82-2 is received by host node 51-1 and slave node 52-2 via communication path 52.Finishing receiving frame 82-2 is phase Frame for host node 51-1.For this reason, host node 51-1 prolongs according to the transmission being sent from the synchronous base according to host node Late sending of time requirement frame 81-2 starts to docking the temporal information harvesting framing 82-2 is received, to respect to The propagation delay time of slave node 51-3 is set.Need exist for illustrating, here, set propagation delay time Between can carry out reciprocal reciprocal biography for prearranged signalss between host node 51-1 and slave node 51-3 via communication path 52 Defeated time delay, alternatively one way propagation delay time.

In addition, host node 51-1 generates for notifying to slave node 51-3 to the set propagation delay time Propagation delay time notification frame 83-2 (SET S2), and to propagation delay time notification frame 83-2 being generated according to main section The synchronous base of point carries out broadcast transmission.It is broadcasted propagation delay time notification frame 83-2 of transmission and above-mentioned propagation delay time Between require frame 81-2 similarly via communication path 52 at scheduled transmission time delay (D1, D2) place by each slave node 51- 2nd, 51-3 is received.

Now, slave node 51-3 is as described above, object according to propagation delay time notification frame 83-2 being received Nodal information, is judged as YES the information with respect to this node, and carries out containing propagation delay time contained by frame in and above-mentioned The synchronization correction of the 2nd embodiment of overhead time etc. is processed.In addition, slave node 51-3 generates with respect to propagation delay time Between notification frame 83-2 acknowledgement frame 84-2 (ANS S2), and broadcast transmission is carried out to the acknowledgement frame 84-2 being generated.Now, The information (Object node information) of frame and the expression synchronization that expression is with respect to host node 51-1 is contained in acknowledgement frame 84-2 Information that correction process completes etc..

The acknowledgement frame 84-2 being sent with above-mentioned finish receiving frame 82-2 in the same manner as via communication path 52 by host node 51-1 and slave node 52-2 is received.Next, host node 51-1 and slave node 51-2 is to institute in acknowledgement frame 84-2 The above-mentioned Object node information containing is confirmed.As described above, acknowledgement frame 84-2 is the frame with respect to host node 51-1.For This, host node 51-1, by the acknowledgement frame 84-2 from slave node 51-3, can complete to synchronous correction process and carry out handle Hold.Need exist for illustrating, although slave node 51-2 have received the propagation delay time and requires frame 81-2 (REQ S2), connects Harvest framing 82-2 (S2), propagation delay time notification frame 83-2 (SET S2) and acknowledgement frame 84-2 (ANS S2), but because For these frames all without respect to this node, so while have received also abandoning to these frames.

In the 2nd embodiment, by order above-mentioned process is carried out to each slave node of communication path 52, can be to biography Defeated time delay is notified.

Need exist for illustrating, for the notifying process in propagation delay time, be not limited to above-mentioned steps.Example As following manner may also be employed, that is,：Require frame to carry out broadcast transmission the propagation delay time, have received the subordinate that this requires frame Node 51-2,51-3 send acknowledgement frame, so that not carrying out influx on communication path 52 and host node 51-1, for example, can adopt Used in the inside of above-mentioned each node setting transmitting counter (sendcounter), and using this transmitting counter when different The mode that machine sends acknowledgement frame is controlled.

In above-mentioned 2nd embodiment, for example, in the system as Ethernet (registered trade mark) with star topology In, for the shared drive network employing time division multiple acess transmission means, can enter to exercise the counter synchronisation of each node Change, and then the Synchronization Control that control opportunity of making device overall is consistent.In addition, in the 2nd embodiment, the meter that just synchronizes For number device, in the case of using the enumerator within microcomputer, can use a counter to be constituted by hardware such as FPGA. So, in the 2nd embodiment, for example, by sending out the receiving time receiving (sending and receiving) frame, hard for example with FPGA etc. Part is come the enumerator to constitute the enumerator synchronous with host node and the process time to microcomputer is measured, and is counted by microcomputer Calculate its Counter Value, can make corrections to processing error.

Need exist for illustrating, the section in the above example, as of node synchronization system 50, principal and subordinate is belonged to Point is synchronous to be illustrated, but in the present invention, is not limited to this, for example, it is also possible to apply adopting in protective relay etc. In sample simultaneous techniquess.

＜ network transmission system：Schematic configuration example ＞

Need exist for illustrating, in above-mentioned 2nd embodiment, for example, exist and adopt HUB (collection between each node Line device) etc. relay situation about being attached.Figure 12 is host node and the slave node comprising to employ the 2nd embodiment One of the schematic configuration of the network transmission system of node synchronization system.Network transmission system 90 shown in Figure 12 has as one There are above-mentioned multiple nodes 51 (being node 51-1～51-3 in the example of Figure 12) and as one or more relays HUB91 (being HUB91-1～91-5 in the example of Figure 12).Need exist for illustrate, with regard to node, the quantity of relay, For species and method of attachment, it is not limited to this.

In the example of Figure 12, the host node of Fig. 7 is node 51-1 is node A (home site), and the slave node of Fig. 7 saves Point 51-2, node 51-3 are node B, node C (slave station).In addition, as shown in figure 12, the communication of network transmission system 90 Path is that for example have the star-like of relay between host node 51-1 and slave node 51-2.Need exist for explanation It is that relay employs HUB as one, but is not limited to this in the present invention, for example, can also use router, turn Send out device, photoconverter etc..

In addition, host node and slave node are, for example, Programmable Logic Controller (also referred to as control device or PLC (programmable logic controller)), the communication path of network transmission system 90 is for these programmable controls The data exchange bus that data between device processed swaps.As the machine being connected with this data exchange bus, for example, except Outside above-mentioned Programmable Logic Controller, also PC, server, I/O module, driving means (for example, changer, servomechanism installation etc.) Deng.

In network transmission system 90 shown in Figure 12, node 51-1 and node 51-3 are connected with same HUB12-1, Node 51-2 is connected with node 51-1 and node 51-3 via the HUB (relay) of 5 sections (5 grades).

Need exist for illustrating, in the HUB of general Ethernet, employ so-called storage and the interface side forwarding Formula.In this case, the frame sending is stored in the reception buffer in HUB, and is executing the inter-process of HUB Sent again after (for example, unusual determination and reception object judgement etc.).

Sequence example ＞ of ＜ node synchronization process

Figure 13 is the schematic diagram of the outline sequence example of node synchronization process.In the example of Figure 13, for convenience of explanation, to making It is illustrated with the synchronization of host node 51-1 and slave node 51-2, but is not limited to this in the present invention, also may be used So that multiple slave nodes synchronize with respect to 1 host node.

In the node synchronization process of Figure 13, first, host node 51-1 generates the 1st reference signal (S11), slave node 51-2 generates the 2nd reference signal (S12).In addition, this process is the process being carried out by the hardware cycle.

Here, host node 51-1, in order to be measured to the propagation delay time, generates propagation delay time requirement frame, and It is notified (S13) to slave node 51-2.Need exist for illustrating, it is only to same that the propagation delay time requires frame The frame that the data of the predetermined portions contained by stepization frame is changed, so it may also be said to it is synchronized frame, but, here For convenience's sake, illustrated using " propagation delay time requires frame ".

Propagation delay time requires frame to be sent to slave node 51-2 (S14) via communication path 52.Slave node After 51-2 receives propagation delay time requirement frame, generate reception completion notice, and notify to host node 51-1 (S15). Reception completion notice is sent to host node 51-1 (S16) via communication path 52.

After host node 51-1 receives reception completion notice, for example, calculate the reciprocal propagation delay time (S17), and generate The propagation delay time frame comprising reciprocal propagation delay time of being calculated etc. notifies (S18), then, the transmission being generated is prolonged Time frame notifies to be transmitted (S19) via communication path 52 to slave node 51-2 late.

After slave node 51-2 receives propagation delay time frame (S20), expense is measured (S21), and carry out as Upper described synchronization judges (S22), in the case of asynchronous, calculating total delay time (S23).Total delay time refers to example As the value be added the propagation delay time with overhead value after, but it is not limited to this.In addition, slave node 51-2 makes Synchronize correction (S24) with the total delay time being calculated.Need exist for illustrating, in the process shown in Figure 13, from Belong to node 51-2 and can also would indicate that the acknowledgement frame completing that synchronously makes corrections sends to host node 51-1.In addition, host node 51-1 is also adopted by above-mentioned steps for the slave node outside the slave node 51-2 being connected with communication path 52 and carries out node Synchronization process.

Here, in the present embodiment, by generate for make computer play as above-mentioned node 60 have each The program (node synchronisation procedure) of the function of unit, and the program being generated is attached to computer etc., can achieve above-mentioned each section The synchronization process of point.

As described above, according to the present invention, prearranged signalss can be made accurately to synchronize.Accordingly, for example, can achieve each section The stabilisation of the throughput of point.In addition, according to the present invention, such as in the system as Ethernet with star topology In, for the total internal memory network employing time division multiple acess transmission means, by making the timer synchronization of each node, Can achieve stabilisation of efficient activity, the efficient activity of data exchange and throughput of transmission etc..

Need exist for illustrating, present embodiment is applied to for example by multiple operation setting on a large scale to steel plant etc. Synchronous method in the case of being implemented for a series of action waiting, alternatively, it is also possible to overall as gigabit Ethernet Each device between the method for synchronization be widely suitable for.

Above presently preferred embodiments of the present invention is had been described in detail, but the present invention is not limited to above-mentioned specific embodiment party Formula, as long as in the range of the idea of the invention that claims are recorded, can carry out various deformation and change.

[symbol description]

10 signal synchronizing systems

11 processors

12 transfer bus

13rd, 53 I/O (input and output) module

14th, 54 external mechanical

15th, 55 programmer

21st, 61 the 1st calculating part

21-1,61-1 the 1st reference signal generating unit

22nd, 33,62,73 storage part

31st, 71 the 2nd calculating part

31-1,71-1 the 2nd reference signal generating unit

32-1,72-1 expense (overhead) determination part

32-2,72-2 count value obtaining section

32-3,72-3 synchronization detection unit

32-4,72-4 synchronization correcting section

41 input units

42 output sections

43 CPU

44 internal memories

45 external interfaces

50 node synchronization systems

51 nodes

52 communication paths

63 synchronized frame notification units

64 propagation delay time notification units

74 reception completion notice portions

75 frame notification units

81 propagation delay times required frame

82 finish receiving frame

83 propagation delay time notification frame

84 acknowledgement frames

90 network transmission systems

91 HUB (relay)

Claims (16)

1. a kind of signal synchronizing system is it is characterised in that have：

1st reference signal generating unit, wherein sets reference value, generates the 1st reference signal when count value reaches this reference value；

2nd reference signal generating unit, wherein sets described reference value, generates the 2nd reference when count value reaches this reference value Signal；

Calculating part, described 1st reference signal that described 1st reference signal generating unit of reception is generated simultaneously starts at synchronous correction Reason；

Expense determination part, receives described 1st reference signal and is simultaneously restarted, measure with this restart time point as starting point to described with Step correction processes the expense till being performed；

Count value obtaining section, after have passed through described expense, obtains described synchronous correction and processes described 2nd reference being performed time point The count value of signal generation portion；

Synchronous detection unit, when the count value acquired by described count value obtaining section is different with the value of described expense, is judged to institute State the 1st reference signal and described 2nd reference signal is asynchronous；And

Synchronous correcting section, if described synchronous detection unit is judged to that described 1st reference signal and described 2nd reference signal are non-same Step, then deduct the count value acquired by described count value obtaining section by the value from described expense, obtain synchronous compensating value, and will Deduct the value after calculated synchronous compensating value from described reference value to set to described 2nd reference signal life as temporal reference value One-tenth portion.

2. signal synchronizing system as claimed in claim 1 it is characterised in that：

Described 2nd reference signal generating unit is the enumerator that only can be accessed by described calculating part.

3. signal synchronizing system as claimed in claim 1 it is characterised in that：

The institute that described synchronous detection unit is measured to the count value acquired by described count value obtaining section and described expense determination part The value stating expense carries out time conversion, is judged to asynchronous when both time is different.

4. a kind of multiprocessor is it is characterised in that have primary processor and slave processor, wherein：

Described primary processor includes：

1st reference signal generating unit, wherein sets reference value, generates the 1st reference signal when count value reaches this reference value； And

1st calculating part, the described 1st reference signal synchronously configuration processor being generated with described 1st reference signal generating unit,

Described slave processor includes：

2nd reference signal generating unit, wherein sets described reference value, generates the 2nd reference when count value reaches this reference value Signal；

2nd calculating part, connects described 1st reference signal, described 2nd reference being generated with described 2nd reference signal generating unit Signal synchronously configuration processor, and start synchronous correction process after receiving described 1st reference signal；

Expense determination part, receives described 1st reference signal and is restarted, and measures the extremely described synchronous benefit restarted as starting point with this Just processing the expense till being performed；

Count value obtaining section, after have passed through described expense, obtains and is performed the described 2nd of time point in described synchronous correction process The count value of reference signal generating unit；

Synchronous detection unit, when the count value acquired by described count value obtaining section is different with the value of described expense, is judged to institute State the 1st reference signal and described 2nd reference signal is asynchronous；And

Synchronous correcting section, if described synchronous detection unit is judged to that described 1st reference signal and described 2nd reference signal are non-same Step, then deduct the count value acquired by described count value obtaining section by the value from described expense, obtain synchronous compensating value, and will Deduct the value after calculated synchronous compensating value from described reference value to set to described 2nd reference signal life as temporal reference value One-tenth portion.

5. multiprocessor as claimed in claim 4 it is characterised in that：

Described 2nd reference signal generating unit is the enumerator that only can be accessed by described 2nd calculating part.

6. multiprocessor as claimed in claim 4 it is characterised in that：

The institute that described synchronous detection unit is measured to the count value acquired by described count value obtaining section and described expense determination part The value stating expense carries out time conversion, is judged to asynchronous when both time is different.

7. multiprocessor as claimed in claim 4 it is characterised in that：

Each cycle ground exports described 1st reference signal,

Described 1st calculating part is controlled to the machine of external connection by each cycle ground execution described program.

8. multiprocessor as claimed in claim 4 it is characterised in that：

Described reference value can be set from the setting device of external connection.

9. multiprocessor as claimed in claim 4 it is characterised in that：

Described expense is the beginning time point processing from the starting point that described expense determination part is restarted to described synchronous correction Time.

10. a kind of node synchronization system is it is characterised in that have host node and slave node, wherein：

Described host node includes：

1st reference signal generating unit, wherein sets reference value, generates the 1st reference signal when count value reaches this reference value；

1st calculating part, the described 1st reference signal synchronously configuration processor being generated with described 1st reference signal generating unit；

Synchronized frame notification unit, is sent the synchronized frame being synchronized with described 1st reference signal to described via communication path Slave node；And

Propagation delay time notification unit, calculating is sent by described host node from described synchronized frame and receives to by described slave node Till propagation delay time, and this propagation delay time notified to described slave node,

Described slave node includes：

2nd reference signal generating unit, wherein sets described reference value, generates the 2nd reference when count value reaches this reference value Signal；

2nd calculating part, connects described 1st reference signal, described 2nd reference being generated with described 2nd reference signal generating unit Signal synchronously configuration processor, and start synchronous correction process after receiving described 1st reference signal；

Expense determination part, receives described 1st reference signal and is restarted, and measures the extremely described synchronous benefit restarted as starting point with this Just processing the expense till being performed；

Count value obtaining section, after have passed through described expense, obtains described synchronous correction and processes described 2nd reference being performed time point The count value of signal generation portion；

Synchronous detection unit, by making the value in described propagation delay time and the value phase of described expense that described host node notified Plus, obtain total delay time value, and to described in acquired by calculated aggregate latency time value and described count value obtaining section The count value of the 2nd reference signal generating unit is compared, and is judged to the 1st reference signal and the 2nd reference signal when both are different Asynchronous；And

Synchronous correcting section, if described synchronous detection unit is judged to that described 1st reference signal and described 2nd reference signal are non-same Step, then by deducting the count value acquired by described count value obtaining section from described total delay time value, obtain synchronous compensating value, And arrange deducting the value after calculated synchronous compensating value from described reference value to the described 2nd with reference to letter as temporal reference value Number generating unit.

11. node synchronization systems as claimed in claim 10 it is characterised in that：

Described propagation delay time notification unit will require frame to send to described slave node in the propagation delay time, receive with respect to institute State the frame that finishes receiving from described slave node that the propagation delay time requires frame, and according to moment during this reception and described The difference between moment when propagation delay time requires frame to send, calculates the described propagation delay time.

12. node synchronization systems as claimed in claim 10 it is characterised in that：

Described communication path is the star-like path between described host node and described slave node with relay.

13. node synchronization systems as claimed in claim 10 it is characterised in that：

Described 2nd reference signal generating unit is the enumerator that only can be accessed by described 2nd calculating part.

14. node synchronization systems as claimed in claim 10 it is characterised in that：

Described synchronous detection unit carries out the time to the count value acquired by described count value obtaining section and described total delay time value Conversion, is judged to asynchronous when both time is different.

15. node synchronization systems as claimed in claim 10 it is characterised in that：

Described reference value can be set from the setting device being connected with described host node or described slave node.

16. node synchronization systems as claimed in claim 10 it is characterised in that：

Described expense is the beginning time point processing from the starting point that described expense determination part is restarted to described synchronous correction Time.