WO2014091592A1

WO2014091592A1 - Signal synchronization system, node synchronization system, signal synchronization method, and node synchroniz ation method

Info

Publication number: WO2014091592A1
Application number: PCT/JP2012/082334
Authority: WO
Inventors: 崇光井
Original assignee: 富士電機株式会社
Priority date: 2012-12-13
Filing date: 2012-12-13
Publication date: 2014-06-19
Also published as: KR20150084917A; JP5825446B2; CN104838615A; KR101636496B1; JPWO2014091592A1; CN104838615B

Abstract

A main module performs counting and generates a first reference signal from the count value rea ching a preset reference value. A sub-module performs counting, generates a second reference signal from the count value reaching a reference value, counts an interval at which a synchronization correction process is performed, and, after the count value reaches a correction processing interval value for the synchronization correction process to be performed, receives the first reference signal, whereupon the sub-module restarts and continues to count. Then, after a count value indicating an interval at which the synchronization correction process is performed reaches the correction processing interval value, the sub- module acquires a count value for generating the second reference signal and a count value restarted after receiving the first reference signal, and temporarily sets a value for offsetting the difference between the count value for generating the second reference signal and the count value restarted after receiving the first reference signal, the offsetting value being set as a reference value to the count value for generating the second reference signal.

Description

Signal synchronization system, node synchronization system, signal synchronization method, and node synchronization method

The present invention relates to a signal synchronization system, a node synchronization system, a signal synchronization method, and a node synchronization method for synchronizing predetermined signals.

Conventionally, when a predetermined program is executed using a processor or the like, a multiprocessor system that executes processing using a plurality of processors for the purpose of dealing with large-scale processing, speeding up processing, load distribution, etc. It has been known. In such a multiprocessor system, in order to synchronize counters (timers) among a plurality of processors, an interrupt signal is generated from the main processor to the counter of the slave processor, and the slave processor matches the interrupt signal. The counter is synchronized.

Also, in an industrial network such as a conventional transmission system for plant control, it is necessary for each device constituting the system to exchange large amounts of data with each other while guaranteeing real-time performance. Therefore, for example, when mutual access is performed in an event according to the occurrence of an access request by an application installed in each device, the network load depends on the application, and real-time performance cannot be guaranteed. There is.

Therefore, conventionally, there is a technology in which each device is provided with a virtual shared memory (common memory) and transmits its own node data to all nodes (stations) on the network at the update timing. When such a technique is used, each received node updates its data and accesses an application, thereby realizing a data exchange method that guarantees real-time performance. Conventionally, there has been proposed a method for realizing efficient broadcast communication (broadcast communication) on a network at the time of data exchange described above (see, for example, Patent Document 1).

In Patent Document 1, the time division multiple access method using the internal timer of each node and the internal timer correction of the slave node using the synchronization frame from the master node are used together. In the method shown in Patent Document 1, the transmission path is configured as a network connected by a bus or a serial cable.

JP 2005-159754 A

By the way, in the counter synchronization correction processing between the main processor and the slave processor as described above, it is preferable to reset the counter of the slave processor directly (in hardware) from the main processor. However, since this counter is a counter that serves as an execution reference for a plurality of program processes performed internally, problems may occur in other processes if the counter is rewritten without permission. Further, when the counter is built in a CPU (Central Processing Unit) of the slave processor, the counter of the slave processor cannot be reset directly from the master processor. Therefore, conventionally, an interrupt signal is once transmitted from the main processor to the slave processor, and the slave processor receives the signal and executes a counter reset process indirectly (software) using predetermined software.

In such a case, the slave processor generates a delay time due to overhead or the like after receiving the interrupt signal from the main processor until executing the reset processing of its own counter corresponding to the signal. Therefore, conventionally, even if reset processing is performed, a counter synchronization error between the main processor and the slave processor remains.

Also, for synchronization of counters between nodes in a master-slave relationship between networks, for example, a method of receiving a synchronization frame and clearing a timer can be considered. However, as described above, if the counter is cleared by firmware after receiving the synchronization frame, an error occurs in the counter due to a delay time such as overhead.

Therefore, even if the synchronization method between nodes using the synchronization frame, which is the conventional method, if the microcomputer firmware corrects the measurement of the synchronization time between the master node and each slave node, the microcomputer processing time An error will occur.

Therefore, in order to suppress the influence on the other processing due to the rewriting of the counter, the interrupt signal transmitted from the main processor to the slave processor is counted by hardware, and based on the difference from the counter in the slave processor, It can be considered that the main processor and the slave processor are synchronized by adjusting the counting target (reference value) of the counter.

The counter of the main processor and the counter of the slave processor have different electrical characteristics, so it is difficult to estimate how much the counter shifts between the main processor and the slave processor. Therefore, if the synchronization correction process for adjusting the reference value of the counter of the slave processor is performed for each interrupt signal, the master processor and the slave processor are kept synchronized. However, if the synchronization correction process is frequently performed, the processing load increases, which may affect other processes that should be executed.

The present invention has been devised in view of the above points. A signal synchronization system, a node synchronization system, a signal synchronization method, and a node synchronization method that synchronize a predetermined signal with high accuracy while suppressing a processing load. The purpose is to provide.

In order to solve the above problem, the signal synchronization of the present invention includes a main module that operates according to a first reference signal and a slave module that operates according to a second reference signal, and synchronizes the second reference signal with the first reference signal. The system includes a first reference signal generation unit that generates a first reference signal when the main module performs a count and the count value reaches a preset reference value, and the slave module performs a count and performs a reference value The second reference signal generating unit that generates the second reference signal when the count value reaches the time, the interval counting unit that counts the interval for performing the synchronization correction processing, and the correction processing interval value for performing the synchronization correction processing in the interval counting unit. After the count value has been reached, the first reference signal is received and restarted, and an overhead counter for counting, and after the count value reaches the correction processing interval value in the interval counter, the first reference signal is received. A counter value acquisition unit that acquires the count value of the second reference signal generation unit and the count value of the overhead counter unit, and a value that cancels the difference between the count value of the second reference signal generation unit and the count value of the overhead counter unit And a synchronization correction unit that temporarily sets the reference value as a reference value in the second reference signal generation unit.

In addition, what applied the arbitrary combination of the component of this invention, the expression, or the component to a method, an apparatus, a system, a computer program, a recording medium, a data structure, etc. is effective as an aspect of this invention.

According to the present invention, it is possible to synchronize a predetermined signal with high accuracy while suppressing a processing load.

It is a figure which shows an example of schematic structure of the signal synchronization system in 1st Embodiment. It is a figure which shows an example of the hardware constitutions of a processor module. It is a time chart figure (the 1) for explaining the example of synchronous amendment processing in a 1st embodiment. It is a time chart figure (2) for explaining the example of synchronous correction processing in a 1st embodiment. FIG. 6 is a time chart (part 3) for explaining an example of synchronization correction processing in the first embodiment; It is a figure which shows the schematic example of a sequence of a signal synchronization method. It is a figure which shows an example of schematic structure of the node synchronous system in 2nd Embodiment. It is a time chart figure (the 1) for explaining an example of synchronous amendment processing in a 2nd embodiment. It is a time chart figure (the 2) for explaining an example of synchronous amendment processing in a 2nd embodiment. It is a time chart figure (the 3) for explaining the example of synchronous amendment processing in a 2nd embodiment. It is a figure for demonstrating an example of the notification procedure of the transmission delay time in 2nd Embodiment. It is a figure which shows an example of schematic structure of the network transmission system containing the node synchronous system using the master node and slave node in 2nd Embodiment. It is a figure which shows the schematic sequence example of a node synchronization method.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The dimensions, materials, and other specific numerical values shown in the embodiment are merely examples for facilitating understanding of the invention, and do not limit the present invention unless otherwise specified. In the present specification and drawings, elements having substantially the same function and configuration are denoted by the same reference numerals, and redundant description is omitted, and elements not directly related to the present invention are not illustrated. To do.

(About this embodiment)
In the present embodiment, for example, when counter (timer) synchronization is performed between modules having a master-slave relationship such as a plurality of processor modules or a plurality of nodes, devices, and boards each including at least one processor module, the main module side In response to the interrupt signal (counter reset signal) from, the overhead value on the slave module side is obtained. In the present embodiment, the synchronization correction process is performed based on the obtained overhead value and the counter on the slave module side.

However, if the synchronization correction process is frequently executed, the processing load increases. Therefore, in this embodiment, the interval for performing the synchronization correction process is counted and synchronized periodically (intermittently) for each predetermined correction process interval value. Execute correction processing.

Also, in this embodiment, when the master-slave device is a master node and a slave node, the synchronization correction process is performed in consideration of the delay time (transmission delay time) on the communication path.

Hereinafter, embodiments in which the signal synchronization system and the node synchronization system in the present embodiment are preferably implemented will be described with reference to the drawings.

(First embodiment: signal synchronization system)
FIG. 1 is a diagram illustrating an example of a schematic configuration of a signal synchronization system according to the first embodiment. The signal synchronization system 10 shown in FIG. 1 shows an example of a multiprocessor for performing counter synchronization among a plurality of processor modules (modules 11a to 11c in the example of FIG. 1) as an example. .

A signal synchronization system 10 shown in FIG. 1 includes a plurality of processor modules 11a to 11c (hereinafter referred to as “processor module 11” as necessary), a transmission bus 12, and an I / O (input / output) module 13 (FIG. 1). And 13a to 13d), an external device 14 (indicated by 14a to 14d in FIG. 1), and a programming device 15. Here, in the example of FIG. 1, for convenience of explanation, the main configuration of each processor module will be described with the processor module 11 a as a main processor module and the

processor modules

11 b and 11 c as slave processor modules. However, the number of slave processor modules is not limited to two as shown in FIG.

In the present embodiment, the present invention is not limited to the above-described configuration, and has the same configuration so that one processor module can be the main processor module 11a and the

slave processor modules

11b and 11c. . Each processor module 11 is connected by a transmission bus 12. In the first embodiment, it is assumed that there is no delay time caused by the transmission bus 12.

Here, the main processor module 11 a includes a first reference signal generation unit 21, a first calculation unit 22, and a storage unit 23. In the example of FIG. 1, the first reference signal generation unit 21 is built in a CPU to be described later, but is not limited to this. For example, the first reference signal generation unit 21 and the CPU are separate. It may be configured. Further, the above-described “built-in” means that only the function units (the first reference signal generation unit 21 and the first calculation unit 22) in the CPU can access the first reference signal generation unit 21, for example. Means.

The

slave processor modules

11b and 11c include a second reference signal generator 31, a second calculator 32, an interval counter 33, an overhead counter 34, a count value acquisition unit 35, and a synchronization determination unit 36. , A synchronization correction unit 37 and a storage unit 38. In the example of FIG. 1, the second reference signal generation unit 31 is built in the CPU. However, the present invention is not limited to this. For example, the second reference signal generation unit 31 and the CPU are configured separately. It may be.

The first reference signal generator 21 performs counting and generates a first reference signal when the count value reaches a preset reference value. The first reference signal generation unit 21 functions as a hardware counter (hereinafter also referred to as “timer” as necessary). The above-described count value is cyclically counted based on the reference value. In FIG. 1, such a hardware counter is indicated by a broken line.

The first calculation unit 22 executes (calculates) a predetermined application program stored in the storage unit 23 according to the first reference signal generated by the first reference signal generation unit 21. The first reference signal is also given (transmitted) to the

slave processor modules

11b and 11c through the transmission bus 12 as an interrupt signal (counter reset signal).

The storage unit 23 stores a predetermined application program (sequence program) to be calculated by the first calculation unit 22. The predetermined application program calculated by the first calculation unit 22 is a process for giving an instruction to, for example, the I / O module 13a connected to the main processor module 11a and controlling the external device 14a by the I / O module 13a. . Therefore, the storage unit 23 stores a program for executing predetermined processing mainly on the I / O module 13a and the external device 14a connected to the own processor module 11a.

That is, the main processor module 11a generates a first reference signal at predetermined intervals, and the first calculation unit 22 executes (calculates) an application program (sequence program) in accordance with the first reference signal. The device is controlled, and the application program (sequence program) is cyclically executed.

Next, the

slave processor modules

11b and 11c will be described. Since the

slave processor modules

11b and 11c have the same configuration, in the following description, the slave processor module 11b will be described, and the slave processor module 11c will be described. Omitted.

The second reference signal generation unit 31 performs counting, sets the same reference value as the reference value set in the first reference signal generation unit 21 described above, and reaches the reference value to reach the second reference value. Generate a signal. The second reference signal generation unit 31 functions as a hardware counter. The above-described count value is cyclically counted based on the reference value. In addition, the counters of the first reference signal generation unit 21 and the second reference signal generation unit 31 are free running counters and are self-running.

The second calculation unit 32 executes (calculates) a predetermined application program or the like stored in the storage unit 38 in accordance with the second reference signal generated by the second reference signal generation unit 31.

The second reference signal generation unit 31 is a counter that can be accessed only from the second arithmetic unit 32 in the CPU, for example, and is a counter (CPU built-in counter) built in the CPU. That is, the second reference signal generation unit 31 is a counter that cannot be reset in hardware from the outside of the main processor module 11a and the like.

Further, the second calculation unit 32 receives the first reference signal (synchronization reference signal) from the main processor module 11a as an interrupt signal, and activates a synchronization correction process described later.

The interval counting unit 33 performs counting and generates a correction processing start signal indicating that a correction processing interval value corresponding to a correction processing interval for performing synchronization processing is set in advance and reaches the correction processing interval value. To do.

The correction processing interval value is set through the following calculation. For example, it is assumed that the synchronization error between the main processor module 11a and the slave processor module 11b, which is allowed to satisfy the processing accuracy required for the signal synchronization system, is 10 μs. In this case, in this embodiment, the shortest time until the synchronization error reaches 1 to 5 μs is calculated. Here, the reason why it is 1 μs or more is that if it is shorter than that, the frequency of synchronization correction processing increases and the processing load increases. The reason why it is 5 μs or less is that the margin for 10 μs is taken into consideration.

At this time, it is assumed that the frequency of the oscillator used in the main processor module 11a and the sub processor module 11b is 50 MHz and the oscillation accuracy is 50 ppm. Under this condition, the shortest time when the synchronization error is 1 μs is the time of 1 clock × the number of oscillations deviating from the synchronization tolerance, and is 20 ns × ((1 μs / 20 ns) × (1/50 ppm)) = 20 ms. Similarly, the shortest time when the synchronization error is 5 μs is 100 ms. Therefore, the correction processing interval value may be a value obtained by converting 20 ms to 100 ms into a count value. By setting the correction processing interval value in such a range and executing the synchronous correction processing intermittently, it is possible to realize higher machining accuracy and improved production quality while suppressing the processing load.

The overhead counting unit 34 counts and synchronizes after reception of the first reference signal described above after reception of the correction processing start signal, that is, after the count value of the interval counting unit 33 reaches the correction processing interval value. The overhead value until the correction process is executed is measured. Specifically, the overhead counter 34 functions as a hardware counter (timer) that receives and restarts the first reference signal.

Since the overhead counting unit 34 is a counter configured by hardware, it reacts immediately to the first reference signal. However, the synchronization correction processing takes time until preparation for reading the count value is completed, for example. The time required to prepare for reading the count value is an overhead. The overhead means a delay time from the occurrence of a certain event until the processing (software) for the event is actually executed. In this example, the overhead is synchronized from the starting point when the overhead counting unit 34 is restarted. The time until correction processing is actually performed is not limited to this.

After receiving the correction processing start signal, that is, after the count value of the interval counter 33 reaches the correction processing interval value, the count value acquisition unit 35 actually executes the synchronization correction processing in response to reception of the first reference signal. The count value of the second reference signal generation unit 31 and the count value of the overhead count unit 34 at the time (starting point) to be obtained are acquired.

When the count value of the second reference signal generation unit 31 and the count value of the overhead count unit 34 acquired by the count value acquisition unit 35 are equal to each other, the synchronization determination unit 36 determines that the first reference signal and the second reference signal are It is determined that they are synchronized. Further, the synchronization determination unit 36, when the count value of the second reference signal generation unit 31 and the count value of the overhead counter 34 acquired by the count value acquisition unit 35 are different from each other, It is determined that the reference signal is asynchronous.

The synchronization determination unit 36 converts the count value of the second reference signal generation unit 31 acquired by the count value acquisition unit 35 and the count value of the overhead count unit 34 into time, and synchronizes when both times are equal. It can also be determined that it is asynchronous, and when both times are different, it can also be determined that they are asynchronous. That is, in the first embodiment, the unit time per clock of each counter may not be equal between the processor modules 11. Therefore, in such a case, each count value is converted into time, and synchronous / asynchronous determination is performed at the converted time.

The synchronization correction unit 37 sets the reference value in the second reference signal generation unit 31 when the synchronization determination unit 36 determines that the first reference signal and the second reference signal are synchronized. In addition, when the synchronization determination unit 36 determines that the first reference signal and the second reference signal are asynchronous, the synchronization correction unit 37 determines the count value of the second reference signal generation unit 31 and the count value of the overhead count unit 34. The value which cancels the difference of is obtained. Specifically, the synchronization correction unit 37 subtracts the count value of the overhead counter 34 from the count value of the second reference signal generation unit 31 acquired by the count value acquisition unit 35 to obtain the synchronization correction value. Next, the synchronization correction unit 37 subtracts the obtained synchronization correction value from the reference value, and sets the subtracted value as a new reference value in the second reference signal generation unit 31. The new reference value is a timer that is temporarily used when the synchronization determination unit 36 determines asynchronous with respect to the timer reference value (default reference value) used when the synchronization determination unit 36 determines synchronization. This is the reference value.

Further, the synchronization determination unit 36 determines that the first reference signal and the second reference signal are asynchronous, sets the subtracted value as a new reference value in the second reference signal generation unit 31, and uses the subtracted value. When the counting is completed, the synchronization correction unit 37 quickly sets the reference value in the second reference signal generation unit 31. Thus, the reference value can be temporarily changed by the synchronization correction value. Here, an example is given in which the correction for the synchronization correction value is executed at a time, but the present invention is not limited to this, and it may be executed in multiple steps. Even in that case, the synchronization correction unit 37 sets the reference value in the second reference signal generation unit 31 after the synchronization correction processing is completed.

The synchronization correction unit 37 sets the above-described default reference value in the second reference signal generation unit 31 each time the synchronization determination unit 36 determines the synchronization between the first reference signal and the second reference signal. However, if synchronization is maintained, once the default reference value is set, nothing needs to be done.

In the present embodiment, since the synchronization correction process is executed at every correction process interval, there is a high possibility that the count value of the second reference signal generation unit 31 and the count value of the overhead count unit 34 are different, and the synchronization determination unit Often, 36 determines that the first reference signal and the second reference signal are asynchronous. Therefore, the synchronization correction unit 37 does not execute the determination by the synchronization determination unit 36, that is, regardless of whether the first reference signal and the second reference signal are synchronous or asynchronous, the synchronization correction unit 37 performs the second reference signal generation unit. A value that cancels the difference between the count value of 31 and the count value of the overhead counter 34 may be obtained, and the value may be set as a new reference value in the second reference signal generator 31.

Thus, by omitting the configuration of the synchronization determination unit 36, the determination process becomes unnecessary, and the processing load for the determination can be reduced.

The storage unit 38 stores a predetermined application program (sequence program) that is calculated by the second calculation unit 32. The predetermined application program calculated by the second calculation unit 32 gives instructions to the I / O modules 13b and 13c connected to the slave processor module 11b, for example, and the external devices 14b and 14c are transmitted by the I / O modules 13b and 13c. It is a process to control. Therefore, the storage unit 38 stores a program for executing predetermined processing mainly on the I / O modules 13b and 13c and the external devices 14b and 14c connected to the own processor module 11b.

The I / O module 13 performs input / output processing with the external device 14 and the like. For example, the I / O module 13 outputs (transmits) data or the like obtained from the connected external device 14 or the like to the processor module 11, or outputs a result processed by the processor module 11 to the external device 14 or the like. Or remember. That is, the processor module 11 controls the external device 14 by calculating the input data obtained from the I / O module 13 by the application program and giving the calculation result to the I / O module 13 as output data.

The external device 14 is, for example, various sensors, motors, recording devices, or the like. The external device 14 detects and drives data, inputs / outputs data, and the like based on a control signal from the I / O module 13.

Here, the reference value may be set in advance in each of the processor module 11a, the processor module 11b, and the processor module 11c, or may be set from a programming device 15 (setting device) externally connected thereto.

The programming device 15 can be realized by adding a function for setting a reference value by communicating with the processor module 11 to a PC (Personal Computer) used by a user or the like. It may be a device. Thereby, a reference value (processing cycle) can be arbitrarily adjusted for each user.

Here, in the above-described example, the multiprocessor has been described as an example of the signal synchronization system 10. However, the signal synchronization system 10 includes a first reference signal generation unit 21, a second reference signal generation unit 31, and an overhead counting unit. 34, the count value acquisition unit 35, the synchronization determination unit 36, and the synchronization correction unit 37 may be included.

The application example of the signal synchronization system 10 is not limited to a multiprocessor. For example, the main device side is a transmitting station that transmits a digital signal of date / time information by an atomic clock, and the slave device side is a radio wave clock. Application as a timer synchronization system is also possible.

(Hardware configuration example of the processor module 11)
Next, a hardware configuration example of the processor module 11 will be described with reference to the drawings. FIG. 2 is a diagram illustrating an example of a hardware configuration of the processor module 11. The processor module 11 illustrated in FIG. 2 includes an input unit 41, an output unit 42, a CPU 43, an FPGA 44, a memory 45, and an external interface 46, which are connected by a common bus B.

The input unit 41 inputs various operation signals such as execution of a program from a user or the like. Note that the input unit 41 may have a keyboard operated by a user or the like, a pointing device such as a mouse or a touch panel, and may have a voice input device when inputting by voice or the like. .

The output unit 42 includes a display that displays various windows and data necessary for operating the processor module 11 that performs processing in the present embodiment, and displays the execution progress and results of the control program executed by the CPU 43. .

Based on a control program such as an OS (Operating System) and an execution program stored in the memory 45, the CPU 43 performs processing of the entire processor module 11 such as various operations and data input / output with each hardware component. Each process in this embodiment is realized by controlling. In addition, the CPU 43 cooperates with the memory 45 to substantially function as the first calculation unit 22, the second calculation unit 32, the count value acquisition unit 35, the synchronization determination unit 36, and the synchronization correction unit 37 described above. A first reference signal generation unit 21 and a second reference signal generation unit 31 are incorporated. Various information necessary during program execution may be acquired from the memory 45 and the execution result or the like may be stored in the memory 45.

An FPGA (Field-Programmable Gate Array) 44 is an integrated circuit that can rewrite a logic circuit. The FPGA 44 is composed of various logic circuits that assist the CPU 43, and particularly functions as the interval counting unit 33 and the overhead counting unit 34 in the present embodiment. However, the interval counting unit 33 may be processed by software.

The memory 45 stores an execution program read by the CPU 43 and the like. The memory 45 includes a ROM (Read Only Memory), a RAM (Random Access Memory), and the like. Further, the memory 45 may have storage means such as a hard disk as an auxiliary storage device. The memory 45 stores an execution program in the present embodiment, a control program provided in a computer, and the like, and performs input / output as necessary. The memory 45 corresponds to the

storage units

23 and 38 described above.

The external interface 46 transmits / receives data and control signals to / from other processor modules 11 via the transmission bus 12 and the like. The external interface 46 also transmits / receives data and control signals to / from the connected I / O module 13.

With the hardware configuration described above, it is possible to execute the synchronization correction processing in this embodiment. In addition, by installing the execution program, the synchronization correction processing in the present embodiment can be easily realized by a general-purpose personal computer or the like.

Next, an example of synchronization correction processing in the first embodiment will be described below.

(Example of synchronization correction processing in the first embodiment)
3 to 5 are time chart diagrams (No. 1 to No. 3) for explaining an example of the synchronization correction processing in the first embodiment. In the example shown in FIGS. 3 to 5, an example of synchronization of count values between the main processor module 11a and the slave processor module 11b is shown. The reference value (processing cycle) in the first embodiment is 1000 μs, but is not limited to this. For example, the setting can be appropriately changed by the programming device 15 described above.

In FIG. 3, the first reference signal generator 21 of the main processor module 11a performs counting. When the count value reaches the reference value at time (1) in FIG. 3, a first reference signal is output. And the 1st calculating part 22 performs a predetermined | prescribed process according to the said 1st reference signal. In FIG. 3, a triangular area indicated by hatching indicates the transition of the count value, and the count value increases as time passes, and is reset when the count target (for example, a reference value) is reached.

Further, the second reference signal generation unit 31 of the slave processor module 11b performs counting. When the count value reaches the reference value at time (2) in FIG. 3, a second reference signal is output. And the 2nd calculating part 32 performs a predetermined | prescribed process according to the said 2nd reference signal. In this manner, the main processor module 11a and the slave processor module 11b perform predetermined processing according to the independent first reference signal and second reference signal, respectively.

In the slave processor module 11b, the interval counter 33 performs counting, and when the count value reaches the correction processing interval value ((3) in FIG. 3), a correction processing start signal is generated. In response to the correction processing start signal, preparation for the synchronous correction processing is started.

The first reference signal generated by the main processor module 11a is transmitted to the slave processor module 11b as an interrupt signal. The slave processor module 11b receives the first reference signal as an interrupt, and starts a synchronization correction process by software ((4) in FIG. 3). At the same time, the overhead counter 34 of the slave processor module 11b clears the counter value by the hardware and restarts ((5) in FIG. 3). Subsequently, when the preparation for the synchronization correction process is completed, the count value acquisition unit 35 acquires the count value from the second reference signal generation unit 31 ((7) in FIG. 3) at the time (6) in FIG. The count value is acquired from the overhead counter 34 ((8) in FIG. 3).

The synchronization determination unit 36 converts the count value given by the count value acquisition unit 35 into time. Here, for example, it is assumed that 300 μs is obtained from the count value of the second reference signal generation unit 31 and 300 μs is obtained from the count value of the overhead counting unit 34. Thus, the overhead from when the first reference signal is interrupted until the count value is acquired in the synchronization correction process can be measured, and the count value of the second reference signal generation unit 31 at that time can be acquired. When the first reference signal and the second reference signal are synchronized, the count values should be equal.

The synchronization determination unit 36 compares the count value (300 μs) of the second reference signal generation unit 31 obtained from the count value acquisition unit 35 with the count value (300 μs) of the overhead count unit 34. In this case, the synchronization determination unit 36 determines that the first reference signal and the second reference signal are synchronized because both are the same value.

Since the synchronization determination unit 36 determines that the first reference signal and the second reference signal are synchronized, the synchronization correction unit 37 sets the reference value 1000 μs in the second reference signal generation unit 31 as usual. (At this time, the second reference signal generator 31 has not restarted). Then, the second reference signal generation unit 31 restarts because the count value reaches the reference value 1000 μs at the time (9) in FIG.

The second reference signal generation unit 31 is built in the CPU 43 described above. However, in the present embodiment, the second reference signal generation unit 31 is not limited to this and may be separate from the CPU 43.

Also, as will be added, the synchronization correction processing shown in FIG. 3 includes the program processing of the count value acquisition unit 35, the synchronization determination unit 36, and the synchronization correction unit 37.

FIG. 4 shows a case where the counter of the slave processor module 11b is delayed by 3 μs from the counter of the main processor module 11a.

In FIG. 4, the interval counter 33 of the slave processor module 11b performs counting, and when the count value reaches the correction processing interval value ((1) in FIG. 4), a correction processing start signal is generated. In response to the correction processing start signal, preparation for the synchronous correction processing is started.

The first reference signal generation unit 21 of the main processor module 11a outputs the first reference signal every 1000 μs because the count value reaches the reference value. After the correction processing start signal is generated, the slave processor module 11b receives the first reference signal as an interrupt, and starts the synchronous correction processing by software ((2) in FIG. 4). At the same time, the overhead counter 34 of the slave processor module 11b clears and restarts the counter value counted by the hardware ((3) in FIG. 4). Subsequently, when the preparation for the synchronization correction process is completed, the count value acquisition unit 35 acquires the count value from the second reference signal generation unit 31 ((5) in FIG. 4) at the time (4) in FIG. The count value is acquired from the overhead counter 34 ((6) in FIG. 4).

The synchronization determination unit 36 converts the count value given by the count value acquisition unit 35 into time. Here, for example, it is assumed that 297 μs is obtained from the count value of the second reference signal generation unit 31 and 300 μs is obtained from the count value of the overhead counting unit 34. The synchronization determination unit 36 compares the two count values and determines that the first reference signal and the second reference signal are asynchronous because the two count values are different.

Since the synchronization determination unit 36 determines asynchronism, the synchronization correction unit 37 generates the second reference signal so that the difference between the count value of the second reference signal generation unit 31 and the count value of the overhead count unit 34 is canceled out. A temporary reference value is set in the part 31. Specifically, the synchronization correction unit 37 uses the expression “reference value (processing period) − (count value of the overhead counter 34 −count value of the second reference signal generator 31)” to calculate the second reference signal generator. A restart value (reset value) of the count value of 31 is obtained, and the obtained count value is set in the second reference signal generation unit 31 as a temporary reference value. In this example, the temporary reference value is 1000 μs− (300 μs−297 μs) = 997 μs. Then, the second reference signal generation unit 31 restarts because the count value reaches the temporary reference value 997 μs at the time (7) in FIG. Incidentally, the count value of the overhead counter 34 minus the count value of the second reference signal generator 31 is the synchronization correction value.

By doing in this way, 1st Embodiment can restart the 2nd reference signal production | generation part 31 at the substantially same timing as the output timing of the 1st reference signal of the following 3rd cycle with respect to a 2nd cycle. it can. Therefore, the first embodiment can synchronize the first reference signal and the second reference signal. In the case of FIG. 4, the reference value is set to 1000 μs after the third cycle.

FIG. 5 shows a case where the counter of the slave processor module 11b is advanced by 3 μs from the counter of the main processor module 11a.

In FIG. 5, the interval counter 33 of the slave processor module 11b performs counting, and when the count value reaches the correction processing interval value ((1) in FIG. 5), a correction processing start signal is generated. In response to the correction processing start signal, preparation for the synchronous correction processing is started.

The first reference signal generation unit 21 of the main processor module 11a outputs the first reference signal every 1000 μs because the count value reaches the reference value. After the correction processing start signal is generated, the slave processor module 11b receives the first reference signal as an interrupt, and starts the synchronous correction processing by software ((2) in FIG. 5). At the same time, the overhead counting unit 34 of the slave processor module 11b clears the count value of the counter by the hardware and restarts ((3) in FIG. 5). Subsequently, when the preparation for the synchronization correction process is completed, the count value acquisition unit 35 acquires the count value from the second reference signal generation unit 31 ((5) in FIG. 5) at the time (4) in FIG. The count value is acquired from the overhead counter 34 ((6) in FIG. 5).

The synchronization determination unit 36 converts the count value given by the count value acquisition unit 35 into time. Here, for example, it is assumed that 303 μs is obtained from the count value of the second reference signal generation unit 31 and 300 μs is obtained from the count value of the overhead counting unit 34. The synchronization determination unit 36 compares the two count values and determines that the first reference signal and the second reference signal are asynchronous because the two count values are different values.

Since the synchronization determination unit 36 determines asynchronism, the synchronization correction unit 37 generates the second reference signal so that the difference between the count value of the second reference signal generation unit 31 and the count value of the overhead count unit 34 is canceled out. A temporary reference value is set in the part 31. Specifically, the synchronization correction unit 37 calculates in the same manner as in the description of FIG. 4, obtains a temporary reference value, and sets it in the second reference signal generation unit 31. In this example, the temporary reference value is 1000 μs− (300 μs−303 μs) = 1003 μs. Then, the second reference signal generation unit 31 restarts because the count value reaches the temporary reference value 1003 μs at the point (7) in FIG. Incidentally, the count value of the overhead counter 34 minus the count value of the second reference signal generator 31 is the synchronization correction value.

By doing in this way, 1st Embodiment can restart the 2nd reference signal production | generation part 31 at the substantially same timing as the output timing of the 1st reference signal of the following 3rd cycle with respect to a 2nd cycle. it can. Therefore, the signal synchronization system of the present embodiment can synchronize the first reference signal and the second reference signal. Note that the reference value is set to 1000 μs after the third cycle in FIG. As described above, in the first embodiment, counter synchronization can be appropriately realized both when the counter (timer) of the slave processor module 11b is delayed or advanced with respect to the counter (timer) of the main processor module 11a. it can.

(Sequence example of signal synchronization method)
FIG. 6 is a diagram illustrating a schematic sequence example of the signal synchronization method. In the example of FIG. 6, for the sake of convenience of explanation, synchronization using the main processor module 11a and the sub processor module 11b will be described. However, the present embodiment is not limited to this, and one main processor module is not limited to this. Multiple slave processor modules can be synchronized.

In the counter synchronization processing of FIG. 6, first, the first reference signal generation unit 21 of the main processor module 11a generates a first reference signal (S01), and the second reference signal generation unit 31 of the slave processor module 11b Two reference signals are generated (S02). This process is cyclically operated in terms of hardware. The main processor module 11a also transmits the first reference signal obtained in the process of S01 to the slave processor module 11b. Therefore, the slave processor module 11b is always in a state where it can receive the first reference signal.

The interval counting unit 33 of the slave processor module 11b counts the correction processing interval, and when the count value reaches the correction processing interval value, generates a correction processing start signal and starts preparation for the synchronous correction processing (S03). .

When the slave processor module 11b receives the first reference signal transmitted by the main processor module 11a after the count value of the interval counter 33 reaches the correction processing interval value (S04), the synchronization correction processing by software is started. Together with (S05), the overhead counting unit 34 is restarted (S06). Then, the count value acquisition unit 35 acquires both count values of the second reference signal generation unit 31 and the overhead count unit 34 (S07), and the synchronization determination unit 36 performs synchronization determination based on the both count values. (S08) If it is determined to be asynchronous, the synchronization correction unit 37 performs synchronization correction (S09).

Thus, it is possible to synchronize a predetermined signal with high accuracy while suppressing the processing load.

(Second embodiment: node synchronization system)
The second embodiment is characterized in that the synchronization correction processing is executed including the delay time by the transmission bus 12 in the first embodiment described above. FIG. 7 is a diagram illustrating an example of a schematic configuration of the node synchronization system according to the second embodiment. The node synchronization system 50 shown in FIG. 7 is an example that performs counter synchronization among a plurality of nodes such as the nodes 51a to 51c.

The node synchronization system 50 includes a plurality of nodes 51a to 51c (hereinafter referred to as “node 51” as necessary), a communication path (communication network) 52, and an I / O (input / output) module 53 (in FIG. 7, 53a to 53d), an external device 54 (indicated by 54a to 54d in FIG. 7), and a programming device 55. That is, in the node synchronization system 50, a master node 51a and

slave nodes

51b and 51c are connected via a communication path 52 as a communication network.

Here, for the sake of convenience, the node 51a is a master node and the

nodes

51b and 51c are slave nodes, and the configuration unique to each node will be described. However, the present invention is not limited to this. It has both configurations so that it can be. In the second embodiment, it is assumed that a transmission delay time by the communication path 52 is generated.

Here, the difference between the second embodiment (FIG. 7) and the first embodiment (FIG. 1) will be described. The master node 51a corresponds to the main processor module 11a in the first embodiment, and the

slave nodes

51b and 51c correspond to the

slave processor modules

11b and 11c in the first embodiment. The programming device 55 is substantially equal to the programming device 15 in the first embodiment, and the I / O modules 53a to 53d are substantially the same as the I / O modules 13a to 13d in the first embodiment. equal. The external devices 54a to 54d are substantially the same as the external devices 14a to 14d in the first embodiment. Therefore, in the following description, the description of the same configuration as in the first embodiment is omitted.

The master node 51a includes a first reference signal generator 61 (corresponding to the first reference signal generator 21 of the first embodiment) and a first calculator 62 (corresponding to the first calculator 22 of the first embodiment). A storage unit 63 (corresponding to the storage unit 23 of the first embodiment), an interval counting unit 64 (corresponding to the interval counting unit 33 of the first embodiment), a transmission delay time notification unit 65, and a synchronization frame And a notification unit 66.

The main difference between the master node 51a and the main processor module 11a in the first embodiment is that the interval counter 33 provided in the slave processor module 11b in the first embodiment is added as the interval counter 64. In addition, a transmission delay time notification unit 65 and a synchronization frame notification unit 66 are newly added. Therefore, in the following description, the main part of the second embodiment will be described, and the same movement as in the first embodiment will be omitted.

Hereinafter, an example in the second embodiment will be described. In the second embodiment, the interval counting unit 64 performs counting, and when a correction processing interval value corresponding to a correction processing interval for performing synchronization processing is preset, and the count value reaches the correction processing interval value, this is indicated. A correction processing start signal is generated. Since the correction processing interval value is substantially the same as that in the first embodiment, the description thereof is omitted here.

Here, the correction processing interval is measured on the master node 51a side, but the correction processing interval may be measured on the slave node 51b side. In that case, when the count value reaches the correction processing interval value in the slave node 51b, a correction processing start signal is transmitted to the master node 51a, and the synchronous correction processing is started.

After receiving the correction processing start signal, the transmission delay time notification unit 65 of the master node 51a transmits a transmission delay time request frame to the

slave nodes

51b and 51c in order to calculate the transmission delay time. This transmission delay time request frame has substantially the same format as a later-described synchronization frame and has a different data in a predetermined portion (for example, a command portion) in the synchronization frame. The transmission delay time request frame is transmitted in synchronization with the first reference signal generated by the first reference signal generation unit 61.

Subsequently, the transmission delay time notification unit 65 receives a reception completion frame from the slave node that responds to the transmission delay time request frame. Then, the transmission delay time notification unit 65 calculates the round trip transmission delay time between the master node 51a and the

slave nodes

51b and 51c from the difference between the time when the response frame is received and the time when the transmission delay time request frame is transmitted. To do. Then, the transmission delay time notification unit 65 transmits a transmission delay time notification frame including the calculated round trip transmission delay time to the

slave nodes

51b and 51c in synchronization with the next first reference signal, whereby the

slave nodes

51b and 51c. Is notified of the delay time caused by the communication path 52.

After notifying the round-trip transmission delay time, the master node 51a, based on the first reference signal (in synchronization with the first reference signal), sends the prepared synchronization frame to the

slave nodes

51b, 51c. This process is executed by the synchronization frame notification unit 66. As will be described in detail later, the synchronization frame is a synchronization reference signal for matching the count value of the second reference signal generation unit 71 of the

slave nodes

51b and 51c with the count value of the first reference signal generation unit 61 of the master node 51a. is there.

Next, the

slave nodes

51b and 51c will be described. The

slave nodes

51b and 51c include a second reference signal generator 71 (corresponding to the second reference signal generator 31 of the first embodiment) and a second calculator 72 (the second calculator 32 of the first embodiment). ), An overhead counting unit 74 (corresponding to the overhead counting unit 34 of the first embodiment), a count value acquiring unit 75 (corresponding to the count value acquiring unit 35 of the first embodiment), and a synchronization determining unit 76 (corresponding to the synchronization determination unit 36 of the first embodiment), a synchronization correction unit 77 (corresponding to the synchronization correction unit 37 of the first embodiment), and a storage unit 78 (storage unit 38 of the first embodiment). ), A reception completion notifying unit 79, and a frame receiving unit 80. The CPU 43 has a second reference signal generation unit 71 built therein. Since the

slave nodes

51b and 51c have the same configuration, the following description will be made using the slave node 51b, and the description of the slave node 51c will be omitted.

The main differences from the processor module 11b of the first embodiment are that the synchronization determination unit 76 is different from the synchronization determination unit 36 of the first embodiment, and that a reception completion notification unit 79 and a frame reception unit 80 are added. It is. However, since the other components are substantially the same as those in the first embodiment, the description thereof is omitted here. Hereinafter, the synchronization correction processing of the slave node 51b including the transmission delay time of the communication path 52 will be described.

The reception completion notification unit 79 receives the above-described transmission delay time request frame from the master node 51a, and transmits a reception completion frame to the master node 51a according to the transmission delay time request frame.

The frame receiving unit 80 receives the above-described transmission delay time notification frame transmitted by the master node 51a, and saves the round-trip transmission delay time (value) included in the frame in the above-described memory 45 or the like. In this way, the slave node 51b obtains the round trip transmission delay time between the master node 51a and the slave node 51b from the master node 51a.

The slave node 51b that has obtained the round-trip transmission delay time from the master node 51a receives the synchronization frame and causes the second computing unit 72 to generate an interrupt. Upon receiving the interrupt, the second calculation unit 72 starts a synchronization correction process described later. In this embodiment, even when a synchronization frame is received without obtaining a round trip transmission delay time, it goes without saying that the synchronization correction processing may be started with the round trip transmission delay time set to zero (0). Also, considering the speed at which the interrupt is raised to the second arithmetic unit 72 after receiving the synchronization frame, although not shown, it is preferable to use hardware logic such as FPGA 44 as the means for receiving the synchronization frame. .

Also, the overhead counting unit 74 measures an overhead value until the synchronization correction process is executed, starting from the reception of the synchronization frame described above. Specifically, the overhead counting unit 74 functions as a hardware counter (timer) that receives and restarts the synchronization frame.

The count value acquisition unit 75 acquires the count value of the second reference signal generation unit 71 and the count value of the overhead count unit 74 at the time when the synchronization correction process is actually executed in response to reception of the synchronization frame. .

The synchronization determination unit 76 calculates the one-way transmission delay time of the communication path 52 by dividing the above-described round-trip transmission delay time by 2, and further converts the one-way transmission delay time and the count value of the overhead counter 74 described above into a time. The total delay time is calculated by adding the calculated value. Then, the synchronization determination unit 76 compares the obtained total delay time with a value obtained by time-converting the count value of the second reference signal generation unit 71 acquired by the count value acquisition unit 75. As a result of the comparison, when both are equal, the synchronization determination unit 76 determines that the first reference signal and the second reference signal are synchronized. When both are different, the first reference signal and the second reference signal are determined. Are determined to be asynchronous. Here, the synchronization means that the count value of the first reference signal generation unit 61 is equal to the count value of the second reference signal generation unit 71.

It should be noted that the synchronization determination unit 76 can, of course, determine synchronization / asynchronization by converting the count values of the respective counters into time as in the synchronization determination unit 36 of the first embodiment.

In the second embodiment, when the synchronization determination unit 76 determines that the first reference signal and the second reference signal are synchronized at every correction processing interval, the synchronization correction unit 77 sets the reference value to the second reference signal. Set in the generation unit 71. If it is determined that the first reference signal and the second reference signal are asynchronous, a value that cancels the difference between the count value of the second reference signal generation unit 71 and the total delay time value is obtained. Specifically, the synchronization correction unit 77 obtains a synchronization correction value by subtracting the total delay time value from the count value of the second reference signal generation unit 71 acquired by the count value acquisition unit 75. Subsequently, the synchronization correction unit 77 subtracts the obtained synchronization correction value from the reference value, and sets the subtracted value as a new reference value in the second reference signal generation unit 71. The new reference value is a timer of the second reference signal generation unit 71 with respect to a reference value (default reference value) set in the second reference signal generation unit 71 when the synchronization determination unit 76 determines synchronization. Temporarily set to correct the value (temporary reference value).

In the present embodiment, it is needless to say that the default reference value does not need to be rewritten thereafter if the default reference value is set in the second reference signal generation unit 71 and synchronization is maintained.

As described above, this embodiment can perform the synchronization correction process considering the influence of the transmission delay time when the synchronization reference signal (synchronization frame) is notified via the communication path 52. That is, in the second embodiment, the count value including the transmission delay time between the nodes and the overhead of the

slave nodes

51b and 51c can be corrected, and synchronization between the nodes can be realized with high accuracy.

(Example of synchronization correction processing in the second embodiment)
FIGS. 8 to 10 are time charts for explaining an example of synchronization correction processing in the second embodiment, and are examples of synchronization of count values between the master node 51a and the slave node 51b. The reference value (processing cycle) in the second embodiment is set to 1000 μs as in the first embodiment, and this reference value can be appropriately changed by the programming device 55.

In FIG. 8, the first reference signal generator 61 of the master node 51a performs counting. When the count value reaches the reference value at time (1) in FIG. 8, a first reference signal is output. And the 1st calculating part 62 performs a predetermined | prescribed process according to the said 1st reference signal.

Further, the second reference signal generation unit 71 of the slave node 51b performs counting. When the count value reaches the reference value at time (2) in FIG. 8, a second reference signal is output. And the 2nd calculating part 72 performs a predetermined | prescribed process according to the said 2nd reference signal. As described above, the master node 51a and the slave node 51b perform predetermined processing according to the independent first reference signal and second reference signal, respectively.

In the master node 51a, the interval counting unit 64 performs counting, and when the count value reaches the correction processing interval value ((3) in FIG. 8), a correction processing start signal is generated. The synchronization correction process in the master node 51a is started in response to the correction process start signal.

When the synchronization correction processing starts, the transmission delay time notification unit 65 of the master node 51a transmits a transmission delay time request frame in order to calculate the transmission delay time ((4) in FIG. 8). When receiving the transmission delay time request frame from the master node 51a, the reception completion notifying unit 79 of the slave node 51b transmits the reception completion frame to the master node 51a according to the transmission delay time request frame ((5 in FIG. 8). )).

Subsequently, the transmission delay time notification unit 65 of the master node 51a calculates the round trip transmission delay time between the master node 51a and the slave node 51b according to the reception completion frame, and includes the calculated round trip transmission delay time (400 μs). A transmission delay time notification frame is transmitted ((6) in FIG. 8). When receiving the transmission delay time notification frame, the frame receiving unit 80 of the slave node 51b saves the round-trip transmission delay time (value) included in the frame in the memory 45 or the like ((7) in FIG. 8).

After the synchronization correction process is started, the synchronization frame notification unit 66 of the master node 51a transmits the synchronization frame as an interrupt signal to the slave node 51b ((8) in FIG. 8). Then, the slave node 51b receives the synchronization frame through the one-way transmission delay time (200 μs) of the communication path 52 at the time of (9) in FIG. 8, and activates the synchronization correction process by software in the slave node 51b. Yes. With the reception of the synchronization frame, the hardware counter of the overhead counter 74 is cleared and restarted ((10) in FIG. 8).

Subsequently, when the preparation for the synchronization correction process is completed, the count value acquisition unit 75 acquires the count value from the second reference signal generation unit 71 ((12) in FIG. 8) at the time (11) in FIG. The count value is acquired from the overhead counter 74 ((13) in FIG. 8).

Subsequently, the count value acquisition unit 75 refers to the count value of the second reference signal generation unit 71, converts it to time, and acquires 400 μs. Subsequently, the synchronization determination unit 76 calculates a one-way transmission delay time 200 μs from the round-trip transmission delay time (400 μs), and adds the calculated transmission delay time and the time-converted count value of the overhead counter 74 to 200 μs. The delay time is 400 μs. Then, the synchronization determination unit 76 compares the total delay time 400 μs with the 400 μs obtained by converting the count value of the second reference signal generation unit 71 acquired by the count value acquisition unit 75, and since both are equal, the first reference signal And the second reference signal are determined to be synchronized.

Since the synchronization determination unit 76 determines that the first reference signal and the second reference signal are synchronized, the synchronization correction unit 77 sets the reference value 1000 μs in the second reference signal generation unit 71 as usual. (The second reference signal generator 71 has not been restarted at the time of setting). The second reference signal generation unit 71 restarts because the count value reaches the reference value 1000 μs at the time point (14) in FIG.

FIG. 9 shows a case where the counter of the slave node 51b is delayed by 3 μs from the counter of the master node 51a.

In FIG. 9, after the count value of the interval counting unit 64 of the master node 51a reaches the correction processing interval value and the synchronization correction processing is started, the frame receiving unit 80 of the slave node 51b performs the round trip included in the transmission delay time notification frame. Since the processing until the transmission delay time (value) is saved in the memory 45 or the like is substantially the same as the processing in FIG. 8, the description thereof is omitted here.

9 (1) in FIG. 9 after the synchronization correction process is started, the synchronization frame notification unit 66 of the master node 51a transmits the synchronization frame as an interrupt signal to the slave node 51b. Then, the slave node 51b receives the synchronization frame through the one-way transmission delay time (200 μs) of the communication path 52 at the time of FIG. 9 (2), and starts the synchronization correction process by software in the slave node 51b. . In addition, with the reception of the synchronization frame, the counter of the overhead counter 74 is cleared and restarted ((3) in FIG. 9).

Subsequently, when the preparation for the synchronization correction processing is completed, the count value acquisition unit 75 acquires the count value from the second reference signal generation unit 71 ((5) in FIG. 9) at the time (4) in FIG. Then, the count value is acquired from the overhead counter 74 ((6) in FIG. 9).

Subsequently, the count value acquisition unit 75 refers to the count value of the second reference signal generation unit 71, converts it to time, and acquires 397 μs. Subsequently, the synchronization determination unit 76 calculates a one-way transmission delay time 200 μs from the round-trip transmission delay time (400 μs), and adds the calculated transmission delay time and the time-converted count value of the overhead counter 74 to 200 μs. The delay time is 400 μs. Then, the synchronization determination unit 76 compares the total delay time 400 μs and the count value of the second reference signal generation unit 71 acquired by the count value acquisition unit 75 with time of 397 μs. It is determined that the signal and the second reference signal are asynchronous.

Since the synchronization determination unit 76 determines that the first reference signal and the second reference signal are asynchronous, the synchronization correction unit 77 sets a temporary reference value in the second reference signal generation unit 71. Specifically, the synchronization correction unit 77 restarts the second reference signal generation unit 71 using the formula “reference value (processing period) − (total delay time−count value of the second reference signal generation unit 71)”. A value (reset value) is obtained, and the obtained count value is set in the second reference signal generator 71 as a temporary reference value. In this example, the temporary reference value is 1000 μs− (400 μs−397 μs) = 997 μs. Then, the second reference signal generation unit 71 restarts because the count value reaches the temporary reference value 997 μs at the point (7) in FIG. Incidentally, the total delay time—the value of the count value of the second reference signal generator 71 is the synchronization correction value.

FIG. 10 shows a case where the counter of the slave node 51b is advanced by 3 μs from the counter of the master node 51a.

In FIG. 10, after the count value of the interval counting unit 64 of the master node 51a reaches the correction processing interval value and the synchronization correction processing is started, the frame receiving unit 80 of the slave node 51b performs the round trip included in the transmission delay time notification frame. Since the processing until the transmission delay time (value) is saved in the memory 45 or the like is substantially the same as the processing of FIGS. 8 and 9, the description thereof is omitted here.

10 (1) in FIG. 10 after the start of the synchronization correction process, the synchronization frame notification unit 66 of the master node 51a transmits the synchronization frame as an interrupt signal to the slave node 51b. Then, the slave node 51b receives the synchronization frame through the one-way transmission delay time (200 μs) of the communication path 52 at the time of FIG. 10 (2), and starts the synchronization correction process by software in the slave node 51b. . In addition, with the reception of the synchronization frame, the counter of the overhead counter 74 is cleared and restarted ((3) in FIG. 10).

Subsequently, when the preparation for the synchronization correction process is completed, the count value acquisition unit 75 acquires the count value from the second reference signal generation unit 71 ((5) in FIG. 10) at the time (4) in FIG. Then, the count value is acquired from the overhead counter 74 ((6) in FIG. 10).

Subsequently, the count value acquisition unit 75 refers to the count value of the second reference signal generation unit 71, converts it into time, and acquires 403 μs. Subsequently, the synchronization determination unit 76 obtains a one-way transmission delay time of 200 μs from the round-trip transmission delay time (400 μs), and adds the obtained one-way transmission delay time to the time-converted count value of the overhead counting unit 74 of 200 μs. The total delay time is 400 μs. Then, the synchronization determination unit 76 compares the total delay time 400 μs with the 403 μs obtained by converting the count value of the second reference signal generation unit 71 acquired by the count value acquisition unit 75 into time, and the first reference because the two are different. It is determined that the signal and the second reference signal are asynchronous.

Since the synchronization determination unit 76 determines that the first reference signal and the second reference signal are asynchronous, the synchronization correction unit 77 sets a temporary reference value in the second reference signal generation unit 71. In this example, the temporary reference value is 1000 μs− (400 μs−403 μs) = 1003 μs. Then, the second reference signal generator 71 restarts because the count value reaches the temporary reference value 1003 μs at the point (7) in FIG.

In the case of the examples of FIGS. 9 and 10, since the master counter and the slave counter are synchronized in the third cycle, the synchronization correction unit 77 subsequently changes the original reference value 1000 μs to the first cycle. 2 is set in the reference signal generation unit 71 (the second reference signal generation unit 71 has not been restarted at the time of setting). Then, the second reference signal generation unit 71 restarts when the count value reaches the reference value 1000 μs. That is, in the second embodiment, the slave counter can be restarted at substantially the same timing as the restart of the master counter in the next fourth cycle with respect to the third cycle. The value and the value of the counter on the slave side can be adjusted to substantially the same value.

Note that the synchronization correction processing includes program processing of the count value acquisition unit 75, the synchronization determination unit 76, and the synchronization correction unit 77 as in the first embodiment.

Further, although the second reference signal generation unit 71 of the slave node 51b has been described on the assumption that it is built in the CPU 43, it is not limited to this. That is, the second reference signal generation unit 71 can be realized even if it is separate from the CPU 43. However, since the second reference signal generation unit 71 is built in the CPU 43, the second reference signal generation unit 71 cannot be hardware reset with a predetermined signal generated outside the CPU 43. In other words, the second reference signal generation unit 71 is a counter whose operation is controlled through a program. For this reason, in this embodiment, the reset process (restart process) of the second reference signal generation unit 71 needs to be executed by a program, and the overhead thereof leads to a synchronization error. Therefore, in this embodiment, a configuration for measuring overhead is required (the same applies to the first embodiment).

In the second embodiment, the synchronization correction process is an interrupt process that is activated by receiving a synchronization frame.

In the above description, for example, the slave node 51b obtains and holds the round trip transmission delay time from the master node 51a, and uses the held round trip transmission delay time in the synchronization correction processing. Apart from this, there is also a method in which the master node 51a includes the round trip transmission delay time in the synchronization frame and transmits it to the slave node 51b, and the slave node 51b that has received this uses the round trip transmission time included in the synchronization frame. . By doing in this way, since the master node 51a can notify the slave node 51b of the round trip transmission delay time according to the situation, the slave node 51b can utilize the round trip transmission delay time according to the situation in a timely manner. .

Further, although the transmission delay time notifying unit 65 has been described to notify the slave node 51b of the round trip transmission delay time, the present invention is not limited to this. For example, the transmission delay time notification unit 65 may calculate the one-way transmission delay time by halving the calculated round-trip transmission delay time, and notify the slave node 51b of the calculated one-way transmission delay time. In this case, the synchronization determination unit 76 of the slave node 51b may obtain the total delay time by using the given one-way transmission delay time as it is.

As described above, in the second embodiment, the first reference signal and the second reference signal can be synchronized including the transmission delay time of the signal through the communication path 52.

(Notification procedure of transmission delay time in synchronization correction processing)
Next, a transmission delay time notification procedure in the above-described synchronization correction process will be described. FIG. 11 is a diagram for explaining an example of a transmission delay time notification procedure according to the second embodiment. In the example of FIG. 11, the above-described master node 51 a and

slave nodes

51 b and 51 c are provided, and each node 51 is connected in a state where signals can be transmitted and received via the communication path 52. To do. Further, in the following description, an example in which the master node 51a acquires the signal transmission delay time through the communication path 52 between the nodes 51 is shown.

Also, the squares shown in FIG. 11 indicate frames, the squares on the line for each node 51 indicate transmission frames, and the squares below the lines indicate reception frames. Further, the frame shown in FIG. 11 includes a transmission delay time request frame 81 (“REQ *” in FIG. 11 (* indicates an identifier (eg, b, c) of each slave node, for example)), and reception is completed. A frame 82 (“REC *” in FIG. 11), a transmission delay time notification frame 83 (“SET *” in FIG. 11), and a response frame 84 (“ANS *” in FIG. 11) to the transmission delay time notification frame 83 Have

In the example of FIG. 11, the master node 51a broadcasts a transmission delay time request frame 81b (REQb) for the slave node 51b on the communication path 52 in accordance with the master node synchronization standard. At this time, the transmission delay time request frame 81b includes information (target node information) indicating a transmission delay time request for the slave node 51b.

The transmission delay time request frame 81b transmitted by broadcast is received by the

slave nodes

51b and 51c via the communication path 52 after a predetermined transmission delay time. In the example of FIG. 11, the slave node 51b receives the transmission delay time request frame 81b with the delay time D1 from the master node synchronization reference, and the slave node 51c receives the transmission delay time request with the delay time D2 from the master node synchronization reference. The frame 81b is received.

Here, each of the

slave nodes

51b and 51c confirms the above-mentioned target node information included in the transmission delay time request frame 81b. As described above, since the transmission delay time request frame 81b is a request for the slave node 51b, only the slave node 51b broadcasts the reception completion frame 82b (RECb) to the master node 51a. At this time, the reception completion frame 82b includes information (target node information) indicating that it is a reception completion frame for the master node 51a.

The transmitted reception completion frame 82b is received by the master node 51a and the slave node 51c via the communication path 52. Next, the master node 51a and the slave node 51c confirm the above-described target node information included in the reception completion frame 82b. As described above, the reception completion frame 82b is a frame for the master node 51a. Therefore, the master node 51a sets the transmission delay time for the slave node 51b based on the time information from the transmission of the transmission delay time request frame 81b transmitted according to the master node synchronization reference until the reception completion frame 82b is received. To do. Here, the set transmission delay time may be a round trip transmission delay time in which a predetermined signal reciprocates between the master node 51a and the slave node 51b via the communication path 52, or may be a one-way transmission delay time.

Also, the master node 51a creates a transmission delay time notification frame 83b (SETb) for notifying the slave node 51b of the set transmission delay time, and broadcasts the created transmission delay time notification frame 83b according to the master node synchronization standard. Send. The transmission delay time notification frame 83b includes the target node information described above.

The transmission delay time notification frame 83b transmitted by broadcast is received by each of the

slave nodes

51b and 51c after a predetermined transmission delay time via the communication path 52 in the same manner as the transmission delay time request frame 81b described above.

At this time, the slave node 51b determines that it is information for the own node from the target node information of the received transmission delay time notification frame 83b, and includes the transmission delay time included in the frame, the overhead time described above, and the like. The synchronization correction process in the second embodiment is performed. In addition, the slave node 51b creates a response frame 84b (ANSb) for the transmission delay time notification frame 83b, and broadcasts the created response frame 84b. At this time, the response frame 84b includes information indicating that the frame is for the master node 51a (target node information), information indicating that the synchronization correction processing has been completed, and the like.

The transmitted response frame 84b is received by the master node 51a and the slave node 51c via the communication path 52, similarly to the reception completion frame 82b described above. Next, the master node 51a and the slave node 51c confirm the above-described target node information included in the response frame 84b. As described above, the response frame 84b is a frame for the master node 51a. Therefore, the master node 51a can grasp that the synchronization correction processing is completed by the response frame 84b from the slave node 51b. The slave node 51c receives a transmission delay time request frame 81b (REQb), a reception completion frame 82b (RECb), a transmission delay time notification frame 83b (SETb), and a response frame 84b (ANSb). However, since none of them is a frame for the own node, the received frame is discarded.

The contents up to the above are the transmission delay time notification procedure to the slave node 51b. Therefore, the master node 51a similarly notifies the slave node 51c of the transmission delay time.

Specifically, in the example of FIG. 11, the master node 51a broadcasts a transmission delay time request frame 81c (REQc) to the slave node 51c on the communication path 52 according to the master node synchronization standard. The transmission delay time request frame 81c transmitted by broadcast is received by each of the

slave nodes

51b and 51c via the communication path 52 with a predetermined transmission delay time (D1, D2) as described above.

Since the transmission delay time request frame 81c is a request for the slave node 51c, only the slave node 51c broadcasts a reception completion frame 82c (RECc) to the master node 51a. The transmitted reception completion frame 82c is received by the master node 51a and the slave node 51c via the communication path 52. The reception completion frame 82c is a frame for the master node 51a. Therefore, the master node 51a sets the transmission delay time for the slave node 51c based on the time information from the transmission of the transmission delay time request frame 81c transmitted according to the master node synchronization reference until the reception completion frame 82c is received. To do. Here, the set transmission delay time may be a round trip transmission delay time in which a predetermined signal reciprocates between the master node 51a and the slave node 51c via the communication path 52, or may be a one-way transmission delay time.

Further, the master node 51a creates a transmission delay time notification frame 83c (SETc) for notifying the slave node 51c of the set transmission delay time, and broadcasts the created transmission delay time notification frame 83c according to the master node synchronization standard. Send. The transmission delay time notification frame 83c transmitted by broadcast is received by each of the

slave nodes

51b and 51c via the communication path 52 with a predetermined transmission delay time (D1, D2) in the same manner as the transmission delay time request frame 81c described above. The

At this time, as described above, the slave node 51c determines from the target node information of the received transmission delay time notification frame 83c that the information is for the own node, and the transmission delay time included in the frame and the overhead time described above. The synchronization correction process in the second embodiment including the above is performed. The slave node 51c creates a response frame 84c (ANSc) for the transmission delay time notification frame 83c, and broadcasts the created response frame 84c. At this time, the response frame 84c includes information indicating that the frame is for the master node 51a (target node information), information indicating that the synchronization correction processing has been completed, and the like.

The transmitted response frame 84c is received by the master node 51a and the slave node 51c via the communication path 52 in the same manner as the reception completion frame 82c described above. Next, the master node 51a and the slave node 51b confirm the above-described target node information included in the response frame 84c. As described above, the response frame 84c is a frame for the master node 51a. Therefore, the master node 51a can recognize that the synchronization correction processing has been completed based on the response frame 84c from the slave node 51c. The slave node 51b receives a transmission delay time request frame 81c (REQc), a reception completion frame 82c (RECc), a transmission delay time notification frame 83c (SETc), and a response frame 84c (ANSc). However, since none of them is a frame for the own node, the received frame is discarded.

In the second embodiment, the transmission delay time can be notified by sequentially performing the above-described processing on each of the

slave nodes

51b and 51c of the communication path 52.

Note that the transmission delay time notification procedure is not limited to the procedure described above. For example, in order to prevent the

slave nodes

51b and 51c that have received the transmission delay time request frame 81 from being broadcasted and to be congested on the communication path 52 or the master node 51a by transmitting the response frame 84, for example A send counter may be provided inside and the response frame 84 may be controlled to be transmitted at different timings using the send counter.

In the second embodiment described above, for example, in a system having a star topology such as Ethernet (registered trademark), the counter of each node is synchronized with the common memory network using the time division multiplex transmission method, and the entire apparatus is Synchronous control that matches the timing of control is possible. In the second embodiment, the counter to be synchronized can be configured using a counter inside the microcomputer or using a counter such as an FPGA. Therefore, in the second embodiment, for example, a counter that is synchronized with the master node 51a at the reception timing of a frame to be transmitted and received and a counter that measures the processing time in the microcomputer are configured by hardware such as FPGA, for example. Processing errors can be corrected by calculating the count value with a microcomputer.

Here, in the above-described example, the node synchronization between the master and the slave has been described as an example of the node synchronization system 50. However, in the present embodiment, the present invention is not limited to this. For example, sampling synchronization in a protection relay or the like It can also be applied to technology.

(Network transmission system: schematic configuration example)
Here, in the second embodiment described above, for example, each node is connected via a relay device such as a HUB (hub) such as IEEE802.3u (100BASE-TX) or IEEE802.3ab (1000BASE-T). May be. FIG. 12 is a diagram illustrating an example of a schematic configuration of a network transmission system including the node synchronization system 50 using the master node 51a and the

slave nodes

51b and 51c in the second embodiment. As an example, the network transmission system 90 shown in FIG. 12 includes a plurality of nodes 51 (nodes 51a to 51c in the example of FIG. 12) and a HUB 91 as one or a plurality of relay devices (in the example of FIG. 12, HUB 91a). 91e). Note that the number and type of nodes and relay devices, and the connection method are not limited thereto.

In the example of FIG. 12, the master node of FIG. 7, that is, the node 51a is the node A (master station), and the slave nodes of FIG. 7, that is, the node 51b and the node 51c are the node B and node C (slave station). As shown in FIG. 12, the communication path of the network transmission system 90 is, for example, a star type having a relay device between the master node 51a and the slave node 51b. The relay device uses HUB as an example. However, the present embodiment is not limited to this, and for example, a router, a repeater, an optical converter, or the like can be used.

The master node 51a and the

slave nodes

51b and 51c are, for example, programmable controllers (also referred to as a control device or PLC (Programmable Logic Controller)), and the communication path of the network transmission system 90 exchanges data between these programmable controllers. Data exchange bus. Examples of devices connected to the data exchange bus include a PC, a server, an I / O module, a drive device (for example, an inverter, a servo, and the like) in addition to the above-described programmable controller.

In the network transmission system 90 shown in FIG. 12, the node 51a and the node 51c are connected to the same HUB 91a, and the node 51b is connected to the node 51a and the node 51c via a 5-stage HUB (relay device). Yes.

Here, a general Ethernet HUB employs an interface method called store & forward. In this case, all the sent frames are stored in the reception buffer in the HUB, and are transmitted after performing the HUB internal processing (for example, abnormality determination, destination determination, etc.).

(Sequence example of node synchronization method)
FIG. 13 is a diagram illustrating a schematic sequence example of the node synchronization method. In the example of FIG. 13, for the sake of convenience of explanation, synchronization using the master node 51a and the slave node 51b will be described. However, in the present embodiment, the present invention is not limited to this. Slave nodes can be synchronized.

In the node synchronization process of FIG. 13, first, the first reference signal generation unit 61 of the master node 51a generates a first reference signal (S11), and the second reference signal generation unit 71 of the slave node 51b generates a second reference signal. A signal is generated (S12). Further, this process is cyclically operated in terms of hardware.

Further, the interval counting unit 64 of the master node 51a counts the correction processing interval, and when the count value reaches the correction processing interval value, generates a correction processing start signal and starts the synchronous correction processing (S13).

When the count value of the interval counting unit 64 reaches the correction processing interval value, synchronization correction processing in the master node 51a is started (S13), and the transmission delay time notifying unit 65 of the master node 51a calculates the transmission delay time. A transmission delay time request frame is transmitted (S14). Note that the transmission delay time request frame is a data obtained by changing a predetermined portion of data included in the synchronization frame, and can be referred to as a synchronization frame. Explains.

Upon receiving the transmission delay time request frame, the reception completion notification unit 79 of the slave node 51b generates a reception completion notification and notifies the master node 51a (S15).

Upon receiving the reception completion notification, the transmission delay time notification unit 65 of the master node 51a calculates, for example, a round trip transmission delay time (S16), and generates a transmission delay time notification frame including the calculated round trip transmission delay time (S17). The generated transmission delay time notification frame is transmitted to the slave node 51b via the communication path 52 (S18).

When receiving the transmission delay time notification frame, the frame receiving unit 80 of the slave node 51b saves the round-trip transmission delay time (value) included in the frame in the memory 45 or the like (S19). Then, the synchronization frame notification unit 66 of the master node 51a transmits the synchronization frame as an interrupt signal to the slave node 51b in synchronization with the first reference signal (S20). When the slave node 51b receives the synchronization frame (S21), the synchronization correction process by software is activated (S22) and the overhead counting unit 74 is restarted (S23). Then, the count value acquisition unit 75 acquires both count values of the second reference signal generation unit 71 and the overhead count unit 74 (S24), and the synchronization determination unit 76 performs synchronization determination based on the both count values. (S25) If it is determined to be asynchronous, an overall delay time is calculated (S26). The total delay time is, for example, a value obtained by adding a transmission delay time and an overhead value, but is not limited thereto. Further, the synchronization correction unit 77 of the slave node 51b performs synchronization correction using the calculated total delay time (S27). In the process illustrated in FIG. 13, the slave node 51b may transmit a response frame indicating that the synchronization correction has been completed to the master node 51a. The master node 51a also performs node synchronization processing in the above-described procedure for slave nodes other than the slave node 51b connected to the communication path 52.

Here, in the present embodiment, a program (node synchronization program) for causing a computer to function as each unit included in the above-described node 51 is generated, and the generated program is installed in the computer or the like, so that Node synchronization processing can be realized.

As described above, according to the present embodiment, it is possible to synchronize a predetermined signal with high accuracy while suppressing the processing load. Thereby, for example, stabilization of the data exchange cycle of each node 51 can be realized. Further, according to the present embodiment, in a system having a star topology such as Ethernet, for example, the timer of each node 51 is synchronized with the shared memory network using the time division multiplex transmission method, thereby improving the transmission efficiency. The efficiency of data exchange, the stabilization of the data exchange cycle, etc. can be realized.

In addition, this embodiment can be applied to a synchronization method when performing a series of operations in a large-scale facility such as a steel plant using a plurality of operations. It can be widely applied as a synchronization method.

The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to such embodiments. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Is done.

Note that each step of the signal synchronization method and the node synchronization method of the present specification does not necessarily have to be processed in time series in the order described in the sequence diagram, and may include processing in parallel or by a subroutine. .

The present invention can be used for a signal synchronization system, a node synchronization system, a signal synchronization method, and a node synchronization method for synchronizing predetermined signals.

DESCRIPTION OF SYMBOLS 10 Signal synchronization system 11 Processor module 12 Transmission bus 13,53 I / O (input / output) module 14,54 External apparatus 15,55 Programming apparatus 21,61 1st reference signal generation part 22,62

1st calculating part

23,38 , 63, 78 Storage unit 31, 71 Second reference signal generation unit 32, 72 Second calculation unit 34, 74 Overhead counting unit 35, 75 Count value acquisition unit 36, 76 Synchronization determination unit 37, 77 Synchronization correction unit 41 Input unit 42 Output unit 43 CPU
44 FPGA
45 Memory 46 External interface 50 Node synchronization system 51 Node 52 Communication path 65 Transmission delay time notification unit 66 Synchronization frame notification unit 79 Reception completion notification unit 80 Frame reception unit 81 Transmission delay time request frame 82 Reception completion frame 83 Transmission delay time notification Frame 84 Response frame 90 Network transmission system 91 HUB (relay device)

Claims

A signal synchronization system including a main module operating in accordance with a first reference signal and a slave module operating in accordance with a second reference signal, wherein the second reference signal is synchronized with the first reference signal,
The main module is
A first reference signal generation unit that performs counting and generates the first reference signal when the count value reaches a preset reference value;
The slave module is
A second reference signal generation unit that performs counting and generates the second reference signal when the count value reaches the reference value;
An interval counting unit that counts the interval at which the synchronization correction processing is performed;
After the count value reaches the correction processing interval value for performing the synchronization correction processing in the interval counting unit, an overhead counting unit that receives and restarts the first reference signal and performs counting,
After the count value reaches the correction processing interval value in the interval count unit, the count value of the second reference signal generation unit and the count value of the overhead counter unit are acquired in response to reception of the first reference signal. A numerical value acquisition unit;
A synchronization correction unit that temporarily sets a value that cancels the difference between the count value of the second reference signal generation unit and the count value of the overhead count unit as a reference value in the second reference signal generation unit;
A signal synchronization system comprising:
The slave module includes a processor that executes an operation in the slave module;
The signal synchronization system according to claim 1, wherein the second reference signal generation unit is a counter that can be accessed only by the processor.
3. The signal synchronization system according to claim 2, wherein a processor included in the slave module functions as the count value acquisition unit and the synchronization correction unit.
The slave module is
It is determined that the first reference signal and the second reference signal are asynchronous when the count value of the second reference signal generation unit acquired by the count value acquisition unit is different from the count value of the overhead counter A synchronization determination unit that
The synchronization correction unit temporarily sets a value that cancels the difference as a reference value in the second reference signal generation unit only when it is determined to be asynchronous to the synchronization determination unit. The signal synchronization system according to any one of claims 1 to 3.
The synchronization determination unit time-converts the count value of the second reference signal generation unit and the count value of the overhead counter acquired by the count value acquisition unit, and determines that they are asynchronous when both times are different The signal synchronization system according to claim 4, wherein:
The first reference signal generation unit periodically generates the first reference signal,
The signal synchronization system according to claim 1, wherein the second reference signal generation unit periodically generates the second reference signal.
The signal synchronization system according to any one of claims 1 to 6, wherein the reference value can be set from an externally connected setting device.
A node synchronization system including a master node that operates according to a first reference signal and a slave node that operates according to a second reference signal, wherein the second reference signal is synchronized with the first reference signal,
The master node is
A first reference signal generation unit that performs counting and generates the first reference signal when the count value reaches a preset reference value;
An interval counting unit that counts the interval at which the synchronization correction processing is performed;
After the count value reaches the correction processing interval value for performing the synchronization correction processing in the interval counting unit, the transmission delay time in the communication path connecting the master node and the slave node is calculated and notified to the slave node. A transmission delay time notification unit;
A synchronization frame notification unit that transmits a synchronization frame synchronized with the first reference signal to the slave node via the communication path;
With
The slave node is
A second reference signal generation unit that performs counting and generates the second reference signal when the count value reaches the reference value;
An overhead counting unit that receives and restarts the synchronization frame and performs counting;
A count value acquisition unit that acquires a count value of the second reference signal generation unit and a count value of the overhead counter in response to reception of the synchronization frame;
A value that cancels the difference between the count value of the second reference signal generation unit and the total delay time value that is the sum of the count value of the overhead counter and the value indicating the transmission delay time is set to the second reference signal. A synchronization correction unit temporarily set as a reference value in the generation unit;
A node synchronization system comprising:
The transmission delay time notification unit transmits a transmission delay time request frame to the slave node, receives a reception completion frame from the slave node with respect to the transmission delay time request frame, and receives the reception time and the transmission delay time. The node synchronization system according to claim 8, wherein the transmission delay time is calculated from a difference from a time when a request frame is transmitted.
The node synchronization system according to claim 8 or 9, wherein the communication path is a star type having a relay device between the master node and the slave node.
The slave node includes a processor that executes operations in the slave node;
The node synchronization system according to any one of claims 8 to 10, wherein the second reference signal generation unit is a counter that can be accessed only by the processor.
The node synchronization system according to claim 11, wherein a processor included in the slave node functions as the count value acquisition unit and the synchronization correction unit.
The slave node is
Synchronous determination for determining that the first reference signal and the second reference signal are asynchronous when the count value of the second reference signal generation unit acquired by the count value acquisition unit is different from the total delay time Further comprising
The synchronization correction unit temporarily sets a value that cancels the difference as a reference value in the second reference signal generation unit only when it is determined to be asynchronous to the synchronization determination unit. The node synchronization system according to any one of claims 8 to 12.
The synchronization determination unit time-converts the count value of the second reference signal generation unit and the count value of the overhead counter acquired by the count value acquisition unit, and determines that they are asynchronous when both times are different The node synchronization system according to claim 13.
The first reference signal generation unit periodically generates the first reference signal,
The node synchronization system according to claim 8, wherein the second reference signal generation unit periodically generates the second reference signal.
16. The node synchronization system according to claim 8, wherein the reference value can be set from an externally connected setting device.
A signal synchronization method for synchronizing the second reference signal to the first reference signal by a main module operating according to the first reference signal and a slave module operating according to the second reference signal,
The main module is
Counting is performed, and the first reference signal is generated when the count value reaches a preset reference value.
The slave module is
Counting, and generating the second reference signal when the count value reaches the reference value;
Count the interval to perform synchronization correction processing,
After the count value reaches the correction processing interval value for performing the synchronous correction processing, the first reference signal is received and restarted, and counting is performed.
After a count value indicating an interval for performing the synchronization correction processing reaches the correction processing interval value, a count value for generating the second reference signal and a count value restarted by receiving the first reference signal Acquired,
A value that cancels the difference between the count value for generating the second reference signal and the count value that has been received and restarted is temporarily used for the count for generating the second reference signal. The signal synchronization method is characterized in that it is set as a reference value.
A node synchronization method for synchronizing the second reference signal to the first reference signal by a master node that operates according to the first reference signal and a slave node that operates according to the second reference signal,
The master node is
Counting is performed, and the first reference signal is generated when the count value reaches a preset reference value,
Count the interval to perform synchronization correction processing,
After the count value of the interval for performing the synchronization correction processing reaches the correction processing interval value, the transmission delay time in the communication path connecting the master node and the slave node is calculated and notified to the slave node,
Transmitting a synchronization frame synchronized with the first reference signal to the slave node via the communication path;
The slave node is
Counting, and generating the second reference signal when the count value reaches the reference value;
Receiving the synchronization frame, restarting, counting,
Obtaining a count value for generating the second reference signal in response to reception of the synchronization frame and a count value restarted by receiving the synchronization frame;
The difference between the count value for generating the second reference signal and the total delay time value that is the sum of the count value that is received and restarted after receiving the synchronization frame and the value indicating the transmission delay time is canceled out A node synchronization method, wherein a value is temporarily set as a reference value in a count for generating the second reference signal.