JP2011023788A - Network synchronization method and synchronization circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a network synchronization method and a synchronization circuit which achieve high responsiveness by a simple configuration. <P>SOLUTION: A path jitter is calculated from a master count value of a synchronizing packet and a slave counter value at this timing. A plurality of path jitters including the latest one are stored. A minimum path jitter out of the plurality of stored path jitters is extracted. A predictive path jitter is formed from differences between respective path jitters and the minimum path jitter. The predictive path jitter is added to the slave counter value to calculate a corrected slave counter value. A plurality of corrected slave counter values including the latest one are stored. Master counter value of a plurality of synchronizing packets including the latest one are stored. A frequency shift is calculated from a ratio of the difference between two stored corrected slave counter values and the difference between two master counter values corresponding to the corrected slave counter values, to perform network synchronization. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a network synchronization method and a synchronization circuit, for example, a technique effective for use in a network synchronization method and a synchronization circuit for generating a clock corresponding to a synchronization packet periodically received through a network.

  Patent Document 1 discloses a time management method between communication devices that manages time in each communication terminal connected to a communication network. In Patent Document 1, in order to reduce the time error generated in both the request station and the response station due to delay in the communication network, the elapsed time from the request transmission of the time notification to the response reception in the time data transmitted from the response station The time data to be newly managed by the own station is added. In addition, a time calculation function is derived from the relationship between a plurality of corrected time data obtained in the past and the time data at the local station when these time data are received, and the time calculation function is automatically included in the time calculation function. Time data that is predicted to be correct is obtained by inputting the current time data at the station.

Japanese Patent Laid-Open No. 04-281439

  FIG. 6 shows a schematic block diagram of a synchronization system examined prior to the present invention. In the figure, the assumed Ethernet (registered trademark) or Ethernet (registered trademark) synchronization system conditions are as follows. The devices connected to the network are one master device and one or more slave devices. Each of the master device and the slave device has a clock oscillator, and operates with a clock output from each clock oscillator. A device that becomes a clock master of the system is a master device. The master device has a master counter that operates with an input clock. The slave device has a slave counter and a synchronous counter that operate with an input clock. The slave device has a synchronization mechanism for following the clock of the master device. The synchronization mechanism measures the difference between the master counter and the slave counter, corrects the synchronization counter, causes the master counter to follow the synchronization counter, and synchronizes between the master counter and the synchronization counter.

  The oscillators have individual differences for each device, and the frequencies do not match. For example, the frequency deviation is about 0 to 100 ppm. The network connects devices with a packet relay. The packet relay relays synchronous packets (hereinafter referred to as SYNC packets) and normal packets. The SYNC packet is periodically issued from the master device and sent to the slave device. For example, the SYNC packet transmission interval is 10 μs to 60 s. The slave device measures the phase difference and frequency deviation from the master device from the SYNC packet. The time stamp of the master device (the count value of the master counter) is included in the SYNC packet. The state in which synchronization is achieved by the system synchronization refers to a state in which the difference between the count values of the master counter of the master device and the synchronization counter of the slave device is within a previously assumed range. That is, it means a state in which the synchronous counter follows the master counter and the difference between the count values is small.

  In order for the slave device to synchronize with the master clock, necessary information 1 to 3 is collected through the SYNC packet for the relationship between the master counter and the slave counter. Information 1 is a frequency deviation between the master clock and the slave clock, information 2 is a phase difference (count value difference) between the master counter and the slave counter, and information 3 is a path delay of the SYNC packet. The present invention relates to a method for obtaining a frequency deviation which is mainly the information 1 among the information 1 to 3 described above.

  The procedure for the slave device to know the frequency of the master clock is as follows. As procedure 1, a SYNC packet is periodically transmitted from the master device, and the slave device receives it. As a procedure 2, the slave device compares the time stamp of the master device included in the SYNC packet with the synchronization counter of its own device. As a procedure 3, as a result of comparison, if the time stamp of the master device is advanced, the slave device advances the synchronization counter of the slave device, and if it is delayed, the slave device corrects to delay the synchronization counter of the slave device.

  Regarding the counter correction in the above procedures 1 to 3, a point that should be considered when performing network synchronization is to avoid abrupt counter correction. If abrupt correction is performed, it leads to a malfunction of the peripheral circuit operating according to the counter value, so that gradual counter correction is required. In order to perform a gradual correction, it is necessary to periodically perform a small correction. If the frequency correction between the master counter and the slave counter is known, the periodic correction can be periodically performed in accordance with the deviation.

  FIG. 7 shows an explanatory diagram of the relationship between the master counter and the slave counter when the path delay is constant. The relationship between the master counter and the slave counter necessary for understanding the network synchronization is verified. In the case where the path delay is constant (no SYNC packet fluctuation) as shown in the figure, the first SYNC packet (s0) is transmitted from the master device. The master count value of s0 is set to “0”, and the slave device sets the slave counter value only when receiving the packet (head packet) of s0. The relationship between the counters of the master device and the slave device when the SYNC packet (s0 to s5) is transmitted is as shown in FIG. In the figure, the transit time of the SYNC packet relay route is constant.

From FIG. 7, the relationship between the master counter of the master device and the slave counter of the slave device can be expressed as (Equation 1). In (Equation 1), a is the ratio of the master device input frequency to the slave device input frequency, and b is the path delay from the master device to the slave device.
Y = aX + b (Formula 1)

Based on the value a, the frequency deviation between the master clock and the slave clock is expressed by (Equation 2) with reference to the input clock of the slave device. From (Equation 2), if the frequency of the master device is equal to that of the slave device, a is 1 and the deviation is 0.
Frequency deviation = a-1 (Formula 2)

  In practice, fluctuations are included in the SYNC packet. In the above network system, fluctuation occurs in the SYNC packet relay time. The cause of the fluctuation is that when the general packet and the SYNC packet compete with each other in the packet relay as shown in FIG. 8, the SYNC packet is made to wait until the processing of the general packet is completed in the packet relay. In addition, since a circuit in the relay path of the SYNC packet includes a synchronization circuit, it may be delayed depending on the synchronization timing. Of the above two causes, the main cause is contention between general packets and SYNC packets. In this specification, the fluctuation of the relay time of the SYNC packet is defined as path jitter.

FIG. 9 is an explanatory diagram of a basic method for obtaining a frequency deviation (basic deviation detection method). In order to obtain the frequency deviation between the master counter and the slave counter, the inclination is calculated from the two SYNC packet information. The SYNC packet information is a time stamp included in the Sync packet and a slave count value when the SYNC packet is received. In FIG. 9, the x and y coordinates of the SYNC packets S2 and S5 are S2: (x2, y2) and S5: (x5, y5), respectively. The distance (w) between the two points in the X direction and the distance (h) in the Y direction can be obtained by (Expression 3) and (Expression 4).
w = x5-x2 (Formula 3)
h = y5-y2 (Formula 4)

From this result, the slope and deviation can be calculated by (Equation 5) and (Equation 6).
Inclination = a = h / w (Formula 5)
Deviation = a-1 = (h / w)-1 (Formula 6)

  Since the master clock and slave clock each have a change in ambient temperature or aging, and the frequency changes, deviation calculation must be performed periodically. The basic deviation detection method does not consider fluctuation due to path jitter. Therefore, when the path jitter is included as follows, there is a difference between the frequency deviation between the master clock and the slave clock and the value obtained by calculation. As a result, there is a problem that the synchronization accuracy is lowered.

  FIG. 10 shows an explanatory diagram of the relationship between the master counter and the slave counter when path jitter occurs in the SYNC packet. In the figure, s1 to s5 indicated by ◯ are plots of the time stamp when the SYNC packet arrives when there is no path jitter and the counter of the slave counter, and d1 to d5 indicated by ● have path jitter. The time stamp when the SYNC packet arrives and the counter of the slave counter are plotted. When path jitter occurs, the slave device receives the SYNC packet at a delayed timing, the slave counter value increases, and the plot position of the SYNC packet moves to the right.

  FIG. 11 is a diagram for explaining the problem in the basic deviation detection method when there is path jitter. As above, s1 to s5 indicated by ◯ are plots of the time stamp when the SYNC packet arrives when there is no path jitter and the counter of the slave counter, and d1 to d5 indicated by ● have path jitter. The time stamp when the SYNC packet arrives and the counter of the slave counter are plotted. When the master device transmits SYNC packets S2 and S5 and path jitter occurs until the slave device arrives, the SYNC packets of s2 and s5 are received by d2 and d5. The slope between the two points from d2 and d5 is a ', and a = a'.

  FIG. 12 is a diagram illustrating the principle of the point-to-point extension method that also considers including path jitter. This point-to-point distance extension method is a method of sufficiently separating two SYNC packets in order to reduce the influence of path jitter. In the example in the figure, the distance between two points for calculating the deviation is calculated by d2 and dn that are sufficiently larger than the path jitter (time), and the slope a ″ is obtained. The obtained slope a ″ is a≈a ″ since w and h are sufficiently large with respect to the path jitter as shown in FIG.

  FIG. 13 shows a statistical processing method (least square method) in consideration of including path jitter. That is, the statistical processing method (least square method) also used in Patent Document 1 is used. In other words, this is a method of obtaining a slope from SYNC packet information including path jitter using a statistical method. The method is to find a straight line y ′ ″ = a ′ ″ x + b ′ ″ that minimizes the distance from each point SYNC packet. If there are many points to be statistically processed, y = ax + b and y '' '= a' '' x + b '' 'approach parallel and can be handled as a = a' ''. The calculation for obtaining y '' '= a' '' x + b '' 'can use the least square method.

  However, since the point-to-point distance extension method described with reference to FIG. 12 requires a distance (time) between two points of the SYNC packet in a network environment where the path jitter is large, from the start of SYNC packet transmission until synchronization is established. The problem is that the time of the process becomes longer. The statistical processing method described in FIG. 13 requires an average value and a difference between each point. That is, the amount of calculation for calculating the deviation is larger than that of the basic deviation detection method or the two-point distance extension method. Because of the large amount of calculation, first, it takes time to output the deviation. Secondly, there is a problem that the circuit scale (LSI) of the synchronization mechanism mounted on the slave device is increased, and the power consumption is increased accordingly.

  An object of the present invention is to provide a network synchronization method and a synchronization circuit that realize high response with a simple configuration. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  One embodiment disclosed in the present application is as follows. The path jitter corresponding to the difference between the time stamp of the received SYNC packet and the slave counter value at the reception timing is calculated. A plurality of path jitters including the latest one are stored in the first history section. The minimum path jitter is extracted from a plurality of path jitters. A predicted path jitter corresponding to the difference between the path jitter and the minimum path jitter is calculated. A corrected slave counter value is formed by adding the predicted path jitter to the slave counter value. A plurality of corrected slave counter values including the latest one are stored in the second history section. Corresponding to the slave counter value, the master count value of a plurality of synchronization packets including the most recent one is stored in the third history section. The network synchronization is calculated by calculating the frequency deviation from the ratio between the difference between the two corrected slave count values extracted from the second history section and the corresponding difference between the two master counter values extracted from the third history section. Do.

  Another embodiment disclosed in the present application is as follows. The synchronization circuit can be mounted on a slave device having a protocol processing unit that receives a synchronization packet transmitted from a master device via a network and a slave counter, and has a path jitter calculation unit and a frequency deviation calculation unit. The first calculation unit of the path jitter calculation unit calculates path jitter corresponding to the difference between the master counter value of the synchronization packet received via the network and the slave counter value at the reception timing of the synchronization packet. The first history unit of the path jitter calculation unit stores a plurality of path jitters including the latest one. The minimum value calculation unit of the path jitter calculation unit extracts the minimum path jitter from the plurality of path jitters stored in the first history unit. The second calculation unit of the path jitter calculation unit forms a predicted path jitter corresponding to the difference between the path jitter and the minimum path jitter. The third calculation unit of the frequency deviation calculation unit calculates a corrected slave counter value obtained by adding the predicted path jitter to the slave counter value. The second history unit of the frequency deviation calculation unit stores a plurality of corrected slave counter values including the latest one. The third history unit of the frequency deviation calculation unit stores master count values of a plurality of synchronization packets including the latest one. The fourth calculation unit calculates the frequency deviation from the ratio between the difference between the two corrected slave counters and the corresponding difference between the master count values extracted from the third history unit.

  Compared with the two-point distance extension method, since it is not necessary to make a distance (time) between two points used in deviation calculation, the frequency deviation can be calculated at an early stage, so that the time from the start of SYNC packet transmission to the establishment of synchronization can be shortened. Since the least square method, which is a statistical method, is not used, the number of calculations is reduced, and the deviation output can be output in a short time. Since the calculation method is simple, the gate scale of the synchronization circuit can be reduced and power consumption can be suppressed.

1 is a system configuration diagram of a network to which the present invention is applied. 1 is a block diagram of an embodiment of a synchronization circuit according to the present invention. FIG. It is explanatory drawing of the relationship between the master counter which concerns on this invention, and a slave counter. It is explanatory drawing of the relationship between the master counter which concerns on this invention, and a slave counter. It is explanatory drawing of the relationship between the master counter and slave counter for demonstrating this invention. It is a schematic block diagram of the synchronous system examined prior to this invention. It is explanatory drawing of the relationship between a master counter and a slave counter in case path | route delay is constant. It is the schematic showing generation | occurrence | production of the path | route delay by packet competition. It is explanatory drawing of how to obtain basic frequency deviation (basic deviation detection method) It is explanatory drawing of the relationship between a master counter when a path jitter occurs in a SYNC packet. It is problem explanatory drawing in the basic deviation detection method in case there exists path jitter. It is a principle explanatory view of the point-to-point extension method that also considers including path jitter. It is explanatory drawing of the statistical processing method (least-squares method) which considered also including path | route jitter.

  A preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 shows a network system configuration diagram to which the present invention is applied. The figure includes a master device M0 that is a master of time, slave devices S1 to S31 that synchronize time with the master device, and switching hubs H0 and H1. Master device M0 and slave devices S1 to S15 are connected via switching hub H0. Master device M0 and slave devices S16 to S31 are connected via switching hubs H0 and H1. The clock (master clock) for operating the master counter that generates the time of the master device M0 is, for example, 200 MHz, which is the master time of the present network system. The clock (slave clock) for operating the slave counter that generates the local time of the slave devices S1 to S31 is about 200 MHz, for example, and has an error of about 100 ppm at maximum with respect to the master clock.

  The master apparatus M0 has a master counter including a clock generator and a synchronization packet generator. The synchronization packet generation unit generates a synchronization packet including a master counter value <mc> i serving as a time stamp. For example, a time stamp generated every 10 ms is broadcasted to the slave devices S1 to S31 as a synchronization packet. Each of the slave devices S1 to S31 includes a slave counter including a similar clock generator, a protocol processing unit that receives a synchronization packet, and a synchronization circuit, as shown in S31 as a representative. The slave devices S1 to S31 use the reception of the synchronization packet as a trigger, and compare the time stamp included in the synchronization packet with the slave counter value <sc> i that is its own time stamp generated by the slave counter. The synchronization circuit calculates a frequency deviation between the master clock and the slave clock necessary for time synchronization between the master device and the slave device.

  The protocol processing unit receives the SYNC packet from the master device M0 and generates a master counter value <mc> i indicating the time included in the synchronization packet. The synchronization circuit compares the master counter value <mc> i with the slave counter value <sc> i to calculate a frequency deviation. In the switching hubs H0 and H1, a communication delay time occurs due to the relay of the synchronization packet and the normal packet. The relay delay time of the synchronization packet in the switching hubs H0 and H1 varies greatly within a range of, for example, a fixed delay of 20 us and a variable delay of about 123.04 us. For this reason, the synchronization circuit according to the present application performs a highly accurate synchronization operation with high-speed response.

  FIG. 2 is a block diagram showing an embodiment of the synchronization circuit according to the present invention. In the figure, the frequency deviation is calculated using the information of the SYNC packet acquired by the slave device from the master device via the network. The synchronization circuit shown in the figure includes a protocol processing unit, a path jitter calculation unit, and a frequency deviation calculation unit.

  The protocol processing unit receives the SYNC packet and generates a data value 1 that is a master counter value. The slave counter generates a data value 2 that is a slave counter value by a slave clock formed by its own transmitter. The data value 1 is supplied as a master counter value <mc> i to the calculation unit AU1 in the path jitter calculation unit. The data value 2 is supplied as a slave counter value <sc> i to the calculation unit AU1 in the path jitter calculation unit and the calculation unit AU3 in the frequency deviation calculation unit.

  The arithmetic unit AU1 generates a counter difference <dc> i of the supplied master count value <mc> i and the slave counter value <sc> i at that time, and the counter difference history unit TBL1 and the arithmetic unit AU2 To supply. The minimum value calculation unit MIN extracts min <dc> which is the smallest from the counter differences stored in the counter difference history unit TBL1, and supplies the extracted min <dc> to the calculation unit AU2. The calculation unit AU2 generates a predicted path jitter <pdj> i based on the count difference <dc> i supplied from the calculation unit AU1 and the minimum value supplied from the minimum value calculation unit MIN, and the frequency This is supplied to the calculation unit AU3 in the deviation calculation unit.

  The arithmetic unit AU3 removes the path jitter component by subtraction and generates a corrected slave counter value <sc ′> i. The corrected slave counter value <sc ′> i is stored in the slave counter value history unit TBL2. The master counter value <mc> i corresponding to the corrected slave counter value <sc ′> i is stored in the master counter value history unit TBL3. The arithmetic unit AU4 calculates a data value 3 which is a frequency deviation by the slave counter value history unit TBL2 and the master counter value history unit TBL3.

The operation of the synchronization circuit can be described as follows. The arithmetic unit AU1 obtains the difference <dc> i between the master counter value <mc> i of the i-th received SYNC packet and the slave counter value <sc> i at the reception timing of the i-th SYNC packet ( The operation (1) calculated by equation (7) is performed.
<dc> i = <sc>i-<dc> i (Equation 7)

  In the counter difference history part TBL1, an operation (2) for holding the counter difference <dc> of the number N of entries set by the register REG1 is performed. The number N of entries in the counter difference history part TBL1 may be a fixed value in addition to the software setting using the register REG1 as in this embodiment. The counter difference history part TBL1 stores N counter differences <dc> including the latest one. That is, when N or more counter differences <dc> are input to the counter difference history part TBL1, the latest one is stored, and the oldest one is discarded instead.

  The minimum value calculation unit MIN estimates and extracts the minimum value min <dc> of the N counter differences <dc> stored in the counter difference history unit TBL1 as the value having the smallest path jitter. Operation (3) is performed.

The arithmetic unit AU2 performs an operation (4) for obtaining a predicted path jitter <pdj> i of communication of the i-th SYNC packet after the minimum value min <dc> is extracted by (Equation 8). Here, the SYNC packet transmission interval or the number N of entries in the counter difference history part TBL1 is determined so that the holding period in the counter difference history part TBL1 becomes a level at which the frequency difference component included in the value in the history can be sufficiently ignored. Is done.
<pdj> i = <dc> i-min <dc> (Equation 8)

The arithmetic unit AU3 removes the path jitter component from the slave counter value <sc> i according to (Equation 9) in order to generate the slave counter value <sc ′> i after the path jitter component is removed (5). Is done.
<sc '> i = <sc>i-<pdj> i (Equation 9)

  In the slave counter value history unit TBL2, the slave counter value <sc ′> i after the slave counter value removal calculated in (Equation 9) is stored for the number M of entries set by the register REG2. (6) is performed. Also in the history part TBL2, M pieces including the latest one are sequentially updated in the same manner as the operation of the counter difference history part TBL1.

  In the master counter value history section TBL3, an operation (7) is performed in which the master counter value <mc> i corresponding to the slave counter value <sc '> i is stored for the number M of entries. As a result, the master / slave counter value history sections TBL3 and TBL2 hold the M most recent master counter values <mc> i and the slave counter values <sc ′> i after removal of the path jitter component, respectively. In order to calculate the frequency deviation with high accuracy, the holding period in the master / slave counter value history sections TBL3 and TBL2 is long so that the error between the predicted path jitter <pdj> i and the true path jitter can be sufficiently ignored. Need to be done. For example, it is necessary to increase the number of entries M to the master / slave counter value history parts TBL3 and TBL2, or to increase the SYNC packet interval.

In the arithmetic unit AU4, the operation (8) for obtaining the frequency deviation <fa> j which is the data value 3 by (Equation 10) is performed. <Mc> k, <sc ′> k in (Expression 10) are values held in the master counter value and slave counter value history sections TBL3 and TBL2. The slave counter value <sc '> i after removal of the path jitter component includes a fixed delay component of prediction, but the denominator [<sc'>(M-1)-<sc'> 0] is offset by the difference between the predicted values and is not affected. Here, <mc> (M-1) is the value stored in the (M-1) th of the master counter history part TBL3, and <mc> 0 is stored in the 0th of the master counter history part TBL3. Value. The same applies to <sc '> (M-1) and <sc'> 0.
<fa> j = [<mc>(M-1)-<mc> 0] / [<sc '>(M-1)-<sc'> 0]-1 (Equation 10)

  It is possible to calculate the frequency deviation with high accuracy by the above operations (1) to (8). The above mathematical formulas indicating the method of calculating the frequency deviation are used for the description thereof, and may be developed and simplified in consideration of mounting. The point-to-point distance extension method and the statistical processing method are countermeasures against path jitter. However, as in this embodiment, the above-described two point-to-point distance extension methods and Even without using a statistical processing method, a simple basic deviation detection method enables highly accurate deviation detection. In order for the slave device to synchronize with the master clock, the time of the slave device is obtained from (Equation 1) using the calculated frequency deviation <fa> j.

  FIG. 3 is an explanatory diagram showing the relationship between the master counter and the slave counter according to the present invention. When path jitter occurs, the master counter value (Y axis) does not change and only the slave counter (X axis) increases (one-side delay). Further, the relationship between the master counter and the slave counter is (Equation 1), and the slope at this time is characterized by a≈1. These characteristics can be treated as the coefficient a = 1 in (Equation 1), assuming that the influence of the frequency deviation is small if the master counter and the slave counter are short. The path jitter calculates the difference between the master counter value and the slave counter value (count difference). If the difference is small, the path jitter is small, and if the difference is large, the path jitter is large. From the above consideration, the path jitter can be calculated by the synchronization circuit, and the path jitter can be removed.

In the figure, for example, a method for correcting and correcting the path jitter (pd4) of s4 using the latest d2 and d3 will be described. Here, the path jitter of d3 is 0, that is, s3 = d4. First, in order to select a point serving as a correction base point (hereinafter referred to as a base point) from d2 and d3, a difference between the time stamp and the slave count is calculated, and d3 having a small difference is selected. Since the slope a in (Equation 1) is 1 between d3 and the SYNC packet d4 including path jitter, the equation for obtaining the path jitter (pd4) of s4 is (Equation 11).
pd4 = d4 counter difference-s3 counter difference
= (D4 slave counter-d4 time stamp)
-(D3 slave counter-d3 time stamp)
= (x4-y4)-(x3-y3) ... (Formula 11)

  When the path jitter is obtained, the point s′4 obtained by removing (correcting) the path jitter from d4 is (x4-pd4, y4). If the corrected points are connected, it becomes almost a straight line, and an equation for obtaining a frequency deviation from two basic points can be used.

  FIG. 4 is an explanatory diagram showing the relationship between the master counter and the slave counter according to the present invention. In the description of FIG. 3, the base point is selected from two points, but the actual operation is selected from a plurality of SYNC packets. This is because the main factor of the path jitter of the SYNC packet is contention with the general packet, and by receiving a plurality of times, the probability of receiving a packet that is less affected by the general packet is increased.

  In the embodiment described above, compared with the point-to-point distance extension method as described in FIG. 12, it is not necessary to open the distance (time) between the two points used in the deviation calculation. Since it can be calculated, the time from the start of SYNC packet transmission to the establishment of synchronization can be shortened. Further, since the least square method which is a statistical method as described with reference to FIG. 13 is not used, the number of calculations is reduced, and a deviation output can be output in a short time. Since the calculation method is simple, the LSI gate scale can be reduced and the power consumption can be suppressed.

  FIG. 5 is an explanatory diagram showing the relationship between the master counter and the slave counter for explaining the present invention. This figure shows the relationship between the distance between two points required for frequency deviation and the distance necessary for the present invention in the above-described two-point distance expansion method. Let s1 be the starting point for obtaining the deviation obtained by the two-point distance expansion method, and let d1 be the point including the path jitter. Let sn be the end point for obtaining the deviation obtained by the distance expansion method between two points. sn is a path jitter = 0. The starting point of the deviation obtained in the present invention is s1, but since the path jitter is corrected, d1 'close to s1 is set. Let sn ′ be the end point of the deviation obtained in the present invention. sn ′ is assumed to have path jitter = 0. From this condition, the frequency deviation between the master counter and the slave counter is obtained from the slope (hereinafter referred to as slope A) of the straight line L2 connecting s1 and sn with no transmission jitter. In order to obtain the frequency deviation by the two-point distance expansion method, it is obtained from the slope of the straight line L1 connecting d1 and sn (hereinafter referred to as slope B). The accuracy of the frequency deviation obtained by the two-point distance expansion method is the difference between the slope A and the slope B.

  Based on the above conditions, the starting point and the ending point necessary for obtaining a deviation with the same accuracy as the above-described two-point distance expansion method in the present invention will be considered. The start point is d1 ′, and the end point sn ′ is a position closer to the s1 direction from sn. sn ′ can be brought close to s1 until the inclination B of the straight line L3 connecting d1 ′ and sn ′ is the same. If the slopes are the same, triangle 1 connecting s1, d1, sn (sides are s1d1, d1sn, sns1) and triangle 2 connecting s1, d1 ', sn' (sides are s1d1 ', d1'sn', sn's1) is similar. From the above, if the path jitter can be corrected from the side s1d1 and reduced to the side s1d1 ′ in the present invention, it can be shortened from the side s1sn to the side s1sn ′ at the same ratio. That is, a frequency deviation with the same accuracy can be obtained even if sn ′ is brought close to s1. That is, a frequency deviation with the same accuracy as that of the two-point distance extension method can be obtained in a shorter time.

  Comparing the amount of calculation required for the present invention with the amount of calculation required for the least-squares method is as follows. The calculations required in the present invention are (Expression 3), (Expression 4), (Expression 5), (Expression 6), (Expression 11), and base point selection. On the other hand, the expression obtained by the least square method has a large amount of calculation like (Expression 4) of Patent Document 1. Both methods calculate each time a SYNC packet is received. In comparing the calculation amounts, the frequency deviation with the same accuracy can be obtained by the two methods depending on various conditions such as the SYNC packet transmission interval, the frequency deviation, and the network configuration which are the synchronization system conditions. Therefore, two calculations are compared with the same input data amount. In the input data, n = m, where the number of the latest SYNC packets used for base point selection performed in the present invention is n, and the number of SYNC points for which a deviation is obtained by the least square method is m. All the calculations required in the present invention are simple calculations. On the other hand, the amount of calculation of (Formula 4) of Patent Document 1 used in the least square method is obviously large because the average value is calculated and there is a difference calculation from the average value. .

  As an effect seen from the whole product and the reason that the effect can be obtained, since the frequency deviation is obtained with high response with a simple configuration as described above, synchronization between the master device and the slave device can be established in a short time, For example, since the number of calculations in the slave device is small, it is possible to realize a compact LSI with reduced power consumption.

  For example, in the slave device S31 of FIG. 1, the number N of entries in the counter difference history part TBL1 that holds the difference between the master counter value <mc> i and the slave counter value <sc> i shown in FIG. The number M of the master / slave counter value history parts TBL3, 2 is set to 400. That is, the frequency difference calculation is performed by the difference between the count-up amounts of the master and slave counters in 4 seconds. For evaluation purposes, the slave clock frequency adds an error of 100 ppm to the master clock.

  In the slave device S31, the frequency difference calculated by the two-point expansion method and the frequency difference <fa> using the frequency difference calculation unit shown in FIG. 1 can be calculated as follows. In contrast to the expected value of 100 ppm, the two-point expansion method has a calculation error of ± 60 ppm of 40 to 160 ppm, whereas in the embodiment, the calculation error of 95 to 105 ppm is ± 5 ppm. In the case of the two-point distance extension method, since communication delay jitter 246.08 us is included for 4 seconds which is the time between two points, the frequency difference calculation error caused by this communication delay jitter is 246.08 us / 4s = 61.52. ppm. On the other hand, in the embodiment, an accuracy improvement of about 12.3 times (61.52 / 5) can be expected as compared with the two-point distance extension method. In other words, even if the time between two points for frequency difference calculation is shortened to 0.33 seconds, which is a factor of 12.3, the present invention can be used to expect the same accuracy as the two-point distance extension method as described above. It becomes.

Although the invention made by the present inventors has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. The master counter value <mc> i and the slave counter value <sc> i may be values obtained by correcting communication delay components in advance by a protocol or the like before correction according to the present invention. Path jitter <pdj> i is calculated on the assumption that the frequency deviation is sufficiently negligible (a = 1) .To improve the accuracy, correction is performed using the obtained frequency deviation <fa>. May be. For example, (Expression 12) may be obtained by adding the frequency correction amount K to (Expression 8). K is K = <fa> * T, and T is the interval from the starting point (minimum value) from which the frequency deviation <fa> is obtained to the i-th.
<pdj> i = <dc> i-min <dc>-K (Equation 12)

  When the slave device has a microcomputer function, the operations of the calculation units and the minimum value calculation unit of the synchronization circuit may be realized by software using a calculation unit included in the microcomputer. In this case, the history section and the register are replaced with a memory circuit.

  The present invention can be widely used in a network synchronization method and a synchronization circuit in various systems such as an FA system and a real-time image / sound transfer apparatus that require synchronization via a network.

  M0 ... Master device, H0, H1 ... Switching hub, S1-S31 ... Slave device, AU1-AU4 ... Calculation unit, TBL1 ... Counter difference history unit, TBL2 ... Slave counter history unit, TBL3 ... Master counter history unit, REG1, REG2 ... Register, MIN ... Minimum value calculator.

Claims (5)

A first procedure for calculating a path jitter corresponding to a difference between a master counter value of a synchronization packet received via a network and a slave counter value at the reception timing of the synchronization packet;
A second procedure for storing a plurality of path jitters including the most recent one in the first history unit formed in the first calculation unit;
A third procedure for extracting a minimum path jitter from a plurality of path jitters stored in the first history section;
A fourth procedure for calculating a predicted path jitter corresponding to a difference between the path jitter formed by the first calculation unit and the minimum path jitter;
A fifth procedure for calculating a corrected slave counter value corresponding to the difference between the slave counter value and the predicted path jitter;
A sixth procedure for storing a plurality of corrected slave counter values including the latest one in the second history section;
A seventh procedure for storing a master count value of a plurality of synchronization packets including the most recent one corresponding to the slave counter value in a third history section;
An eighth procedure for calculating a frequency deviation from a ratio between a difference between the two corrected slave count values extracted from the second history part and a difference between two corresponding master counter values extracted from the third history part; ,
A ninth procedure for correcting the slave counter value using the calculated frequency deviation,
Network synchronization method. In claim 1,
In the master counter value and the slave counter value, a communication delay component is corrected in accordance with a network communication protocol applied in advance.
Network synchronization method. In claim 1 or 2,
The predicted path jitter is corrected using the calculated frequency deviation.
Network synchronization method. It can be connected to the master device via a network, and can be mounted on a slave device having a protocol processing unit that receives a synchronization packet transmitted from the master device and a slave counter.
A path jitter calculator,
A frequency deviation calculator,
The path jitter calculation unit
A first calculation unit;
A first history part;
A minimum value calculator,
A second arithmetic unit,
The first calculation unit calculates a path jitter corresponding to a difference between a master counter value of a synchronization packet received via a network and a slave counter value at a reception timing of the synchronization packet;
The first history unit is formed by the first calculation unit, stores a plurality of path jitters including the latest one,
The minimum value calculation unit extracts a minimum path jitter from a plurality of path jitters stored in the first history unit,
The second calculation unit calculates a predicted path jitter corresponding to a difference between the path jitter formed by the first calculation unit and the minimum path jitter,
The frequency deviation calculator is
A third computing unit;
A second history section;
A third history section;
A fourth arithmetic unit,
The third calculation unit calculates a corrected slave counter value that is a difference between the slave counter value and the predicted path jitter,
The second history unit stores a plurality of corrected slave counter values including the latest one,
The third history unit corresponds to the slave counter value, stores a master count value of a plurality of synchronization packets including the latest one,
The fourth calculation unit calculates a frequency deviation from a ratio between a difference between the two corrected slave counters extracted from the second history unit and a difference between the corresponding master count values extracted from the third history unit,
The slave counter value is corrected using the calculated frequency deviation.
Synchronization circuit. In claim 4,
The first history unit stores N path jitters that can be changed by the first register,
The second history unit and the third history unit store M corrected slave counter values and master counter values that can be changed by the second register, respectively.
Synchronization circuit.

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