JP2004179807A - Clock reproducing apparatus, data communication device, and clock reproducing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stably reproduce a clock even under a state where network fluctuation is large. <P>SOLUTION: Since the timewise change rate of the counter difference (STCn-PCRn) between a count value PCRn of reception clock information (PCR) 8 received by a count means 2 in the n-th and a count value STCn of reproduction clock information (STC) 7, where the count means 2 counts a reproduction clock from a clock reproduction means 1 at that time, shows deviation in a frequency, a clock control means 3 adjusts the frequency of a clock reproduction means 1 so that the counter difference does not change timewise, thus performing clock reproduction synchronizing with the reception clock information (PCR) 8. The reception timing of the PCR deviates from original timing under the state, where the network fluctuation is large, thus preventing accurate clock reproduction. Therefore, only PCR having small fluctuation in transmission is selected by a control means for performing clock control by the clock, thus stably reproducing the clock. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a clock reproducing apparatus for reproducing a clock of a transmission source on a receiving side using clock information transmitted from a transmission source in a device for performing communication or broadcasting, and a data communication for reproducing received data based on the reproduced clock. The present invention relates to an apparatus and a clock recovery method.
[0002]
[Prior art]
For example, in the conventional clock reproducing apparatus disclosed in Japanese Patent Application Laid-Open No. 2001-28537, the influence of the network fluctuation is obtained by calculating the total sum of the difference between the received clock information (PCR) 8 and the counter that counts the reproduced clock. Smoothing. In other words, this is the same as calculating the sum of the difference between the received clock information with the average network delay and the counter, and the difference can be calculated in a state where the network fluctuation can be ignored. By taking the sum of the difference from the counter for a predetermined period based on all the received clock information, frequency control is performed without being greatly affected by network fluctuation.
[0003]
[Patent Document 1]
JP 2001-28537 A
[0004]
[Problems to be solved by the invention]
However, the conventional clock recovery device has a problem that clock recovery cannot be performed properly for large network fluctuations.
[0005]
For example, in the case of the Internet or the like, the network fluctuation may reach several tens of ms, and in such a situation, the deviation of the counter when a 27 MHz clock is used reaches 270000 or more. The fluctuation assumed in the conventional clock recovery device is about several tens of a counter difference. In this case, each difference can be recognized as a difference of about one digit by taking the sum, but even if the sum of the differences is taken in a situation where there is a large network fluctuation as described above, the difference cannot be corrected to an allowable range. As a result, the frequency of the clock to be reproduced fluctuates, and stable clock reproduction cannot be performed.
[0006]
The present invention has been made in order to solve the above-described problems, and provides a clock recovery device, a data communication device, and a clock recovery method capable of performing stable clock recovery even in a situation where network fluctuation is large. The purpose is to:
[0007]
[Means for Solving the Problems]
In order to achieve the above object, a clock recovery device and a clock recovery method of the present invention count a recovered clock and select only valid clock information from clock information received from a transmission side, and select the selected received clock information. And controlling the frequency of the reproduced clock based on the count value.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
FIG. 1 is a configuration diagram showing a clock reproducing apparatus according to Embodiment 1 of the present invention. In the drawing, reference numeral 1 denotes clock reproducing means capable of controlling the frequency of a clock, 2 denotes a counting means for counting the clock of the clock reproducing means 1, and 3 denotes reproduced clock information counted by the counting means 2 (in the MPEG-2 system standard). Clock control means for controlling the frequency of the clock recovery means 1 based on the STC) 7 and the received clock information (PCR in the case of the MPEG-2 system standard) 8 transmitted and received by the transmission device (not shown). is there.
[0009]
Next, the operation will be described.
When receiving clock information (PCR) 8 is transmitted from the transmitting device (not shown), first, the counting unit 2 loads the receiving clock information (PCR) 8 received first as an initial value of the counter. The clock control means 3 records two counter values, that is, the counter value of the received clock information (PCR) 8 and the counter value of the reproduced clock information (STC) 7 from the counting means 2. At this time, the clock control means 3 does not control the frequency of the clock reproduction means 1. Therefore, the clock reproducing means 1 outputs a clock at a default frequency. The reception clock information (PCR) 8 is obtained by periodically incrementing the counter value of the clock in the transmission device (not shown) by "1000" at an arbitrary interval from the transmission device (not shown). , "1040", "1100",..., Which are affected by the transmission delay before transmission to the receiving apparatus.
[0010]
Then, the counting means 2 counts the counter by incrementing the counter by one from the initial value in synchronization with the frequency of the reproduction clock output from the clock reproduction means 1 and counts the counter as reproduction clock information (STC) 7. Output to
[0011]
Thereafter, the count value of the received clock information (PCR) 8 received by the count means 2 and the clock control means 3 at the nth time is PCRn, and the count value of the count means 2 at this time is the counter value obtained by counting the reproduction clock from the clock reproduction means 1. It is assumed that certain reproduction clock information (STC) 7 is STCn and time is Tn.
[0012]
By the way, if the frequency of the clock of the transmitting device (not shown) for transmitting the received clock information (PCR) 8 is different from the frequency of the clock of the clock reproducing means 1 of the receiving device, the counter increment of the unit time is different. Therefore, the absolute value of the counter difference (STCn-PCRn) increases with time.
[0013]
Since the time rate of change of the counter difference (STCn-PCRn) indicates a frequency shift, the clock control means 3 adjusts the frequency of the clock recovery means 1 so that the difference does not change with time. In addition, clock reproduction synchronized with the reception clock information (PCR) 8 can be performed.
[0014]
As described above, as a system standard for transmitting clock information indicating the state of the clock on the transmission side and generating a clock synchronized with the clock on the transmission side based on the clock information in the receiving device receiving the clock information, ISO / ISO There is IEC13818-1. This is called the MPEG-2 system standard and has been incorporated in various image communication systems.
[0015]
FIG. 2 is an explanatory diagram illustrating a mechanism of clock synchronization conforming to the MPEG-2 system standard. The transmitting device A is provided with a PCR (Program Clock Reference) generating means A1, while the receiving device B is provided with a clock reproducing device B1, and this clock reproducing device B1 is shown in FIG. 1 is a clock recovery device of the present invention shown in FIG.
In the MPEG-2 system standard, clock information sent from the transmission side is called a PCR (Program Clock Reference), and clock information reproduced on the reception side is called an STC (System Time Clock), and the PCR is used on the transmission side. The counter value of the counter operated by the clock and STC are the counter values of the counting means 2 operated by the clock reproduced on the receiving side. The receiving device uses the PCR sent from the transmitting device to adjust the frequency of the STC in the clock recovery device of the present invention to the clock of the transmitting device.
[0016]
In the MPEG-2 system standard, a system for performing fixed packet multiplexing is referred to as MPEG-2 TS, and a system for performing variable length packet multiplexing is referred to as MPEG-2 PS, and clock information to be transmitted is referred to as PCR and SCR (System Clock Reference), respectively. In.
[0017]
In a situation where the transmission delay of the network is not constant, the arrival time of the received clock information (PCR) 8 fluctuates, so that the corresponding counter value of the counting means 2 fluctuates from a desired value. As a result, the counter difference (STCn-PCRn) also fluctuates, and normal clock reproduction cannot be performed.
[0018]
Therefore, in the clock reproducing apparatus B1 of the first embodiment, the clock control means 3 uses only the reception clock information (PCR) 8 having the same transmission delay time as the effective reception clock information (PCR) 8 among the reception clock information (PCR) 8. By performing the clock reproduction control, normal clock reproduction can be performed.
[0019]
As described above, in the clock recovery device B1 of the first embodiment, the clock control unit 3 controls the clock recovery by using only the reception clock information having the same delay time from the reception clock information (PCR) 8. , Stable clock reproduction not affected by network fluctuation can be performed.
[0020]
By the way, even if the average of the transmission delay is taken, the average value of the transmission delay is not constant depending on the situation. Although the transmission delay increases as much as possible depending on the situation, the transmission delay does not decrease more than a certain level due to the configuration of the network. Therefore, accurate clock reproduction can be performed by using only the received clock information (PCR) 8 having a small delay time and transmitted with a stable delay time.
[0021]
FIG. 3 is an explanatory diagram illustrating the relationship between the transmission time and the reception time of the reception clock information (PCR) 8.
The vertical axis shows the counter value of the clock information, and the horizontal axis shows the time. A straight line C on the left side and points on the straight line C indicate that the counter value of the clock having a constant frequency on the transmitting side increases linearly and the counter value is discretely transmitted.
The counter value of the reception clock information (PCR) 8, which is a point on the straight line C on the transmission side, does not change due to the transmission delay, but changes only at the time and reaches the reception side.
[0022]
On the receiving side, the slope of the straight line C on the transmitting side, that is, the frequency of the received clock information (PCR) 8 is not known, so that some points are collected and the same clock is reproduced at the same frequency as the transmitting side. It is necessary to reproduce the straight line of the slope.
[0023]
In FIG. 3, a straight line as indicated by a broken line D to be reproduced on the receiving side is drawn by using, for example, two pieces of clock information D2 and D6 having a small transmission delay time. In this way, by selecting two pieces of clock information from the one with the smallest transmission delay time, it is possible to select clock information that is not affected by the transmission delay as much as possible. As a result, the slope of the straight line D becomes as close as possible to the slope of the straight line C on the transmission side. Therefore, by using two pieces of clock information having a small delay time, it is possible to almost predict the slope of the straight line C on the transmission side, and the reproduction clock information (STC) on the reception side is transmitted from the transmission side and received. This means that the clock frequency of the received clock information (PCR) 8 substantially matches. Here, the description has been made in such a manner that the slope of the transmission-side straight line C is predicted using, for example, two pieces of clock information having a small transmission delay time, but it is needless to say that two or more pieces may be used.
[0024]
As described above, in the clock reproduction device B1 of the first embodiment, the clock control unit 3 uses, for example, two pieces of the reception clock information (PCR) 8 among the reception clock information (PCR) 8 that are as short as possible. Then, the frequency of the clock of the reception clock information (PCR) 8 on the transmission side is predicted, and the clock reproduction is controlled so as to be at this frequency, whereby stable clock reproduction not affected by network fluctuation can be performed.
[0025]
Note that the clock frequency shift and the like when the clock control means 3 performs the clock reproduction control on the clock reproduction means 1 are determined in advance.
[0026]
Next, a specific method for selecting the received clock information (PCR) 8 having a small delay time when the clock control means 3 performs the clock reproduction control on the clock reproduction means 1 will be described below.
[0027]
<Receive clock information with small delay time (PCR) Method 1 for selecting 8>
FIG. 4 is an explanatory diagram showing an example of a method for selecting the reception clock information (PCR) 8 having a small delay time.
If the transmission timing of the clock information on the transmission side is known, it is easy for the reception side to select the clock information with a small transmission delay, but the reception side does not know the clock information on the transmission side. FIG. 4 shows an example of a method for selecting clock information with a small transmission delay on the receiving side when the clock information on the transmitting side is unknown.
[0028]
Specifically, in the case shown in FIG. 4, the clock regeneration device B1 of the first embodiment generates an approximate straight line E using a large number of received clock information (PCR) 8. The approximate straight line E is, for example, a straight line that minimizes the sum of squares of the distance between each point and the approximate straight line E. The approximate straight line E is compared with the position of each point in the horizontal direction (time axis direction). A point on the left side of the approximate straight line E, that is, a point having a large time difference from the approximate straight line E, is determined by a clock having a small transmission delay time. If two points having a large time difference from such an approximate straight line E are selected, two pieces of received clock information (PCR) 8 having a small delay time are determined, and the influence of the transmission delay is reduced as much as possible. Clock information that has not been received can be selected, and an approximate straight line E having a slope as close as possible to the slope of the straight line C on the transmission side can be obtained as in the case shown in FIG.
[0029]
As described above, in the clock regenerating apparatus B1 of the first embodiment, as shown in FIG. 4, an approximate straight line E is created from a large number of received clock information (PCR) 8, and the approximate straight line E and each received clock are generated. By comparing the time with the information (PCR) 8, it is possible to select the reception clock information (PCR) 8 whose delay time is as small as possible. As a result, as in the case shown in FIG. 3, the clock frequency of the reception clock information (PCR) 8 on the transmission side is predicted using, for example, two reception clock information (PCR) 8 having a small delay time. By performing the clock reproduction control so as to satisfy the above condition, stable clock reproduction not affected by network fluctuation can be performed.
[0030]
<Receive clock information with small delay time (PCR) Method 2 for selecting 8>
FIG. 5 is an explanatory diagram showing another example of a method for selecting the reception clock information (PCR) 8 having a small delay time. The clock information is the same as that in FIGS. 3 and 4, and additionally includes a trajectory F of the counter value of the counting means 2.
Specifically, since the frequency of the count value counted by the counting means 2 is almost the same as the frequency of the clock on the transmission side, the counter value of the counting means 2 is compared with the counter value of the reception clock information (PCR) 8. By doing so, clock information with a small delay time can be selected. That is, the smaller the value obtained by subtracting the counter value of the received clock information (PCR) 8 from the counter value of the counting means 2 when the received clock information (PCR) 8 is received, the smaller the value of the received clock information (PCR) having a shorter delay time. ) 8. In FIG. 5, as the point is higher than the straight line of the trajectory F of the counting means, its value becomes smaller, which means that the clock information has a shorter delay time.
[0031]
As described above, in the clock reproduction device B1 of the first embodiment, as shown in FIG. 5, the reception clock information (PCR) 8 is received from the counter value of the counting means 2 when the reception clock information (PCR) 8 is received. ) By selecting a value that is smaller than the value obtained by subtracting the counter value of 8, it is possible to easily select the reception clock information (PCR) 8 having a small delay time. As a result, as in the case shown in FIG. 3, the clock frequency of the reception clock information (PCR) 8 on the transmission side is predicted using, for example, two reception clock information (PCR) 8 having a small delay time. By performing the clock reproduction control so as to achieve the above, stable clock reproduction not affected by the network fluctuation can be performed.
[0032]
<Frequency control of reproduction clock at predetermined time intervals>
In the above description, the number of samples of the reception clock information (PCR) 8 used when selecting the reception clock information (PCR) 8 having a small delay time, the timing of clock control, and the like are not described. In selecting the reception clock information (PCR) 8 having a small delay time as described above, for example, of the reception clock information (PCR) 8 received at predetermined time intervals, as shown in FIG. For example, as shown in FIG. 5, only one piece of the reception clock information (PCR) 8 having a small difference from the counter value of the counting means 2 is selected, and the reception clock information (PCR) 8 and the reception clock information (PCR) The approximate straight line D shown in FIG. 3 is selected based on the reception clock information (PCR) 8 which is similarly selected from another predetermined period. It may be. By doing so, stable control can be performed because clock control can be performed at regular intervals, and processing load can be reduced because control intervals can be provided.
[0033]
As described above, in the clock reproducing device B1 of the first embodiment, only one of the received clock information (PCR) 8 received at a predetermined time is selected, and the received clock information (PCR) 8 and other information are selected. By performing clock control using only one piece of received clock information (PCR) 8 selected in the same manner from the predetermined period of time, stable clock reproduction control with a small processing load can be performed.
[0034]
<Receive clock information (PCR) 8 is the frequency control of the reproduction clock for each predetermined number>
As in the case of every predetermined time, after receiving the reception clock information (PCR) 8 every predetermined number, only one reception clock information (PCR) 8 having a small delay time or a small difference from the counting means 2 is received. By selecting the received clock information (PCR) 8 and, for example, only one received clock information (PCR) 8 similarly selected from another predetermined number of received clock information (PCR) 8 before and after the received clock information (PCR), for example, The clock control may be performed by selecting the approximate straight line D shown in FIG. By doing so, the reception clock information (PCR) 8 having a smaller delay time can be selected while a predetermined number of samples are always secured, so that the reception clock information (PCR) 8 having a smaller delay time can be found without fail. More accurate clock reproduction with less errors is possible.
[0035]
As described above, in the clock reproducing apparatus B1 of the first embodiment, only one of the received clock information (PCR) 8 is selected for each predetermined number, and the received clock information (PCR) 8 and other By performing clock control using a predetermined number of pieces of reception clock information (PCR) 8 in the same manner from one piece of reception clock information (PCR) 8, reception clock information (PCR) 8 having a small delay time is increased. Clock recovery control that can be found with a probability and that is stable and has a small processing load can be performed.
[0036]
<Initially loaded receive clock information (PCR) Example of Frequency Control of Reproduced Clock when 8 is Not Short in Delay Time>
The transition of the counter value of the counting means 2 to be reproduced by this method is an approximate straight line D on the right side in FIG. 3 connected by the received clock information having a small delay time.
However, the count value of the received clock information (PCR) 8 initially loaded into the counting means 2 is not necessarily short in delay time. In order to put the count value of the counting means 2 on the straight line D on the right side in FIG. 3 from this initial state, control that causes a large frequency change is required, and the clock becomes unstable as a clock recovery function. Therefore, it is not preferable.
[0037]
Therefore, when keeping the distance between the straight line D on the right side of FIG. 3 and the initially loaded reception clock information (PCR) 8 constant, that is, when performing clock control on the clock recovery means 1, the initially loaded reception clock information By performing the clock control by adding the difference between (PCR) 8 and the clock, the slope of the frequency controlled by the clock for the clock reproducing means 1 is parallel to the straight line D on the right side in FIG. A straight line passing through the reception clock information (PCR) 8 may be used as a locus of the counter value of the counting means 2. As a result, control can be performed so as to match the clock frequency on the transmission side from the time of initial loading, and stable clock reproduction can be performed.
[0038]
As described above, the clock recovery device B1 according to the first embodiment holds the counter difference between the approximate line D on the right side shown in FIG. 3 and the received clock information (PCR) 8 initially loaded. The clock regeneration control is performed so that the trajectory obtained by adding the count difference to the right approximate straight line D shown in FIG. The fluctuation of the clock frequency due to the difference between the received signal and the approximate straight line D on the right side of FIG.
[0039]
<Area (Zone) Management for Counter Difference (STCn-PCRn)>
The temporal change rate of the counter difference (STCn-PCRn) between the reproduction clock information (STC) 7 and the reception clock information (PCR) 8 indicates the deviation of the frequency of the reproduction clock in the clock reproduction means 1. When the counter difference (STCn-PCRn) includes an error due to network fluctuation, if the clock control is performed based on this difference, the frequency of the reproduced clock fluctuates.
[0040]
For this reason, the counter difference (STCn-PCRn) may always include an error, and the reproduction clock control may be performed only when the counter difference is large enough to be regarded as an error.
In other words, the management of the counter difference (STCn-PCRn) is performed in the area (zone), and the clock control is maintained as it is as long as the counter difference (STCn-PCRn) is changed within a certain zone. At this time, the frequency of the clock is controlled.
[0041]
By doing so, the reproduced clock is not disturbed by the error included in the counter difference, and the clock control is performed when the frequency difference can be clearly recognized, so that stable and accurate clock reproduction control can be performed.
[0042]
As described above, the management based on the counter difference (STCn-PCRn) is performed in the zone, and the reproduction clock is controlled only when the counter difference exceeds the zone, so that the counter difference (STCn-PCRn) fluctuates in the network. Even if an error is included, if the counter difference (STCn-PCRn) is within the zone, clock control is not performed based on the counter difference (STCn-PCRn), and the frequency of the reproduced clock fluctuates due to network fluctuation. , And stable and accurate clock reproduction can be performed.
[0043]
<Frequency control of reproduced clock when counter difference (STCn-PCRn) shifts in the direction of magnitude>
When selecting a sample having a small delay time from several samples of the reception clock information (PCR) 8 for each predetermined period or every predetermined number, there is a case where a sample having a transmission delay time that is not so small is actually included. It is possible. Then, the transmission delay time is recognized as being small, if not small, and the deviation of the counter difference (STCn-PCRn) between the reproduction clock information (STC) 7 and the reception clock information (PCR) 8 is determined by the reproduction clock information (STCn-PCRn). The frequency difference between the STC) 7 and the received clock information (PCR) 8 is erroneously recognized.
[0044]
Therefore, this is a situation where a sample of a delay time or a count difference smaller than the delay time or the count difference detected in the previous period or the predetermined number range cannot be found in the next period or the predetermined number range, for example, the counter difference ( In the case where (STCn-PCRn) shifts in the direction of increasing, the number of samples is further increased and the delay time and the count difference are smaller, that is, for example, a sample with a smaller counter difference (STCn-PCRn) is searched. Assuming that the frequency is really shifted, for example, clock control is performed using the received clock information (PCR) 8 having a small sample of delay time or count difference during that period or within a predetermined range.
[0045]
On the other hand, when the counter difference (STCn-PCRn) shifts in a direction to decrease, it means that a sample with a smaller delay time is found. However, the minimum value of the delay time has a limit, and a sample with an extremely small delay time is limited. Does not exist. Therefore, when the counter difference shifts in the direction of decreasing, it is a time when the frequency is really shifted, so that the reception clock information (PCR) 8 having a small delay time or a sample of the count difference in the period or within a predetermined number is immediately transmitted. To perform clock control.
[0046]
As described above, based on the direction in which the counter difference (STCn-PCRn) shifts, the number of samples of the reception clock information (PCR) 8 is increased by increasing the sample extraction period or the number of samples, or the sample extraction period or the number of samples is increased. The clock control is performed by using the received clock information (PCR) 8 having a small delay time and a small count difference within the sample extraction period or the range of the number of samples to be extracted. Clock control can be changed in accordance with the direction in which (STCn-PCRn) shifts, and stable and quick clock reproduction control can be performed.
[0047]
Embodiment 2 FIG.
In the first embodiment described above, it has been described that the clock regeneration control is performed using a preset coefficient such as the sampling period, the sampling number, and the frequency shift regardless of the magnitude of the network fluctuation. However, in the second embodiment, the control method such as the coefficient is changed according to the situation of the network fluctuation so that the optimal clock reproduction can always be performed.
[0048]
FIG. 6 is a configuration diagram illustrating a clock recovery device according to the second embodiment.
In the figure, reference numeral 4 denotes a fluctuation prediction means for predicting the magnitude of the network fluctuation from information of the reproduction clock information (STC) 7 and the reception clock information (PCR) 8. 6, the same reference numerals as those in FIG. 1 denote the same or equivalent elements as in FIG. 1, and a detailed description of these components will be omitted.
[0049]
Next, the operation will be described. Except for the operation described below, the operation is the same as that of the first embodiment.
The fluctuation prediction means 4 predicts the magnitude of the network fluctuation from the fluctuation of the counter difference (STCn-PCRn) between the reproduction clock information (STC) 7 and the reception clock information (PCR) 8, and the clock control means 3 Notify
[0050]
The clock control means 3 determines and controls the frequency of the reproduction clock of the clock reproduction means 1 based on the reproduction clock information (STC) 7, the reception clock information (PCR) 8, and the network fluctuation prediction information predicted by the fluctuation prediction means 5. I do.
[0051]
Since the magnitude of the network fluctuation is proportional to the fluctuation of the counter difference (STCn-PCRn), it can be estimated to some extent from the difference between the maximum value and the minimum value of the counter difference within a certain time or within the number of samples.
[0052]
When the network fluctuation is large, the possibility that the delay time of the reception clock information (PCR) 8 approaches the minimum value decreases. If clock recovery control is performed without using the received clock information (PCR) 8 whose delay time is close to the minimum value, accurate clock recovery cannot be performed because errors are included in the clock recovery control. Therefore, when the network fluctuation is large, by increasing the number of samples of the reception clock information (PCR) 8, the probability of selecting the reception clock information (PCR) 8 whose delay time is close to the minimum value increases, and accurate clock recovery is performed. Can be performed. By increasing the sample time, the number of samples can be increased.
[0053]
However, increasing the number of samples and the sample time of the received clock information (PCR) 8 results in an increase in the control interval, which makes it impossible to perform quick clock reproduction.
[0054]
Therefore, when the fluctuation is small, the clock time can be quickly reproduced by reducing the sample time or the number of samples of the received clock information (PCR) 8 and controlling the frequency of the reproduced clock of the clock reproducing means 1.
[0055]
As described above, according to the second embodiment, the fluctuation estimation means 5 predicts the magnitude of the network fluctuation, and the period and the number of samples of the reception clock information (PCR) 8 sampled based on the predicted magnitude of the network fluctuation. Is determined and controlled, so that the clock can be quickly and stably reproduced in accordance with the magnitude of the network fluctuation.
[0056]
In the case where the clock difference is managed by the zone as described in the first embodiment, in the second embodiment, the size of the zone may be changed according to the magnitude of the network fluctuation. In other words, when the network fluctuation is large, stable clock reproduction can be performed by increasing the zone of the clock difference so as not to erroneously recognize the fluctuation as a frequency change. When the fluctuation is small, the time required to cross the zone is shortened by reducing the zone of the clock difference. As a result, the control interval is shortened, and the clock regeneration control can be performed quickly.
[0057]
As described above, the speed of the network fluctuation is predicted by the fluctuation predicting means 5, and the size of the zone for managing the counter difference is changed according to the predicted size of the fluctuation. it can.
[0058]
Note that also in the second embodiment, various processes performed by the clock control unit 3 described in the first embodiment when performing clock recovery control on the clock recovery unit 1 are described. (Method 1 for selecting (PCR) 8), "Method 2 for selecting received clock information (PCR) 8 with small delay time", "Frequency control of reproduced clock at predetermined time intervals", " "Received clock information (PCR) 8 controls frequency of reproduced clock for every predetermined number", "Example of frequency control of reproduced clock when initially loaded receive clock information (PCR) 8 is not short in delay time", "Counter difference (STCn-PCRn) may be performed in the case of deviation in the direction of magnitude. By doing so, the effect described in the first embodiment can be obtained together with the effect in the second embodiment.
[0059]
Embodiment 3 FIG.
In the above first and second embodiments, the case where the clock regeneration control is performed under the situation where the transmission delay occurs due to the network fluctuation has been described. However, in the third embodiment, the more accurate clock signal can be obtained regardless of the presence or absence of the network fluctuation. An embodiment for performing high clock reproduction control will be described. Note that the configuration of the clock recovery device is the same as that of the first embodiment shown in FIG. 1 or the second embodiment shown in FIG. 6, and therefore, the description of the configuration is omitted and the features are referred to those drawings. Only the operation will be described.
[0060]
The basic clock reproduction control operation except for the control algorithm in the clock control means 3 is the same as in the first and second embodiments, and therefore, the description is omitted.
[0061]
FIG. 7 is an explanatory diagram showing changes in counter values on the transmission side and the reception side.
The clocks on the transmission side and the reception side each operate at a predetermined frequency, and the counter means 2 is incremented at that frequency. Therefore, the transition of the counter value naturally rises at each step like a staircase. FIG. 7 shows a trajectory when it is assumed that the counter continuously increases. The counter value at a certain time is obtained by cutting off or rounding up the decimal point of the counter value indicated by a point intersecting the time on the straight line indicating the locus F of the counter value. For example, the counter value on the transmitting side at time t0 indicates 123.2 on a straight line, but the actual counter value is 123 when rounded down.
[0062]
In order to recognize the frequency difference between transmission and reception, the amount of change in the difference between the transmission and reception counters per unit time is required.
The counter difference from t0 to t13 in FIG. 7 is -1,0,0,1,1,0,1,1,1,2,1,1,2,2.
When the difference between the counter values that change in a stepwise manner is obtained, an error of ± 1 due to rounding down or rounding up is added, and an accurate frequency difference cannot be obtained. This is a kind of quantization error.
[0063]
Since the frequency difference in FIG. 7 is the variation of the difference indicated by two straight lines per unit time, if the frequency difference is obtained using only the information of the point that accurately indicates the difference between the two straight lines, the accurate Clock recovery can be performed. The value obtained by subtracting the straight line on the transmitting side from the straight line on the receiving side increases with time. The counter difference indicates 1 when one change point of the counter value falls between the two straight lines. At this time, the difference between the two straight lines is larger than 0 and smaller than 2.
[0064]
As shown in FIG. 7, when the counter difference slightly increases or decreases but gradually increases, the linear difference increases with time at a plurality of times having the same counter difference. The first change point of the counter difference value is the smallest linear difference among the points having the same counter difference value. At this time, the linear difference becomes a value close to the value obtained by subtracting 1 from the counter difference.
Therefore, the first change point of the value of the counter difference is a value close to {linear difference + 1}.
[0065]
By performing clock control using only points at which the linear difference can be obtained to some extent accurately, accurate clock regeneration can be performed. Therefore, clock control is performed using only the first change point of the value of the counter difference.
In FIG. 7, if the frequency difference is obtained using the counter differences at t3 and t9, which are the first change points of the counter difference value, a more accurate frequency difference can be obtained. The frequency difference obtained by the calculation is ｛(counter difference at t9) − (counter difference at t3)) / time = (2-1) / 6Δt = 1 / 6Δt, and the difference between the slopes of the two straight lines shown in FIG. Is almost the same as
[0066]
Also, an accurate frequency difference can be obtained by using only the last change point of the value of the counter difference. The last change point of the value of the counter difference is a value close to {linear difference-1}.
In FIG. 7, the frequency difference obtained using t5 and t11, which are the last change points of the counter difference value, is similarly １ ／ Δt.
[0067]
As described above, according to the third embodiment, even when the counter difference changes only slightly, an accurate frequency difference can be obtained by using only the information of the first or last change point of the counter difference, Accurate clock reproduction can be performed.
[0068]
In the third embodiment, the control algorithm in the clock control unit 3 is different from that in the first and second embodiments. However, the present invention is not limited to this, and the clock control unit 3 in the first and second embodiments is not limited to this. Of course, the control algorithm in the third embodiment may be replaced with the control algorithm in the third embodiment.
[0069]
In the first to third embodiments, the reception clock information 8 or the reproduction clock information 7 is described by way of an example of the PCR (Program Clock Reference) and the STC (System Time Clock) in the MPEG-2 system standard. However, the invention is not limited to this, and any invention may be used as long as the reproduction clock information 7 is generated and synchronized on the reception side based on the clock information 8 on the transmission side, and the invention is not limited to the MPEG-2 system standard. .
[0070]
【The invention's effect】
According to the present invention, the reproduction clock is counted, and only valid reception clock information (PCR) 8 is selected from the reception clock information (PCR) 8 received from the transmission side, and the selected reception clock information (PCR) is selected. 3) Since the frequency of the reproduction clock is controlled based on 8 and the count value, stable clock reproduction can be performed even in a situation where the network fluctuation is large.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing a clock reproduction device according to a first embodiment of the present invention.
FIG. 2 is an explanatory diagram illustrating a mechanism of clock synchronization based on the MPEG-2 system standard.
FIG. 3 is an explanatory diagram illustrating a relationship between a transmission time and a reception time of reception clock information (PCR) 8;
FIG. 4 is an explanatory diagram showing an example of a method for selecting reception clock information (PCR) 8 having a small delay time.
FIG. 5 is an explanatory diagram showing another example of a method for selecting reception clock information (PCR) 8 having a small delay time.
FIG. 6 is a configuration diagram showing a clock recovery device according to a second embodiment.
FIG. 7 is an explanatory diagram showing transition of counter values on a transmission side and a reception side in the third embodiment.
[Explanation of symbols]
1 clock recovery means, 2 count means, 3 clock control means, fluctuation estimation means.

Claims (14)

Clock recovery means for outputting a recovered clock;
Counting means for counting the reproduced clock output by the clock reproducing means,
Only valid clock information is selected from the clock information received from the transmitting side, and the frequency of the reproduced clock output from the clock reproducing means is controlled based on the selected received clock information and the count value of the counting means. Clock control means;
A clock recovery device comprising: 2. The clock recovery apparatus according to claim 1, wherein said clock control means selects reception clock information having a short transmission delay time until reception as effective reception clock information. The clock control means, when selecting reception clock information having a small transmission delay time as effective reception clock information, uses a plurality of reception clock information to calculate a time axis direction from an approximate straight line obtained from each value and the reception time. 3. The clock recovery apparatus according to claim 2, wherein the selection is made smaller and further away from the approximate straight line. The clock control unit, when selecting the reception clock information having a small transmission delay time as the effective reception clock information, selects a value obtained by subtracting the value of the reception clock information from the counter value of the counting unit and having a smaller value. 3. The clock recovery device according to claim 2, wherein The clock control means selects valid clock information from a plurality of received clock information received at predetermined time intervals, and outputs the clock data from the clock reproduction means based on the selected received clock information and the count value of the counting means. 5. The clock recovery device according to claim 1, wherein the frequency of the output recovered clock is controlled. The clock control means selects valid clock information from a plurality of received clock information received for each predetermined number of samples, and based on the selected received clock information and a count value of the counting means, 5. The clock reproducing apparatus according to claim 1, wherein the frequency of the reproduced clock output from the controller is controlled. Further, a fluctuation estimating means for detecting or estimating the fluctuation of the network from the received clock information,
The clock control means determines the sample time or the number of samples of the received clock information based on the magnitude of the fluctuation of the network estimated by the fluctuation estimation means,
7. The clock recovery device according to claim 5, wherein: 8. The clock reproducing apparatus according to claim 1, wherein, when controlling the frequency of the reproduced clock, the clock control unit adds and controls a difference of the transmission delay time of the received clock information received first. The clock control means calculates a counter value difference obtained by subtracting the selected received clock information from the counter value of the counting means, classifies the data into several zones based on the counter value difference, and calculates a counter value difference based on a change in the counter value difference. 9. The clock reproducing apparatus according to claim 1, wherein the frequency control of the reproduced clock is performed only when the clock has moved to a different zone. 10. The clock reproducing apparatus according to claim 9, wherein the clock control means controls the frequency of the clock by changing the size of the zone of the counter value difference according to the magnitude of the network fluctuation. As a result of calculating the counter value difference, the clock control means calculates the counter value difference after further increasing the sample data when the counter value increases from before and the counter value difference enters a different zone. 11. The clock reproducing apparatus according to claim 9, wherein the frequency control of the reproduced clock is performed only when moving to a different zone due to a change in the counter value difference. When the difference between the received clock information and the counter value of the counting means changes only slightly, the clock control means uses the received clock information of only the first or last change point in the difference value. A clock recovery device according to any one of claims 1 to 11. A data communication device comprising the clock recovery device according to any one of claims 1 to 11, wherein the data recovery device reproduces received data based on a reproduction clock whose frequency is controlled by the clock reproduction device. Counting the reproduction clock, selecting only valid clock information from the clock information received from the transmission side, and controlling the frequency of the reproduction clock based on the selected reception clock information and the count value. Characteristic clock recovery method.

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