JP2008118549A - Receiving apparatus and clock synchronization method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform clock control in dejittering, while satisfying a predetermined drift rate and to shorten the time until a clock-controlled variable in dejittering is approximately converged and the clock control can be performed, while satisfying the predetermined drift rate. <P>SOLUTION: A receiving unit 31 includes a time count generating section 46 for generating time count information; a communication I/F section 41 for receiving a packet from a transmitter; a time count differential calculating section 43 for calculating the time count differential, on the basis of first time count information contained in the packet from the transmitter and second time count information which has been generated by the time count generating section 46, when the communication I/F section 41 received the packet; a data filter 44 for removing an abnormal value of the time count differential; and a frequency difference estimating section 45 for calculating the frequency difference of an oscillator from the transmitter, from the information of the time count differential passed through the data filter. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a receiving apparatus and a clock synchronization method. In particular, the present invention relates to a technique for realizing high-speed clock synchronization between terminals that transmit and receive via a network that causes jitter.

  In a video transmission system based on MPEG2-TS (Motion Picture Experts Group 2-Transport Stream), it is known that a failure occurs unless the receiver processes at the same speed as the transmitter.

  Also, video transmission by MPEG2-TS is as follows: (1) Transmitter sends video at its own pace, (2) No feedback from receiver, (3) Transmitter takes video just taken (4) The transmitter has the property that it can transmit video to a plurality of receivers.

  For this reason, it is necessary that (1) the transmitter side transmits clock information to the receiver, and (2) the receiver side incorporates a PLL (Phase Locked Loop) to regenerate the clock synchronized with the transmitter side. It is.

  FIG. 16 is a block diagram showing a typical example of a video transmission system based on MPEG2-TS.

  A video transmission system based on MPEG2-TS will be described with reference to FIG. As shown in FIG. 16, the transmitter 1200 encodes video data from the input video source by the MPEG2 encoder 1202 and simultaneously gives clock information by the oscillator 1204. The MPEG2-TS packet stored in the transmission buffer 1206 is transmitted to the receiver 1210. The receiver 1210 stores the MPEG2-TS packet from the transmitter 1200 in the reception buffer 1212. Then, clock information is extracted from the MPEG2-TS packet, and a clock synchronized with the MPEG2 encoder 1202 is reproduced using the PLL 1214. In addition, the MPEG2 decoder 1216 decodes the video data using the reproduction clock.

  Thus, the decoder uses the PLL to generate a counter STC (System Time Clock) synchronized with the encoder clock. Note that the clock information PCR (Program Clock Reference) from the MPEG encoder is embedded in the MPEG2-TS packet at a rate of at least once every 0.1 second.

FIG. 17 is a block diagram showing a configuration of a general PLL.
With reference to FIG. 17, a configuration of a commonly used PLL as shown in section (D.0.3) of Non-Patent Document 1 in the MPEG2 decoder will be described. In the PLL, when a TS packet including PCR is first received, the PCR value is loaded into the internal counter 1302. Each time a TS packet including a subsequent PCR is received, a subtractor 1304 obtains the difference between the STC value and the PCR value given from the internal counter 1302 at the time of reception. Subsequently, the difference is applied to the low-pass filter 1306 to be converted into a control voltage, whereby the frequency of the voltage-controlled oscillator 1308 is changed. Accordingly, the output of the internal counter 1302 is adjusted, and an STC value synchronized with the encoder clock is generated.

  Although the PLL operates as described above, in order to stabilize such an operation, each MPEG2-TS packet is kept free from jitter as much as possible (the mutual interval when output from the transmitter is maintained). To the MPEG decoder).

  Section (D.0.9) of Non-Patent Document 1 and Non-Patent Document 2 describe a jitter absorption method when a video stream is received via a network that causes jitter.

  Non-Patent Document 2 describes the following three methods (a) to (c). Here, the function for absorbing jitter (dejittering) may exist separately from the MPEG decoder, or may be integrated into the MPEG decoder itself.

  (A) In the case of CBR (Constant Bit Rate), a method using a buffer and a PLL.

  According to the method (a), the PLL on the receiver side adjusts the output rate on the receiver side so that the usage amount of the receiver side buffer is approximately halved according to the usage amount of the receiver side buffer. .

(B) A method using a time stamp.
FIG. 18 is a diagram showing an outline of the video transmission system described in Non-Patent Document 2.

  The method (b) will be described with reference to FIG. In transmitter 1400, clock 1402 assigns sample value CR (Clock Reference) to each packet generated by encoder 1404.

  The receiver 1410 restores TCd (delayed TC) using the PLL 1414 from the sample value CR included in the received packet. “TCd” is obtained by adding a fixed time to the counter value generated by the clock 1402 on the transmitter 1400 side.

  The receiver 1410 temporarily stores the video data from the transmitter 1400 in the dejittering buffer 1416 and reproduces it. The leading packet is output from the de-jittering buffer 1416 in response to the determination by the control unit 1418 that TCd is equal to the CR included in the packet. The subsequent MPEG2 packet is output from the de-jittering buffer when the CR included in the packet becomes equal to TCd.

  The size of the de-jittering buffer is designed such that the packet transmission delay is delayed by an average delay time ± J / 2 [seconds] (however, the transmitter / receiver is designed to compensate for delay fluctuations of maximum J [seconds]). Designed to withstand the added transmission delay. If the packet arrives with an average delay time, the de-jittering buffer occupies an intermediate position. When a packet arrives with a delay of J / 2 [seconds] compared to the average delay time, the de-jittering buffer becomes empty. If the packet arrives J / 2 [seconds] earlier than the average delay time, the de-jittering buffer is full.

(C) A method of using a common clock when a common clock is available.
According to the method (c), when a common network clock is available between the transmitter and the receiver and the frequency of the system clock can be locked thereto, the jitter can be absorbed by using a buffer.

  Further, section (D.0.9) of Non-Patent Document 1 also describes a method in which the above method (a) is improved so that it can be applied to the case of VBR (Variable Bit Rate). . This is the method (a ′).

  In the method (a ′), the time at which data is input to the buffer is measured using PCR or SCR, not the usage amount of the receiver buffer, and the time at which the data is output from the buffer is controlled. A PLL similar to that in FIG. 17 is configured and adjusted so that the period from when data is input to the buffer until it is output is constant.

  Patent Document 1 describes a method of synchronizing a data supply device and a data processing device. According to this method, the difference value generated between the transmission time of data transmitted from the data supply device and the reception time of data received by the data processing device is sequentially detected. Then, the local maximum value and the local minimum value of the difference value are detected every predetermined time, and the processing speed of the data processing device is controlled in accordance with the increase / decrease of the local maximum value and the local minimum value to achieve synchronization.

  Patent Document 2 describes a method of correcting a counter value. According to this method, the counter correction means for correcting the transmission source counter value so as to remove the fluctuation of the reception timing of the reception clock information is provided. As a result, a straight line indicating the time change of the counter value that minimizes the sum of squares of the differences from the received counter values is obtained, and the counter value is corrected so that the newly received counter value is positioned on the straight line. .

  Patent Document 3 describes a method similar to the method (a ′). According to this method, the amount of data stored in the receiver is monitored, and when the amount of stored data exceeds the upper threshold, the frequency of the reception clock is set to a high frequency. Further, when the data storage amount becomes smaller than the lower reference value, the reception clock frequency is set to a low frequency.

  Patent Document 4 describes a method similar to Patent Document 3. According to this method, the data output speed to the decoder is not switched in two steps of high and low, but the data output speed is gradually changed at the switching timing.

  FIG. 19 is a diagram showing the relationship between the data accumulation amount (buffer time amount) and the clock control amount in Patent Literature 3 and Patent Literature 4.

  As shown in FIG. 19, when the data accumulation amount (buffer time amount) exceeds the upper threshold value, the clock control amount is set high, and when it falls below the lower threshold value, the clock control amount is set low. The machine can continue to play without causing internal buffer overrun or underrun.

Also, Patent Document 5 eliminates the clock shift between transmission and reception by smoothing the relative fluctuation time in a network environment where transmission delay fluctuation occurs and monitoring the monotonic increase or decrease with time. There has been proposed a method of controlling in such a direction.
JP 2003-218842 A JP 2000-174742 A Japanese Patent Laid-Open No. 2002-165148 Japanese Patent Laid-Open No. 2006-42273 JP-A-2003-258894 ISO / IEC13818-1: 2000 (E) AnnexD ISO / IEC13818-1: 2000 (E) AnnexJ ITU-T Recommendation J.M. 133 (07/2002) Appendix I

  The method described in section (D.0.3) of Non-Patent Document 1 is a method generally used in MPEG decoders such as digital broadcasting. However, the video data passes through a network that causes jitter. If transmitted, the PLL does not operate normally and there is a problem that the video is not displayed.

  In FIG. 17, in the PLL, a subtracter 1304 calculates the difference between the STC value of the internal counter and the PCR value. If the difference value is not kept within a certain range (several tens of μs), the MPEG decoder determines that a stable STC value has not been generated, and may stop displaying video during that period.

  For example, when video data is transmitted via a network that causes jitter, the difference value cannot be kept within a certain range. Therefore, the PLL alone of the MPEG decoder can generate a stable STC value. Can not.

  Therefore, when video data is transmitted via a network that causes jitter, a function for absorbing jitter is necessary in addition to the PLL described in (D.0.3) of Non-Patent Document 1. It is considered to be.

  In addition, the three methods (a) to (c) described in Non-Patent Document 2 have a problem that the method (a) can be applied only when the video data is CBR. Considering versatility, it should be applicable to VBR.

  The method (b) can be applied to VBR. The point of giving a time stamp to the packet is the same as the present invention. However, when the TCd is restored using the PLL, there is no problem even if the average value of the packet transmission delay time is large. However, if the variation is large, there is a problem that it takes too much time for the PLL to synchronize.

  The video transmission system according to the present invention assumes that video data is transmitted via a general IP (Internet Protocol) network such as a wireless network, a wired network, or the Internet. For this reason, in such an environment, jitter of at least about several hundreds of milliseconds can occur.

  On the other hand, when the method (b) is used as a function for absorbing jitter (hereinafter referred to as “dejittering”), and the PLL described in the section (D.0.3) of Non-Patent Document 1 is used at the subsequent stage, Then, the target accuracy for absorbing jitter by the method (b) needs to be about several tens of μs.

  In a network environment that causes jitter as assumed in the present invention, it is difficult to suppress to a sufficient accuracy with a PLL, and even if it can be suppressed, the pull-in time until synchronization becomes very long. As a result, there is a problem that no video is displayed during that period.

  Method (c) is based on the premise that a common clock exists between end-to-end. Although this method may use a common clock in some closed environments, such a common clock does not exist on a general IP network, so that there is a problem that it is not versatile.

  Method (a ') also has the same problem as method (b). That is, since the amount of jitter assumed in the present invention is large, it is difficult to suppress the PLL to a sufficient accuracy, and even if it can be suppressed, the pull-in time until synchronization may become very long. is there.

  Problems to be considered in dejittering control include (1) a VCXO (Voltage Controlled Crystal Oscillator) problem of the MPEG decoder and (2) problems in the MPEG standard.

  (1) The VCXO problem of the MPEG decoder is that if the clock control amount is set too large (for example, controlled at ± 200 ppm) in de-jittering control, the frequency adjustment range of the MPEG decoder VCXO is out of range. The problem is that the video is not displayed. The VCXO is usually included in the PLL. For example, it corresponds to the voltage controlled oscillator 1308 in FIG.

  A specific example will be described. For example, in the MPEG video transmission system as shown in FIG. 16, the frequency variable range of the VCXO included in the PLL of the receiver 1210 is ± 75 ppm around the nominal frequency, and the accuracy of the oscillator 1204 of the transmitter 1200 is ± 100 ppm. . In this case, even if there is no influence by the network, there is a possibility that it exceeds the range controllable by the VCXO, so that the decoder cannot follow the clock of the encoder and there is a possibility that the video is not displayed. Whether an image is displayed depends on the accuracy of the oscillator components. Considering the effects of the network, the accuracy of the transmitter's oscillator and the accuracy of the receiver's oscillator must be considered.

FIG. 20 is a diagram for explaining conditions for displaying an image.
With reference to FIG. 20, it will be described under what conditions video is displayed. In FIG. 20, the accuracy of the oscillator 1601 of the MPEG2 encoder 1600 is ± E [ppm], the accuracy of the oscillator 1603 of the transmitter 1602 is ± T [ppm], the accuracy of the oscillator 1607 of the receiver 1606 is ± R [ppm], MPEG2 The accuracy of the nominal frequency of the VCXO 1609 included in the PLL of the decoder 1608 is ± P [ppm], and the frequency adjustable range is ± W [ppm]. However, E, T, R, P, W> 0.

  At the time when data is input from the MPEG2 encoder 1600 to the MPEG2 decoder 1608 via the transmitter 1602, the network 1604, and the receiver 1606, the clock information PCR given by the MPEG2 encoder 1600 has the worst ± {E + T + R} [ppm]. Clock accuracy error may be included. This value must be within the frequency variable range of the VCXO 1609 in order for the video to be displayed. Therefore, the condition of the following formula (1) is necessary.

E + T + R <WP-Formula (1)
One specific value is E = 30, T = R = 50, P = 15, W = 150. In this case, since the expression (1) is satisfied, it is considered that the video is displayed from the beginning. However, in the de-jittering control, if the amplitude of the clock control amount becomes large, the expression (1) may not be satisfied. Therefore, even when dejittering control is performed, it is problematic to set the amplitude of the clock control amount too large in order to satisfy the expression (1).

Next, (2) problems in the MPEG standard will be described.
Non-Patent Document 3 (4.3) to (4.6) describes the PCR limit (how much deviation from the nominal frequency of 27 MHz is allowed).

  Specifically, it describes PCR frequency offset, PCR drift rate, PCR overall jitter, and PCR accuracy. In particular, the limits of the PCR frequency offset and the PCR drift rate are as follows (hereinafter referred to as “PCR conditions”).

(Limit of PCR frequency offset) = ± 810 Hz or ± 30 ppm
(Limit of PCR drift rate) = ± 75 mHz / second or ± 10 ppm / hour In Non-Patent Document 3, it is described that PCR accuracy does not make sense in the case of a variable bit rate. The PCR overall jitter has a standard of ± 500 ns when the network delay is zero, but no clear standard when a network delay exists. In ISO / IEC13818-9, a standard of ± 25 us is shown. However, if a time stamp having sufficient accuracy is given to each packet, this standard can be observed, so it is not considered to be a problem. .

  Since the PCR condition is a request seen from the MPEG decoder side, it is considered that the condition should be observed including clock control in dejittering. However, the fact that PCR conditions cannot be observed does not immediately cause a practical problem (for example, video is not displayed or video quality is deteriorated). However, although it depends on the chip of the MPEG decoder, it is considered that a practical problem occurs if the PCR conditions are greatly deviated.

  In the method (b) and the method (a ′), it is impossible to predict how much clock control is performed by the PLL, and it is considered impossible to satisfy the PCR condition and transmit.

  In the method described in Patent Document 1, the data processing speed is changed every predetermined time. Since the amount of clock control to be changed at a time can be freely determined, it is considered possible to satisfy the PCR conditions depending on the design.

FIG. 21 is a diagram showing a time change of the clock control amount.
As shown in FIG. 21, first, the step of the clock control amount is increased, and the step is gradually decreased. If the step of the clock control amount remains small from the beginning, it takes time until the clock control amount almost converges. Therefore, the step of the clock control amount is set large from the beginning and gradually decreased.

  Even if such a method is implemented, Patent Document 1 determines whether to increase or decrease the data processing speed every predetermined time. If the predetermined time is not repeated several times, clock control in dejittering is performed. It cannot be brought to a state where the quantity almost converges. (The predetermined time is at least several seconds and the number of repetitions is at least several tens of times. It takes several minutes until the clock control amount is almost converged.) Therefore, the dejittering control amount is almost equal. There is a problem that it takes time to converge.

  Further, Patent Document 2 discloses a method of correcting the PCR value using the least square method, but there is a problem that the slope obtained by the least square method is not accurate when the packet transmission delay time varies greatly. .

  Further, in the methods of Patent Document 3 and Patent Document 4, the clock control amount in de-jittering basically has only two stages, that is, slow or fast, and only exceeds the variation in clock oscillation frequency accuracy between the transmitter and the receiver. It must be controlled with a large amplitude. For example, if the clock oscillation frequency accuracy of the transmitter and the receiver is both ± 100 ppm, the clock control amount in dejittering must be changed in a range of ± 200 ppm or more. In the methods of Patent Document 3 and Patent Document 4, it is considered that the VCXO problem of the MPEG decoder cannot be cleared because the amplitude of the clock control amount is too large. In addition, it is considered that the PCR condition (PCR drift rate) cannot be maintained because the clock control amount changes too quickly.

  Further, in Patent Document 5, since all data is subjected to a smoothing filter, if the variation in packet transmission delay time is large, the smoothing filter does not converge and the clock frequency difference cannot be accurately obtained. There's a problem.

  The present invention has been made in order to solve the above-described problems, and an object of the present invention is to control while satisfying a predetermined drift rate in clock control in dejittering, and to provide a clock control amount for dejittering. This is to shorten the time until control can be performed while substantially converging and satisfying a predetermined drift rate.

  According to one aspect of the present invention, a reception device for data communication with a transmission device connected to a network, wherein a time count generation for generating first time count information as a reference clock on the reception device side Means, receiving means for receiving a packet from the transmitting apparatus, second time count information included in the packet from the transmitting apparatus, and generated by the time count generating means when the receiving means receives the packet Time count difference calculating means for calculating a time count difference based on the first time count information, a data filter for removing an abnormal value of the time count difference, and information on the time count difference that has passed through the data filter And a frequency difference estimating means for calculating a frequency difference from the reference clock on the transmitting apparatus side.

  Preferably, the frequency difference estimator determines a clock control amount based on the calculated frequency difference, and advances the first time count information generated by the time count generator according to the clock control amount from the frequency difference estimator. Time count control means for controlling the direction.

  Preferably, the data filter calculates a corrected time count difference based on the first time count information and the third time count information obtained by simulatingly speeding up the second time count information, and calculates the minimum time until the calculation time. The time count difference corresponding to the correction time count difference that is larger than the correction time count difference is removed as an abnormal value.

  Preferably, the data filter calculates a corrected time count difference based on the second time count information and the fourth time count information obtained by artificially delaying the first time count information, and minimizes the time until the calculation time. The time count difference corresponding to the correction time count difference that is larger than the correction time count difference is removed as an abnormal value.

  Preferably, the data filter obtains a minimum value for each predetermined time interval, and removes a time count difference other than the minimum value as an abnormal value.

  Preferably, the frequency difference estimation means calculates a frequency difference by approximating the relationship between the time from the time when the reception means starts receiving the packet and the time count difference with a straight line by regression analysis.

  Preferably, the apparatus further includes an accuracy determining unit for determining the accuracy of the frequency difference calculated by the frequency difference estimating unit.

  Preferably, the accuracy determination unit determines that the accuracy of the frequency difference is a predetermined accuracy in response to a lapse of a predetermined time from the time when the reception unit starts receiving the packet.

  Preferably, the accuracy determining unit determines that the accuracy of the frequency difference is a predetermined accuracy in response to receiving a predetermined number of packets from the time when the receiving unit starts receiving the packets.

  Preferably, the accuracy determining means determines that the accuracy of the frequency difference is a predetermined accuracy in response to the number of time count differences that have passed through the data filter reaching a predetermined number.

  Preferably, the accuracy determination unit determines that the accuracy of the frequency difference is a predetermined accuracy in response to the difference between the maximum value and the minimum value of the frequency difference calculated before the predetermined timing being within a predetermined range. .

  Preferably, the accuracy determination means determines that the accuracy of the frequency difference is a predetermined accuracy in response to the residual sum of squares calculated from the time count difference information and the approximated straight line being within a predetermined range. To do.

  Preferably, a steady state clock control amount determining means for determining a clock control amount so as to satisfy a predetermined drift rate condition, and the time count control means, the clock control amount from the frequency difference estimating means or the Selecting means for selectively giving any one of the clock control amounts from the steady state clock control amount determining means, wherein the selecting means is configured such that the accuracy determining means has the accuracy of the frequency difference at a predetermined accuracy. In response to the determination that there is a clock control amount from the steady state clock control amount determination unit, the time count control unit is given in place of the clock control amount from the frequency difference estimation unit.

  Preferably, the steady state clock control amount determining means includes a time clock difference minimum value detecting means for detecting a minimum value of the time count difference and a reference clock based on a change in the detected minimum value in a predetermined period. And a time count delay determination means for determining a clock control amount so that the progress of the clock is within a predetermined drift rate range.

  Preferably, a buffer for accumulating the received packet, a first buffer time amount indicating a time range of time count information of the packet accumulated in the buffer included in the packet from the transmitting device, and the packet receiving device A buffer time amount calculating means for calculating a third buffer time amount that is the sum of the second buffer time amounts at the time of being stored in the buffer, and the steady state clock control amount determining means is In the period, the buffer time amount maximum value detecting means for detecting the maximum value of the third buffer time amount, and how to advance the reference clock within a predetermined drift rate range based on the detected change in the maximum value And a time count delay determination means for determining the clock control amount.

  Preferably, the apparatus further includes a buffer for accumulating packets, and the steady state clock control amount determination unit is configured to set a fourth buffer time amount indicating a time range of the time count information of the packets accumulated in the buffer during a predetermined period. Based on the buffer time amount maximum value detecting means for detecting the maximum value and a change in the detected maximum value, the clock control amount is determined so that the reference clock advances within a predetermined drift rate range. Time count delay determination means.

  According to another aspect of the present invention, a reception device for data communication with a transmission device connected to a network, wherein a time count generation for generating first time count information as a reference clock on the reception device side Means, receiving means for receiving a packet from the transmitting apparatus, second time count information included in the packet from the transmitting apparatus, and generated by the time count generating means when the receiving means receives the packet Based on the first time count information, the time count difference calculating means for calculating the time count difference, and the frequency difference from the reference clock on the transmitting device side is calculated from the information on the time count difference, and the clock control amount A frequency difference estimating means for determining the frequency difference, and an accuracy determining means for determining the accuracy of the frequency difference calculated by the frequency difference estimating means. That.

  Preferably, the frequency difference estimation unit determines a clock control amount based on the calculated frequency difference, and the time count generation unit generates the first control value according to the clock control amount from the frequency difference estimation unit. Time count control means for controlling how the time count information advances is further provided.

  Preferably, a steady state clock control amount determining means for determining a clock control amount so as to satisfy a predetermined drift rate condition, and the time count control means, the clock control amount from the frequency difference estimating means or the Selecting means for selectively giving any one of the clock control amounts from the steady state clock control amount determining means, wherein the accuracy determining means is such that the accuracy of the frequency difference is a predetermined accuracy. In response to the determination, a clock control amount from the steady state clock control amount determination unit is given to the time count control unit instead of the clock control amount from the frequency difference estimation unit.

  According to still another aspect of the present invention, a receiving device for data communication with a transmitting device connected to a network, a receiving means for receiving a packet from the transmitting device, and a reference clock on the receiving device side A time count generating means for generating the first time count information, a detecting means for detecting the control state of the reference clock, and a transmitting means for notifying the transmitting apparatus of the detected control state. .

  Preferably, the apparatus further includes a transmission unit for notifying the transmission device that the accuracy determination unit has determined that the accuracy of the frequency difference is a predetermined accuracy.

  Preferably, the apparatus further includes power input detection means for detecting a power input state with respect to the receiving device, and the selection means is provided to the time count control means in response to detection of power input or reset by the power input detection means. On the other hand, a clock control amount from the frequency difference estimation means is given.

  Preferably, the selection unit gives the clock control amount from the frequency difference estimation unit to the time count control unit in response to the determination that the reception unit has not received the packet from the transmission device for a predetermined time.

  Preferably, the transmission device transmits a dummy packet to the reception device, and the frequency difference estimation means estimates the frequency difference based on the time count difference of the dummy packet.

  According to still another aspect of the present invention, a reception device for data communication with a transmission device connected to a network, and a time count for generating first time count information as a reference clock on the reception device side Generation means, receiving means for receiving packets from the transmitting apparatus, buffer for storing received packets, and time count information of packets stored in the buffer included in the packets from the transmitting apparatus Buffer time amount calculating means for calculating a third buffer time amount that is the sum of the first buffer time amount indicating the range and the second buffer time amount at the time when the packet is accumulated in the buffer of the receiving device; A data filter for removing an abnormal value of the third buffer time amount, and information on the third buffer time amount that has passed through the data filter. , And a frequency difference estimating means for calculating the frequency difference between the reference clock of the transmitting apparatus side.

  According to still another aspect of the present invention, there is provided a clock synchronization method for data communication with a transmission device connected to a network, the step of generating first time count information as a reference clock on the reception device side; Based on the step of receiving a packet from the transmission device, the second time count information included in the packet from the transmission device, and the first time count information generated when the packet is received in the reception step A step of calculating a time count difference, a step of removing an abnormal value of the time count difference, and a step of calculating a frequency difference from the reference clock on the transmitting device side from the information of the time count difference from which the abnormal value has been removed. Prepare.

  According to the present invention, in clock control in de-jittering, control is performed while satisfying a predetermined drift rate, and the time until control can be performed while satisfying the predetermined drift rate after the de-jittering clock control amount is almost converged is shortened. it can.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same parts are denoted by the same reference numerals. Their names and functions are also the same. Therefore, detailed description thereof will not be repeated.

  As will be apparent from the following description, according to the present invention, in clock control in dejittering, control is performed while satisfying a predetermined drift rate, and the clock control amount of dejittering is substantially converged to achieve a predetermined drift rate. Shorten the time until control can be achieved with satisfaction.

FIG. 1 is a diagram showing a time course of a clock control amount of dejittering.
In FIG. 1, the vertical axis represents the clock control amount, and the horizontal axis represents time. As shown in FIG. 1, the receiving apparatus according to the present invention specifically falls within a range of about ± 10 ppm in the first few seconds, and thereafter performs control while satisfying a predetermined drift rate. In the following description, the control state (T1) that fits at once in the first few seconds is called “transient state”, and the subsequent change in the clock control amount is in the state of synchronous control (T2). This is called “steady state”.

[Embodiment 1]
FIG. 2 is a diagram showing a network video transmission system according to the present embodiment.

  The network video transmission system 100 will be described with reference to FIG. The video transmission system 100 includes a transmitter 10, a network 20, and a receiver 30. The transmitter 10 and the receiver 30 can transmit and receive data via the network 20.

  The transmitter 10 includes an MPEG encoder 11, a transmission unit 12, and oscillators 13 and 14. The receiver 30 includes a receiving unit 31, an MPEG decoder 32, an oscillator 33, and a variable frequency oscillator 34. The receiving unit 31 also includes a dejittering control unit (not shown).

  In the transmitter 10, video data is input from a video source such as a tuner or a DVD player. The MPEG encoder 11 encodes the video data into an MPEG2 packet and passes it to the transmission unit 12. The transmission unit 12 adds time count information based on the oscillator 13 to the MPEG2 packet to form a packet, and transmits the packet to the receiver 30 via the network 20.

  In the receiver 30, the packet received by the receiving unit 31 is transmitted to the MPEG decoder 32 after the jitter is absorbed by the de-jittering control unit (that is, the interval between the packets is restored). The de-jittering control unit compares the time count information included in the packet with the time count information based on the oscillator 33 and absorbs jitter. The MPEG decoder 32 decodes the MPEG2 packet and outputs the video data to a video sink such as a television.

  The network 20 in the present embodiment is assumed to be a wireless LAN network such as IEEE802.11. However, other than that, it may be a wired LAN network such as Ethernet (registered trademark) or power line communication, or a general IP (Internet Protocol) network via a plurality of repeaters such as the Internet.

FIG. 3 is a diagram illustrating an example of a packet format.
With reference to FIG. 3, the format of the packet transmitted by the transmission unit 12 will be described. In this embodiment, it is assumed that the packet transmission protocol is UDP (User Datagram Protocol) and that the payload portion of UDP is shown in FIG. However, the packet transmission protocol is not limited to UDP, but may be TCP (Transmission Control Protocol), or may be other than those.

  The packet format may be simply a single MPEG2 packet with one piece of time count information. In the present embodiment, the packet has a size suitable for transmission via Ethernet (registered trademark) or the like. Thus, it is assumed that seven MPEG2 packets are transmitted together.

  MPEG2-TS data is assigned to the TS-data fields 200-0 to 200-6. The TS-data field is 188 bytes.

  Time count information based on the oscillator 13 at the time when each MPEG2-TS is input from the encoder is assigned to the TTS fields 210-0 to 210-6. The TTS field is 4 bytes.

  A sequence number of the packet is given to the SEQ field 220. The transmission side increments the packet sequence number by one. The reception side can check packet lost, re-reception of the same packet, or reversal of the packet reception order by looking at the sequence number continuity. In this embodiment, error processing such as packet loss is not described. In FIG. 3, 4 bytes are allocated to the SEQ field, but the SEQ field may be omitted.

In the TXQ field 230, time count information based on the oscillator 13 on the transmission side is given. Time count information at the time of actually trying to transmit a packet is given. In FIG. 3, 4 bytes are allocated to the TXQ field, but the TXQ field may be omitted. In this case, the time count information at the time when the packet is to be transmitted can be replaced with TTS ₆ which is the latest time count information. However, there is a normal time lag between the time when the MPEG2 packet is input from the encoder and the time when the packet is to be transmitted.

  Although not shown in FIG. 2, the transmission unit 12 generally has a transmission buffer. A packet before transmission can be stored in the transmission buffer. By having a transmission buffer, it is possible to obtain tolerance of failure even when a bursty transmission failure occurs in the network 20.

  Further, the count-up frequency of the time count information in the transmitter 10 and the receiver 30 is made common. Here, the count-up frequency of the time count information is 1 MHz. That is, the count is incremented by 1 every 1 μsec.

FIG. 4 is a diagram illustrating state transition of the receiver 30 according to the present embodiment.
The control state of the receiver 30 will be described with reference to FIG. The receiver 30 is roughly divided into two states, a transient state 300 and a steady state 310. The operations in the transient state and the steady state are associated with the movement of the clock control amount described in FIG. In addition, after the receiver 30 is turned on or reset, it enters a transient state.

  The receiver 30 performs high-speed dejittering control in a transient state. If the frequency difference between the oscillators of the transmitter 10 and the receiver 30 is estimated with sufficient accuracy, the high-speed de-jittering control is terminated and the steady state is entered.

  On the other hand, the receiver 30 performs dejittering control while maintaining a predetermined drift rate in a steady state. When the receiver 30 does not receive a packet and a certain period of time elapses, a transition is made to a transient state.

First, an operation when the receiver 30 is in a transient state will be described.
FIG. 5 is a diagram illustrating a detailed configuration of the reception unit 31.

  As shown in FIG. 5, the reception unit 31 includes a communication interface (hereinafter “I / F”) unit 41 for transmitting and receiving packets, a de-jittering buffer 42, a time count difference calculation unit 43, and a data filter. 44, a frequency difference estimation unit 45, a time count generation unit 46, a time count difference minimum value detection unit 47, a time count slow speed determination unit 48, an accuracy determination unit 49, and a selection unit 50.

  The packet received by the communication I / F unit 41 is checked for packet length and the like, and if it is an MPEG packet as shown in FIG.

  The packet stored in the de-jittering buffer 42 is adjusted in timing based on the time count information included in the packet and the time count information generated by the time count generation unit 46 and is output to the MPEG decoder.

  Hereinafter, the timing at which a packet is output from the de-jittering buffer 42 to the MPEG decoder will be described with reference to FIG. First, a parameter is set in advance as to how long to wait after receiving the first packet on the receiver side before outputting the packet to the MPEG decoder. This is the initial reproduction delay time. The initial reproduction delay time is desirably set to a time that can absorb the transmission delay fluctuation generated in the network.

  The timing for outputting the first packet is the earlier of the following conditions (A) or (B).

Condition (A) When the initial playback delay time has elapsed since the first packet was received at the receiver side Condition (B) When the buffer time amount stored in the receiver side buffer exceeded the initial playback delay time ( However, the amount of buffer time is the difference between the time count information given to the latest packet and the oldest packet stored in the receiver side buffer. (The time count information on the transmitter side is given.)
Here, the receiver side sets the delay time (delayed_time) as shown in the following equation (2) when the first packet is output.

“Delay time (delayed_time)” = “Time count information when the first packet is output” − “Time count information included in the first packet” (2)
The timing for outputting the second and subsequent packets is output when the current time count information (current_time) satisfies the condition of the following expression (3).

“Current time count information (current_time)” ≧ “time count information included in second and subsequent packets” + “delayed time (delayed_time)” Equation (3)
If the transmitter stores a certain amount of packets in the transmission buffer at the start of transmission / reception, a large amount of packets are temporarily transmitted / received when transmission / reception starts, so the condition (B) is satisfied first. . Otherwise, the condition (A) is often satisfied first.

If the condition of Expression (3) is already satisfied, the packet is output immediately.
However, care must be taken when comparing the time count information. This is because the time count information is an unsigned 32-bit integer and is a numerical value that cycles through 0 to 2 ^ 32.

FIG. 6 is a diagram for explaining the comparison of the numerical values that circulate such as time count information.
As shown in FIG. 6A, the magnitude comparison of the time count information is not a simple comparison, but must be compared so that it is determined to be larger as it goes clockwise. Specifically, the size comparison may be performed using a code as shown in FIG. Also in the following description, it is assumed that a code as shown in FIG. 6B is used to compare the time count information (time count difference).

  Returning to FIG. 5, the packet transmission delay time may not be stable for a while after the communication I / F unit 41 starts to receive a packet. If the packet transmission delay time is not stable, the subsequent frequency difference estimator 45 cannot accurately obtain the frequency difference. In such a case, the received packet may be ignored for a predetermined time (for example, 0.5 seconds). Alternatively, it is ignored until a predetermined number of packets (for example, 150 packets) is received after the reception of the packets is started. Alternatively, it may be ignored until the packet transmission delay time is stabilized after the start of packet reception. Here, “packet transmission delay time is stable” means, for example, that the standard deviation of the N most recent packet transmission delay times is calculated, and if it is equal to or less than a predetermined value, it is determined that the packet transmission delay time is stable.

  The time count generation unit 46 generates time count information based on the oscillator 33 and the clock control amount. The clock control amount is a parameter that adjusts the progress of the time count information.

  Assuming that the count-up frequency is 1 MHz and the clock control amount is set to X [ppm], the time count information is counted up 1 million + X times per second.

  Here, when the clock control amount is set to plus, the time count information advances faster. Further, when the clock control amount is set to minus, the time count information advances slowly.

  The time count information is counted up by dividing the clock of the oscillator 33. For example, when the oscillation frequency of the oscillator 33 is 33 MHz and the clock control amount is X [ppm], the frequency division value may be set as the right side of the following equation (4).

1/33 × (1 + X × 10 ^ (− 6)) ≈30303 / (999999−X) (4)
Note that the frequency division value is expressed as a rational number. The frequency division value of n / d means that the time count information is counted up at a rate of n every d clock cycles of the oscillator 33.

  As described above, the time count generation unit 46 adjusts the progress of the time count information using the clock control amount as an argument, and generates time count information.

  The selection unit 50 selectively selects either the clock control amount from the frequency difference estimation unit 45 or the clock control amount from the time count delay determination unit 48 according to the control signal from the accuracy determination unit 49. To give.

  The accuracy determination unit 49 gives the selection unit 50 the clock control amount from the frequency difference estimation unit 45 in the transient state and the clock control amount from the time count delay determination unit 48 in the steady state. Send a control signal. The transition from the transient state to the steady state and from the steady state to the transient state will be described later.

  The time count difference calculation unit 43 detects a difference between the time count information included in the packet and the time count information generated by the time count generation unit 46 at the time when the packet is received. The time count difference (deliver_time) is obtained by the following equation (5).

“Time count difference (deliver_time)” = “Time count information when received by receiver (received_time)” − “Time count information when transmitter transmits (transmit_time)” (5)
When the packet transmission time is significantly longer than the preceding and succeeding packets, the time count difference at that time becomes larger than the preceding and succeeding packets. The data filter 44 removes such data as invalid data. The reason for providing such a data filter is that the packet transmission time varies greatly.

FIG. 7 is a diagram illustrating an example of a histogram of packet transmission times in wireless transmission.
In FIG. 7, the horizontal axis represents packet transmission time, and the vertical axis represents frequency. As shown in FIG. 7, at first glance, it looks like a normal distribution, but it can be seen that the packet transmission time has a long tail in the + ∞ direction. In wireless transmission, the packet transmission time may exceed 100 ms, and it is not appropriate to assume an upper limit for the packet transmission time. This is true not only in wireless transmission but also in many network environments.

  If there is an abnormal value in the time count difference, the error becomes large when the frequency difference is estimated. Since the object of the present invention is to estimate the frequency difference with high accuracy in a short time, a data filter is provided.

  Returning to FIG. 5, the frequency difference estimator 45 estimates the difference in oscillation frequency generated between the oscillator 13 of the transmitter and the oscillator 33 of the receiver. Estimation is performed based on the time count difference removed by the data filter 44.

  Further, the frequency difference estimation unit 45 outputs a clock control amount to the time count generation unit 46. The default clock control amount at the stage where the frequency difference is not estimated is set to 0 [ppm]. The time count generation unit 46 adjusts how the time count information advances faster or slower depending on the clock control amount.

  FIG. 8 is a plot diagram of the time count difference obtained by the time count difference calculation unit 43.

  The time count difference will be described with reference to FIG. In FIG. 8, the horizontal axis represents the elapsed time [μs] from the start of data reception. The vertical axis represents the time count difference [μs].

  The time count information on the transmission side and the time count information on the reception side are counted up independently. When the transmitting side and the receiving side are each turned on or reset, they start counting up from zero. Since the timing at which the power is turned on and reset is different between the transmission side and the reception side every time, the difference value itself of the time count information is meaningless. However, the progress of the time count information difference is meaningful.

  As shown in FIG. 8, it can be seen that the time count difference tends to increase with the passage of time. This is due to the difference in oscillation frequency that occurs between the oscillator 13 of the transmitter and the oscillator 33 of the receiver.

  Whether it increases or decreases with the passage of time depends on the relationship between the oscillator 13 of the transmitter and the oscillator 33 of the receiver. That is, if the progress of the oscillator 33 of the receiver is faster than the oscillator 13 of the transmitter, it increases with time, and if the progress of the oscillator 33 of the receiver is slower than the oscillator 13 of the transmitter, the time is increased. Decreases with progress.

  FIG. 9 is a plot of the time count difference after invalid data is removed by the data filter.

  As shown in FIG. 9, the data filter 44 removes invalid data from the plot diagram as shown in FIG.

FIG. 10 is a flowchart of processing for detecting invalid data.
With reference to FIG. 10, a process in which the data filter 44 detects invalid data will be described. Each time the data filter 44 receives a packet, the packet receives time count information (transmit_time) at the time of transmission by the transmitter and time count information (received_time) at the time of reception by the receiver. As a routine to detect invalid data.

  First, in step S900, the data filter 44 determines whether the received packet is the top packet.

  If it is the first packet (YES in step S900), in step S902, the data filter 44 initializes static variables (first_transmit_time, min_deliver_time2). Specifically, the time count information (first_transmit_time) of the time at which the transmitter tries to transmit the first packet is set to zero. Here, the “first packet” means a packet received first after power-on or reset. Further, the corrected minimum value (min_deliver_time2) of the time count difference is set to + ∞. The “corrected time count difference” will be described in detail in step S906.

  Subsequently, in step S904, the time count information (transmit_time) at the time when the transmitter tries to transmit included in the received packet in the time count information (first_transmit_time) at the time when the transmitter tries to transmit the first packet. Is assigned.

  On the other hand, if it is not the top packet (NO in step S900), the corrected time count difference (deliver_time2) is calculated in step S906. The correction calculation of the time count difference performed here is performed for data determination as described below. The calculation is performed according to the following equation (6).

(Deliver_time2) = (received_time) − (transmit_time2) (6)
Here, (transmit_time2) is obtained by artificially increasing the time count information of the transmitter by +200 [ppm] earlier. A specific calculation formula is as shown in the following formula (7).

(Transmit_time2) = ((transmit_time)-(fisrt_transmit_time)) * (1 + 200e-6) + (fisrt_transmit_time) (7)
Here, the time count information of the transmitter is artificially increased by +200 [ppm] earlier, but this is an amount that exceeds the sum of the frequency errors assumed by the oscillators on the transmitter side and the receiver side. Set. Here, it is assumed that the accuracy of the oscillators on the transmitter side and the receiver side is less than 100 ppm. With this setting, the time count information on the receiver side advances more slowly than the time count information on the transmitter side.

  Further, a method of artificially delaying the time count information on the receiver side may be taken. With this setting, the time count information on the transmitter side advances faster than the time count information on the receiver side.

  Accordingly, it is estimated that the corrected time count difference decreases with the passage of time regardless of which method is used. You may change the quantity made to be pseudo-fast according to the precision of the oscillator used in a system.

  FIG. 11 is a diagram in which the corrected time count difference (deliver_time2) is plotted with respect to the data shown in FIG.

  As shown in FIG. 11, when the time count information of the transmitter is corrected by advancing the time count information of the transmitter in a pseudo manner and the corrected time count difference time (deliver_time2) is calculated, it decreases with the passage of time. I understand that.

  Returning to FIG. 10, in step S908, it is determined whether or not the corrected time count difference time (deliver_time2) calculated in step S906 is smaller than the minimum value (min_deliver_time2) of the corrected time count difference at the present time. To do.

  If it is equal to or smaller than the minimum value (YES in step S908), the corrected time count difference time (deliver_time2) calculated in step S906 is set to the minimum value (min_deliver_time2) of the corrected time count difference in step S910. Is assigned.

  Next, in step S912, it is determined that the received packet is valid data, and the process ends.

  On the other hand, if it is larger than the minimum value (NO in step S908), it is determined in step S914 that the data is invalid, and the process ends.

  The data filter can be realized by the method as described above. As a method for realizing the data filter, there is the following method in addition to the above-described method.

  On the receiver side, it is divided every predetermined time (for example, 100 ms) or divided every predetermined number of packets (for example, 50 packets), and the minimum of the time count difference is obtained in each period. It is determined that the data is valid only when the time count difference is minimal, and it is determined that the data is invalid otherwise.

  Alternatively, on the receiver side, M is extracted from the smaller of the past N times of the time count difference (deliver_time), and the M is averaged (this is referred to as “moving lower average”). When a packet is received, if the time count difference (deliver_time) is within the range of the moving lower average ± X (X is a predetermined value), it is determined to be valid data, otherwise it is invalid Judged as data.

  Returning to FIG. 5, the frequency difference estimation unit 45 calculates the frequency difference based on the data determined to be valid by the data filter 44.

FIG. 12 is a flowchart of the process for calculating the frequency difference.
With reference to FIG. 12, the frequency difference estimation part 45 demonstrates the process which calculates the frequency difference of a transmitter / receiver. Each time the packet is received, the frequency difference estimation unit 45 includes time count information (transmit_time) at the time of transmission by the transmitter, and time count information (received_time) at the time of reception by the receiver. Is used as a parameter to call a routine that calculates the frequency difference. Here, the least square method is used as a method of calculating the frequency difference.

FIG. 13 is a diagram for explaining the least square method.
Here, the least square method will be described with reference to FIG. In FIG. 13, the horizontal axis is x, and the vertical axis is y.

The least square method is used to obtain a straight line y = ax + b (this is called a “regression line”) that best approximates n points (x _i , y _i ) (i = 1,..., N). . That is, in the least square method, the sum of squares of the difference (referred to as a residual) between each point (xi, yi) and the regression line y = ax + b expressed by the following equation (8) is minimized. In this method, each coefficient (in this case, a and b) is obtained.

  However, A, B, C, D, and E in the equation (8) are expressed by the following equation (9).

  In order to obtain each coefficient, specifically, the following equations (10) and (11) obtained by partial differentiation of the residual sum of squares S represented by equation (8) and substituting zero are obtained. calculate.

  Returning to FIG. 12, the process of calculating the frequency difference will be described in detail below according to the flowchart. Note that the frequency difference estimation unit 45 performs the following processing every time a packet is received.

  First, in step S1100, the time count difference calculation unit 43 calculates a time count difference (deliver_time) according to Equation (5).

  In step S1102, the frequency difference estimation unit 45 determines whether or not the received packet is the head packet.

  If it is the first packet (YES in step S1102), in step S1104, the frequency difference estimation unit 45 performs initial setting of static variables (first_transmit_time, first_deliver_time, SX, SY, SXX, SXY, SYY, CNT). Specifically, the value of each variable is set to zero. Here, the time count difference of the first packet is “first_deliver_time”. SX corresponds to variable E in equation (8). Similarly, SY corresponds to variable C, SXX corresponds to variable B, SXY corresponds to variable D, SYY corresponds to variable A, and CNT corresponds to n.

  Next, in step S1106, the time count information (transmit_time) at the time the transmitter tries to transmit is included in the received time count information (first_transmit_time) at the time when the transmitter tries to transmit the first packet. To do. Also, the time count difference (deliver_time) of the received packet is substituted for the time count difference (first_deliver_time) of the first packet.

  On the other hand, if it is not the leading packet (NO in step S1102), in step S1108, accuracy determination unit 49 determines whether the accuracy of the frequency difference estimated by frequency difference estimation unit 45 is a predetermined accuracy (the accuracy is sufficient). It is determined whether there is. This determination method will be described later.

  If the estimation of the frequency difference is sufficient (YES in step S1108), in step S1110, frequency estimation unit 45 calculates the frequency difference and ends the process. The frequency difference (A) is calculated corresponding to the equation (10). Specifically, the following equation (12) is calculated.

Frequency difference (A) = (CNT × SXY−SY × SX) / (CNT × SXX−SX × SX) (12)
On the other hand, if the estimation of the frequency difference is not sufficient (NO in step S1108), in step S1112, the frequency difference estimation unit 45 determines whether the time count difference (deliver_time) obtained in step S1102 is valid data. judge.

  Whether or not the data is valid is determined by the data filter 44 according to the flowchart shown in FIG.

  If the data is valid (NO in step S1112), in step S1114, the frequency difference estimation unit 45 performs a preparatory calculation for the least squares method and ends the process. Note that the preparation calculation is a calculation corresponding to the equation (9). Specifically, “(transmit_time) − (first_transmit_time)” is X, and “(deliver_time) − (first_deliver_time)” is Y. Also, SX + X is assigned to SX, SY + Y is assigned to SY, SXX + X × X is assigned to SXX, SYY + Y × Y is assigned to SYY, and CNT + 1 is assigned to CNT.

  On the other hand, if the data is not valid (NO in step S1112), the process ends.

  As described above, the processing for calculating the frequency difference is performed. Further, the frequency difference estimation unit 45 determines the clock control amount based on the frequency difference calculated in step S1110.

  The time count generation unit 46 adjusts the progress of the time count information using the clock control amount as an argument. Once the frequency difference is calculated in step S1110, the process for calculating the frequency difference is no longer performed. The transient state ends and transitions to a steady state.

  Next, a method will be described in which, in step S1108, the accuracy determination unit 49 determines whether the accuracy of the estimated frequency difference is a predetermined accuracy (the estimation is sufficient).

  The first method determines that the estimation of the frequency difference is sufficient when a predetermined time (for example, 5 seconds) elapses after the first packet is received.

  In the second method, if a predetermined number of packets (for example, 1500 packets) is received after receiving the head packet, it is determined that the estimation of the frequency difference is sufficient.

  In the third method, if a predetermined number (for example, 50) of effective data differences (corresponding to CNT in step S1114) is collected, it is determined that the estimation of the frequency difference is sufficient.

  In the fourth method, every time a predetermined time elapses or every time a predetermined number of packets are received, the coefficient a is obtained using the equation (10), and the past N maximum and minimum of the calculation result are obtained. Is determined to be less than a predetermined value (for example, 10 [ppm]), it is determined that the estimation of the frequency difference is sufficient.

In the fifth method, every time valid data is obtained by receiving a packet, the residual sum of squares S shown in Expression (8) is calculated, and the calculation result is equal to or less than a predetermined value. If it is determined, it is determined that the estimation of the frequency difference is sufficient. This is because the value of the residual sum of squares S becomes smaller when each data is better fitted to the regression line. If the value of the residual sum of squares S is small, each point (x _i , y _i ) in FIG. 13 is located closer to the regression line, so that the slope can be estimated correctly. In the fifth method, since it is necessary to keep the number of data constant, only N pieces of valid data immediately before reception are prepared and calculated.

  Alternatively, when the number of data is kept constant, the oldest data is not deleted, but a regression line at the time when N pieces of data are obtained is temporarily calculated, and the data that is the farthest point from the regression line is deleted. Then, only N pieces of data may be left.

  In addition, a correlation coefficient, a determination coefficient (R-square), or the like may be used as an index indicating the degree of fit of the regression line.

  If it is determined that the accuracy of the frequency difference is sufficient as described above, the accuracy determination unit 49 gives the clock control amount determined from the frequency difference with sufficient accuracy to the time count generation unit 46, and then the time A control signal is sent to the selection unit 50 so as to give the clock control amount from the count slow speed determination unit 48.

  When the process is terminated in step S1110, the accuracy determination unit 49 may notify the transmitter side that the estimation of the frequency difference is sufficient via the communication I / F unit 41. As a result, the transmitter side performs transmission with a method with less variation in transmission delay time when the receiver side is in a transient state, and transmits with a method with good transmission efficiency when the receiver side is in a steady state. It becomes possible to do.

  If the transmitter side performs transmission by a method with less variation in transmission delay time, there is an advantage that it is easy to correctly calculate the estimation of the frequency difference by the receiver.

FIG. 14 is a diagram illustrating an example of a detailed configuration of the transmission unit 12.
With reference to FIG. 14, the structure of the transmission part 12 which can change a transmission method by the notification by the side of a receiver as mentioned above is demonstrated.

  The transmission unit 12 includes a packet generation unit 51, a transmission buffer unit 52, a transmission time addition unit 53, a communication I / F unit 54, a transmission method selection unit 55, and a time count generation unit 56.

  The packet generation unit 51 adds time count information based on the time count generation unit 56 to the MPEG packet input from the MPEG encoder, and generates a packet.

The transmission buffer unit 52 temporarily stores packets.
The transmission time giving unit 53 takes out the packet from the transmission buffer unit 52 and sends the packet to the communication I / F unit 54. At this time, transmission time information is added to the packet.

The communication I / F unit 54 transmits the packet to the receiver side.
The transmission method selection unit 55 selects a method for transmitting a packet. For example, it is selected to transmit by a method with little variation in transmission delay time or to transmit by a method with good transmission efficiency. The transmission method selection unit 55 may determine the selection based on the determination of only the transmitter 10 or may be determined by receiving a packet from the receiver 30.

The time count generation unit 56 generates time count information based on the oscillator 13.
With the above procedure, the frequency difference between the oscillators of the transmitter 10 and the receiver 30 can be accurately obtained in a short time. At this point, the transient period ends.

After the period of the transient state ends, dejittering control in the steady state is performed.
The de-jittering control in the steady state is aimed at making the change of the clock control amount as gentle as possible. Desirably, it is controlled gently until the PCR drift rate described in Non-Patent Document 3 is satisfied. If it is a consumer device, it is not always necessary to satisfy the PCR drift rate, but the target drift rate is determined in advance. Note that it is not always necessary to satisfy the PCR drift rate because the change in the oscillation frequency due to the temperature change of a crystal oscillator component generally used in consumer devices is the PCR drift described in Non-Patent Document 3. One reason is that it is greater than the rate.

  The de-jittering control in the steady state includes a method of controlling the “packet relative transmission time” to be constant, a method of controlling the “total amount of buffer time of the transceiver” to be constant, There is a method of controlling so that the “buffer time amount” becomes constant. Hereinafter, each method will be described with reference to FIG.

[Method to control packet relative transmission time to be constant]
The “packet relative transmission time” here is the same value as the above-mentioned time count difference ((deliver_time) = (received_time) − (transmit_time)). It is assumed that the time count information of the transmitter is included in the packet payload.

First, the time count difference calculation unit 43 obtains a packet relative transmission time.
Then, the time count difference minimum value detection unit 47 obtains a minimum value of “packet relative transmission time” for each predetermined period. For example, the minimum value is obtained every 6 seconds. The determination method in which the data filter 44 is effective when the time count difference becomes minimum at a predetermined time in the transient state has been described above. However, in the steady state, the time count difference minimum value detection unit 47 determines the minimum value. The range of the “predetermined period” to be obtained is longer than the “predetermined time”. This is to perform a gentle synchronization control in a steady state.

  The minimum value of the “packet relative transmission time” increases in the direction in which the clock on the receiver side advances faster than the transmitter side. If the way of the clock on the receiver side is slower than that on the transmitter side, it will go in a decreasing direction.

  The time count slow speed determination unit 48 determines whether the clock progress on the receiver side is slow or fast by looking at the change in the minimum value of the “packet relative transmission time”. In accordance with {increase / decrease} in the minimum value of the “packet relative transmission time”, the receiver advances the clock in the range of a predetermined drift rate. It is determined in advance how much the clock control amount is changed. For example, it is changed by ± 1/9 [ppm] every 6 seconds.

  It is preferable that the amount of change in the clock control amount at a predetermined time is designed so that it can be adjusted by a parameter. In addition, the time count slow speed determination unit 48 does not regard a difference of a predetermined value or less (for example, about 10 μsec) as a significant difference in the change in the minimum value of the “packet relative transmission time”, and the clock of the receiver side You may keep the way you go.

[Method of controlling the total buffer time of the transceiver to be constant]
Also, by observing the amount of buffer time, it is possible to determine whether the clock on the receiver side is slow or fast.

  Each time a receiver receives a packet, it calculates the total amount of buffer time of the transceiver. This is performed in a portion corresponding to the time count difference calculation unit 43.

  Information on the buffer time amount of the transmitter is assumed to be included in the payload of the packet. This is performed in a portion corresponding to the transmission time giving unit 53 in FIG.

  Returning to FIG. 5, the buffer time amount of the receiver acquires the time amount of the packet stored in the de-jittering buffer 42 when the packet is received.

  The buffer time amount of the receiver decreases as the packet transmission time increases. This is because the amount of buffer time on the transmitter side does not change as information included in the packet, but when the packet transmission time increases, the receiver side receives the packet with a delay. During this time, packets continue to be output from the de-jittering buffer on the receiver side, so the amount of buffer time is reduced. Therefore, it is important to look at the maximum value for the buffer time amount.

  The receiver obtains the maximum value of “the total amount of buffer time of the transceiver” every predetermined time. This is performed in a portion corresponding to the time count difference minimum value detection unit 47.

  The maximum value of the “total amount of buffer time of the transmitter / receiver” tends to decrease if the clock progress on the receiver side is faster than that on the transmitter side. If the way of the clock on the receiver side is slower than that on the transmitter side, the direction is increased. The change in the maximum value of the “total amount of buffer time of the transceiver” is determined to determine whether the clock advance on the receiver side is slow or fast. This is performed in a portion corresponding to the time count delay determination unit 48.

  In accordance with {increase / decrease} in the maximum value, the clock advance on the receiver side is {increased / decreased} within a predetermined drift rate range.

[Method to control the buffer time of the receiver to be constant]
Further, when information on the buffer time amount of the transmitter cannot be obtained, the determination may be made based only on the buffer time amount of the receiver.

  Unless there is a bursty transmission failure in the network 20, the buffer time amount of the transmitter is considered to be zero or close to zero. If even one packet is in such a state during a predetermined time, even if information on the buffer time amount of the transmitter cannot be obtained, it can be determined only by the buffer time amount of the receiver.

  The receiver obtains a maximum value of “the amount of buffer time of the receiver” every predetermined time. The change in the maximum value of the “receiver buffer time amount” is observed to determine whether the clock on the receiver side is slow or fast. In accordance with {increase / decrease} in the maximum value, the clock advance on the receiver side is {increased / decreased} within a predetermined drift rate range.

  By using any of these methods, the de-jittering control can be continued while keeping the target drift rate.

The method of de-jittering control in the steady state has been described above.
In addition, a transition from a steady state to a transient state may occur. When the reception of the packet is interrupted and the de-jittering buffer 42 is emptied and a predetermined time elapses, it is considered that the stream transmission has been completed, and a transition is made.

Even if the power is turned on or reset, the steady state transitions to the transient state.
When shifting from the steady state to the transient state, the selection unit 50 gives the clock count from the frequency difference estimation unit 45 to the time count generation unit 46.

  In addition, you may provide the transmission means which transmits a packet from a receiver to a transmitter when it transfers to a transient state. As a result, the transmitter side can perform transmission using a method with little variation in transmission delay time. By transmitting the packet, the transmission method of the transmitter can be explicitly instructed from the receiver side.

  In the video transmission system according to the present invention, whether or not video is normally displayed in a transient state is not guaranteed depending on the clock accuracy of the parts. Due to the above-described MPEGX VCXO problem, video may or may not be displayed normally depending on the set. Therefore, in a transient state, the transmitter may transmit a dummy packet, and the receiver may discard the received dummy packet. By controlling in this way, it is possible to eliminate differences in operation due to individual differences in the set.

  Further, the configuration of the dummy packet is not limited to the packet format shown in FIG. 3 and may be a packet of only transmission time information. Since the packet length can be set short, it can be expected that variations in packet transmission time will be reduced.

  FIG. 15 is a diagram illustrating simulation results with and without the data filter 44.

  With reference to FIG. 15, the difference of the convergence result with and without the data filter will be described. In FIG. 15, the horizontal axis represents the simulation elapsed time [seconds]. The vertical axis represents the absolute value [ppm] of the error between the frequency difference estimated using the least square method and the true value. The closer to 0 ppm, the better the estimation.

  Further, in FIG. 15, the simulation is performed 2000 times, and the next worst value is shown except for 10 times with poor convergence accuracy. Therefore, the result of FIG. 15 can be expected with a probability of 99.5%. The graph 140 shows the case where the data filter 44 is not provided, and the graph 142 shows the case where the data filter 44 is provided.

  Here, the simulation conditions will be described in detail. A Pareto distribution is used as a variation in the packet transmission delay time. The shortest packet transmission delay time is 50 μsec, and the parameters are set so that 99.7% is within 10 ms.

  As shown in FIG. 15, when there is no data filter 44, it converges only to several ppm even after 10 seconds or more. On the other hand, it can be seen that when the data filter 44 is present, it converges to about ± 1 ppm in 5 seconds.

  The simulation result of FIG. 15 shows that the time until the amount of clock control in dejittering almost converges (can be controlled while satisfying a predetermined drift rate) can be set short by the presence of the data filter 44.

  As described above, according to the video transmission system according to the present embodiment, in clock control in dejittering, control is performed while satisfying a predetermined drift rate, and the clock control amount for dejittering is almost converged and predetermined. It is possible to shorten the time until control can be performed while satisfying the drift rate.

[Embodiment 2]
In the high-speed de-jittering control in the transient state in the first embodiment, the time count difference between the transmitter side and the receiver side is obtained in order to obtain the difference in oscillation frequency generated between the transmitter and the receiver. In the present embodiment, a method of looking at the total buffer time amount of packets stored in the transmitter and the receiver, which is different from the method in the first embodiment, will be described.

  The total elapsed time of the buffer time amount has a form as if the graph shown in FIG. Since the same (upside down) inclination as the time lapse of the time count difference is obtained, the difference in oscillation frequency generated between the transmitter and the receiver can be obtained.

  The second embodiment is a modification in which the oscillation frequency difference is obtained not by the “time count difference” in the first embodiment but by the “total amount of buffer time of the transceiver”.

  In the present embodiment, the time count difference calculation unit 43 shown in FIG. 5 is changed so as to calculate the total buffer time amount of packets stored in the transmitter and the receiver. The total buffer time amount is obtained by the following equation (13).

“Total buffer time amount (buf_amount)” = “Buffer time amount stored in transmitter (tx_queue)” + “Buffer time amount stored in receiver (rx_queue)” (13)
Note that the buffer time amount (tx_queue) stored in the transmitter is obtained from the packet. The TXQ field 230 shown in FIG. 3 is changed to the buffer time amount stored in the transmitter at the time of attempting to transmit the packet.

  The amount of buffer time stored in the transmitter is obtained by calculating the difference between the time count information of the latest packet and the time count information of the oldest packet among the packets stored in the transmission buffer according to the following equation (14). can get.

“Amount of buffer time stored in transmitter (tx_queue)” = “time count information of latest packet (tx_newest_tts)” − “time count information of oldest packet (tx_oldest_tts)” (14)
The amount of buffer time stored in the receiver is the difference between the time count information of the latest packet and the time count information of the oldest packet among the packets stored in the de-jittering buffer 42. It is obtained by asking according to.

“Amount of buffer time stored in receiver (rx_queue)” = “time count information of latest packet (rx_newest_tts)” − “time count information of oldest packet (rx_oldest_tts)” (15)
The data filter 44 is changed so as to remove the abnormal value of “total amount of buffer time (buf_amount)”. The algorithm of the data filter 44 can use the method presented in the first embodiment as it is only by considering the inversion of the sign (eg, updating the minimum value → changing the maximum value to update). The frequency difference estimator 45 can also use the method presented in the first embodiment as it is only by considering the inversion of the sign. The subsequent processing is the same as in the first embodiment.

  In the following, the total time lapse graph of the buffer time amount shows the reason why the time lapse graph of the time count difference is just upside down.

  “Time lag from input to encoder (time_to_send)” obtained from the following equation (16) is added to equation (15) to obtain “buffer time amount (tx_queue) stored in transmitter” May be.

“Time lag from input from encoder to transmission (time_to_send)” = “time count information at time when transmitter tries to transmit (transmit_time)” − “time count information of latest packet (tx_newest_tts)” (16)
Note that adding equation (16) to the buffer time amount (tx_queue) stored in the transmitter is based on the following concept.

  There is an idea that the meaning of the amount of buffer time is substantially different between a case where the transmitter transmits a packet immediately after the packet is input from the encoder and a case where the packet is transmitted after a while.

  For example, assuming that packets are input from the encoder at intervals of 150 μs, the previous packet is input 50 μs ago. Then, since the next packet should be input after 100 μs, the amount of buffer time stored in the transmitter at that time increases by 150 μs. The idea is that instead of increasing the buffer time amount by 150 μs after 100 μs, the buffer time amount is increased by 50 μs at the present time.

  When packets are input from the encoder at a constant interval (for example, 150 μsec), the value of Expression (18) is very small (for example, 0 μsec to 150 μsec).

  Further, by adding the “time until the oldest packet is output (time_to_output)” obtained by the following equation (17) to the equation (15) for obtaining the buffer time amount (rx_queue) stored in the receiver Also good.

“Time until the oldest packet is output (time_to_output)” = “Time when the oldest packet is scheduled to be output (expected_sph)” − “Time count information when the receiver receives the packet (received_time)” Formula (17)
The time when the oldest packet is scheduled to be output can be calculated by the following equation (18).

Time when the earliest packet is scheduled to be output (expected_sph) = “time count information of the oldest packet (rx_oldest_tts)” + “delay time (delayed_time)” (18)
Adding equation (17) to the amount of buffer time (rx_queue) stored in the receiver is based on the following concept.

  There is an idea that the meaning of the amount of buffer time is substantially different between when the receiver receives a packet immediately after outputting the oldest packet and when the receiver receives the packet after a while.

  For example, assuming that packets are input from the encoder at intervals of 150 μs, the oldest packet is scheduled to be output in 50 μs when the receiver receives the packets. Then, even if 50 μs elapses, the buffer amount stored in the receiver does not change at all, so the idea is to add 50 μs of that amount to the buffer time amount (rx_queue) stored in the receiver.

  When packets are input from the encoder at regular intervals (eg, 150 μsec), the value of Equation (8) is very small (eg, 0 μsec to 150 μsec).

  The oldest packet in the transmitter is a packet that is about to be transmitted. The latest packet in the receiver is a packet just received. Therefore, “the oldest packet time count information (tx_oldest_tts)” at the transmitter is equal to “the latest packet time count information (rx_newest_tts)” at the receiver.

  In summary, the total buffer time amount can also be obtained by the following equation (19).

“Total amount of buffer time (buf_amount)” = “Time count information when the transmitter tries to transmit (transmit_time)” − “Time count information when the receiver receives the packet (received_time)” + “Delay time (Delayed_time) "... Formula (19)
Since the delay time (delayed_time) is a fixed time, except for this, the total buffer time amount is merely a sign-inverted time count difference (deliver_time). From the above, it can be seen that the total time lapse graph of the buffer time amount is obtained by vertically inverting the time lapse graph of the time count difference. In the second embodiment, the first embodiment is changed from “time count difference” to “total amount of buffer time of transceiver”, and a time count difference calculation unit 43, a data filter 44, and a frequency difference estimation unit 45 are used. Is a change.

[Embodiment 3]
Further, the high-speed de-jittering control in the transient state of the second embodiment can be controlled only by “the buffer time amount of the receiver”.

  The transmission apparatus according to the present embodiment can be implemented even when the packet does not include information on the buffer time amount of the transmitter. The buffer time amount of the transmitter is regarded as zero, and the rest is the same as in the second embodiment.

  The present invention is not limited to the MPEG2-TS video transmission system, and can be applied to all network transmissions of streaming media (video, audio, audio, etc.). Specific services include VoIP, telephony, remote conference, streaming video, Webcast, VoD (video on demand), IP broadcasting, and the like.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is the figure which showed the time passage of the clock control amount of dejittering. It is a figure which shows the network video transmission system which concerns on this Embodiment. It is a figure which shows an example of the format of a packet. It is a figure which shows the state transition of the receiver 30 which concerns on this Embodiment. 3 is a diagram illustrating a detailed configuration of a reception unit 31. FIG. It is a figure for demonstrating magnitude comparison of the numerical value to circulate, such as time count information. It is a figure which shows an example of the histogram of the packet transmission time in radio | wireless transmission. FIG. 7 is a plot diagram of time count differences obtained by a time count difference calculation unit 43. It is a plot figure of the time count difference after invalid data are removed by the data filter. It is a flowchart about the process which detects invalid data. It is the figure which plotted the time count difference (deliver_time2) corrected with respect to the data shown in FIG. It is a flowchart about the process which calculates a frequency difference. It is a figure for demonstrating the least squares method. 4 is a diagram illustrating an example of a detailed configuration of a transmission unit 12. FIG. It is a figure which shows the simulation result with and without the data filter 44. It is the block diagram which showed the typical example of the video transmission system by MPEG2-TS. It is the block diagram which showed the structure of the general PLL. It is a figure which shows the outline of the video transmission system described in the nonpatent literature 2. FIG. It is the figure which showed the relationship between the data storage amount (buffer time amount) and the clock control amount in patent document 3 or patent document 4. It is a figure for demonstrating the conditions for an image | video to be displayed. It is a figure which shows the time change of a clock control amount.

Explanation of symbols

  10 transmitter, 11 MPEG encoder, 12 transmitter, 13 oscillator, 14 oscillator, 20 network, 30 receiver, 31 receiver, 32 MPEG decoder, 33 oscillator, 34 variable frequency oscillator, 41 communication I / F unit, 42 Jittering buffer, 43 Time count difference calculation unit, 44 Data filter, 45 Frequency difference estimation unit, 46 Time count generation unit, 47 Time count difference minimum value detection unit, 48 Time count slow speed determination unit, 49 Accuracy determination unit, 50 selection Section, 51 packet generation section, 52 transmission buffer section, 53 transmission time assignment section, 54 communication I / F section, 55 transmission method selection section, 56 time count generation section, 100 network video transmission system, 1200 transmitter, 1202 MPEG2 encoder 1204 oscillator, 120 Transmit buffer, 1210 receiver, 1212 receive buffer, 1214 PLL, 1216 MPEG2 decoder, 1302 internal counter, 1304 subtractor, 1306 low pass filter, 1308 voltage controlled oscillator, 1400 transmitter, 1402 clock, 1404 encoder, 1410 receiver, 1412 Decoder, 1414 PLL, 1416 de-jittering buffer, 1418 controller, 1600 MPEG2 encoder, 1601 oscillator, 1602 transmitter, 1603 oscillator, 1604 network, 1606 receiver, 1607 oscillator, 1608 MPEG2 decoder, 1609 VCXO.

Claims (26)

A receiving device for data communication with a transmitting device connected to a network,
A time count generation means for generating first time count information as a reference clock on the receiving device side;
Receiving means for receiving a packet from the transmitting device;
Based on the second time count information included in the packet from the transmission device and the first time count information generated by the time count generation means when the reception means receives the packet, the time A time count difference calculating means for calculating the count difference;
A data filter for removing an abnormal value of the time count difference;
A receiving apparatus comprising: frequency difference estimating means for calculating a frequency difference from a reference clock on the transmitting apparatus side from information on the time count difference that has passed through the data filter. The frequency difference estimation means determines a clock control amount based on the calculated frequency difference,
2. The reception according to claim 1, further comprising time count control means for controlling how the first time count information generated by the time count generation unit proceeds according to a clock control amount from the frequency difference estimation means. apparatus.   The data filter calculates a corrected time count difference based on the first time count information and the third time count information obtained by simulatingly speeding up the second time count information. The receiving apparatus according to claim 1, wherein the time count difference corresponding to the correction time count difference that is larger than the minimum correction time count difference is removed as an abnormal value.   The data filter calculates a corrected time count difference based on the second time count information and fourth time count information obtained by artificially delaying the first time count information. The receiving apparatus according to claim 1, wherein the time count difference corresponding to the correction time count difference that is larger than the minimum correction time count difference is removed as an abnormal value.   The receiving apparatus according to claim 1, wherein the data filter obtains a minimum value for each predetermined time interval and removes the time count difference other than the minimum value as an abnormal value.   The frequency difference estimation means calculates the frequency difference by approximating the relationship between the time from the time when the reception means starts receiving the packet and the time count difference by a regression analysis by a straight line, and calculating the frequency difference. The receiving device according to claim 1.   The receiving apparatus according to claim 1, further comprising an accuracy determination unit for determining the accuracy of the frequency difference calculated by the frequency difference estimation unit.   The reception according to claim 7, wherein the accuracy determination unit determines that the accuracy of the frequency difference is the predetermined accuracy in response to elapse of a predetermined time from the time when the reception unit starts receiving the packet. apparatus.   The accuracy determining unit determines that the accuracy of the frequency difference is the predetermined accuracy in response to receiving a predetermined number of the packets from the time when the receiving unit starts receiving the packets. 7. The receiving device according to 7.   The reception according to claim 7, wherein the accuracy determination unit determines that the accuracy of the frequency difference is the predetermined accuracy in response to a predetermined number of time count differences having passed through the data filter. apparatus.   The accuracy determining means determines that the accuracy of the frequency difference is the predetermined accuracy when the difference between the maximum value and the minimum value of the frequency difference calculated before a predetermined timing is within a predetermined range. The receiving device according to claim 7.   The accuracy determination means is configured such that the accuracy of the frequency difference is the predetermined accuracy when a residual sum of squares calculated from the information of the time count difference and the approximated straight line is within a predetermined range. The receiving device according to claim 7, wherein the receiving device is determined. A steady state clock control amount determining means for determining a clock control amount so as to satisfy a predetermined drift rate condition;
A selection means for selectively giving either the clock control amount from the frequency difference estimation means or the clock control amount from the steady state clock control amount determination means to the time count control means;
In response to the determination by the accuracy determining unit that the accuracy of the frequency difference is a predetermined accuracy, the selecting unit is configured to replace the clock control amount from the frequency difference estimating unit with respect to the time count control unit. The receiving apparatus according to claim 7, wherein a clock control amount from said steady state clock control amount determination means is provided. The steady state clock control amount determination means includes:
A time count difference minimum value detecting means for detecting a minimum value of the time count difference in a predetermined period;
And a time count delay determination means for determining the clock control amount so that the advance of the reference clock is within a predetermined drift rate range based on the detected change in the minimum value. 13. The receiving device according to 13. A buffer for accumulating the received packets;
A first buffer time amount indicating a time range of time count information of packets accumulated in the buffer included in a packet from the transmission device; and a second time when the packet is accumulated in the buffer of the reception device. Buffer time amount calculating means for calculating a third buffer time amount obtained by summing the buffer time amounts of
The steady state clock control amount determination means includes:
A buffer time amount maximum value detecting means for detecting a maximum value of the third buffer time amount in a predetermined period;
And a time count delay determination means for determining the clock control amount based on the detected change in the maximum value so that the advance of the reference clock is within a predetermined drift rate. 13. The receiving device according to 13. A buffer for storing the packet;
The steady state clock control amount determination means includes:
A buffer time amount maximum value detecting means for detecting a maximum value of a fourth buffer time amount indicating a time range of time count information of packets accumulated in the buffer in a predetermined period;
And a time count delay determination means for determining the clock control amount based on the detected change in the maximum value so that the advance of the reference clock is within a predetermined drift rate. 13. The receiving device according to 13. A receiving device for data communication with a transmitting device connected to a network,
A time count generation means for generating first time count information as a reference clock on the receiving device side;
Receiving means for receiving a packet from the transmitting device;
Based on the second time count information included in the packet from the transmission device and the first time count information generated by the time count generation means when the reception means receives the packet, the time A time count difference calculating means for calculating the count difference;
From the information of the time count difference, a frequency difference estimation unit for calculating a frequency difference with a reference clock on the transmission device side and determining a clock control amount;
A receiving apparatus comprising: accuracy determining means for determining the accuracy of the frequency difference calculated by the frequency difference estimating means. The frequency difference estimation means determines a clock control amount based on the calculated frequency difference,
18. The reception according to claim 17, further comprising time count control means for controlling how the first time count information generated by the time count generation unit proceeds according to a clock control amount from the frequency difference estimation means. apparatus. A steady state clock control amount determining means for determining a clock control amount so as to satisfy a predetermined drift rate condition;
A selection means for selectively giving either the clock control amount from the frequency difference estimation means or the clock control amount from the steady state clock control amount determination means to the time count control means;
In response to the determination by the accuracy determining unit that the accuracy of the frequency difference is a predetermined accuracy, the selecting unit is configured to replace the clock control amount from the frequency difference estimating unit with respect to the time count control unit. 19. The receiving apparatus according to claim 18, wherein a clock control amount from said steady state clock control amount determination means is provided. A receiving device for data communication with a transmitting device connected to a network,
Receiving means for receiving a packet from the transmitting device;
A time count generation means for generating first time count information as a reference clock on the receiving device side;
Detecting means for detecting a control state of the reference clock;
A receiving device comprising: a transmitting means for notifying the transmitting device of the detected control state.   The receiving device according to claim 7 or 17, further comprising transmitting means for notifying the transmitting device that the accuracy determining unit determines that the accuracy of the frequency difference is the predetermined accuracy. A power input detecting means for detecting an input state of power to the receiving device;
The selection means gives a clock control amount from the frequency difference estimation means to the time count control means in response to the power input detection means detecting the input or reset of the power supply. 19. The receiving device according to 19.   The selection unit gives a clock control amount from the frequency difference estimation unit to the time count control unit in response to a determination that the reception unit has not received the packet from the transmission device for a predetermined time. The receiving device according to claim 13 or 19. The transmitting device transmits a dummy packet to the receiving device;
The receiving apparatus according to any one of claims 1 to 23, wherein the frequency difference estimation unit estimates the frequency difference based on a time count difference of the dummy packet. A receiving device for data communication with a transmitting device connected to a network,
A time count generation means for generating first time count information as a reference clock on the receiving device side;
Receiving means for receiving a packet from the transmitting device;
A buffer for accumulating the received packets;
A first buffer time amount indicating a time range of time count information of packets accumulated in the buffer included in a packet from the transmission device; and a second time when the packet is accumulated in the buffer of the reception device. A buffer time amount calculating means for calculating a third buffer time amount that is the sum of the buffer time amounts of
A data filter for removing an abnormal value of the third buffer time amount;
A receiving apparatus comprising: frequency difference estimating means for calculating a frequency difference from a reference clock on the transmitting apparatus side from information on the third buffer time amount that has passed through the data filter. A clock synchronization method for data communication with a transmission device connected to a network,
Generating first time count information as a reference clock on the receiver side;
Receiving a packet from the transmitting device;
A time count difference is calculated based on second time count information included in the packet from the transmission device and first time count information generated when the packet is received in the receiving step. Steps,
Removing an abnormal value of the time count difference;
Calculating a frequency difference with a reference clock on the transmission device side from information on the time count difference from which the abnormal value has been removed.

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