JPH08307863A - Transmission reception synchronization method for video coding information - Google Patents

Abstract

PURPOSE: To attain video image communication keeping real time performance by obtaining a time according to a prescribed method and using decoding time information as current time when a receiver side arrival time of the decoding time information is a time having already elapsed. CONSTITUTION: When a delay fluctuation is small, changeover switches 301, 302 are thrown to the position (a), and when the delay fluctuation is large, the changeover switches 301, 302 are thrown to the position (b). When the changeover switches are thrown to the position (b), a value PCR being an initial value is used for an initial value of a counter and the succeeding PCR is not in use. Furthermore, a receiver side system clock VCO is set to a clock with a higher frequency than that of a sender side clock signal. Then a sender side system clock and its time are reproduced by a receiver side on the basis of the sender side time information and when decoding time information is coincident, the receiver side decodes the video image. Furthermore, when the receiver side arrival time of the decoding time information is a time having elapsed already, the decoding time information is set as a current time and the video image is decoded.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to transmission / reception of encoded video information, and more particularly to a method of transmitting / receiving encoded video information.

[0002]

2. Description of the Related Art MPEG is a technique to which the present invention is applied.
2 is known. In MPEG2, time information PCR (Progr
amClock Reference) and decoding time information DTS (Decoding Time Stamp) indicating the time to decode the received video coding information are added to the video coding information and transmitted.

A method similar to that of PLL (Phase Lock Loop) may be adopted as a method of realizing transmission / reception synchronization by using PCR. The simplest example is shown in FIG. Various circuits may be inserted in a portion surrounded by a dotted line in FIG. 2 in order to suppress divergence and vibration of the receiving side system clock and accelerate convergence, but in the present invention, this circuit will be discussed. The explanation is omitted because it is not the purpose.

VCO for generating the system clock on the receiving side
(Variable Clock Oscilato
r) is synchronized with the PCR sent from the sender. The basic operation is as follows. 1. The PCR value received first is used as the counter initial value. 2. This counter is set to the system clock (VC
Count up with O). This counter is the time on the receiving side. 3. When the receiving system clock is different from the transmitting system clock, the value of the next received PCR and the counter is different. The difference between the two is Dn. 4. Considering that the difference Dn has occurred in the time between the two PCRs, the frequency of the VCO is changed by the amount corresponding to 1 / k of Dn. Return to 5.2. The value of the first DTS added to the video coded information is fetched into the comparator asynchronously with the above 1 to 5.
The time, that is, the counter value is compared with this DTS, and when the time reaches DTS, decoding is started.

In the above-mentioned 4, the difference Dn itself is set to 1 / k equivalent because the arrival time of the PCR includes delay fluctuations, so the difference Dn equivalent is fed back to the VCO as it is. This is to prevent a large jitter from occurring in the system clock on the receiving side. Further, in the above operation, in addition to the buffer originally required for decoding, a buffer for absorbing the deviation generated between the transmission side system clock and the reception side system clock is required. This is called a receive buffer.

PCR time interval, magnitude of delay fluctuation,
Depending on the value of k, the relationship between the transmission side system clock and the initial frequency of the reception side VCO, etc., the progress until the synchronization of the transmission side system clock and the reception side system clock VCO is various, and the reception side system. The clock may be faster or slower than the system clock on the transmitting side, but will eventually settle to an accuracy of up to 1 / k of the delay fluctuation. An example is shown in FIG.

The vertical axis of FIG. 3 represents the deviation of the system clock during transmission and reception. The difference between the area of the portion above the origin of the vertical axis and the area of the portion below the vertical axis up to a certain elapsed time is the time difference caused by the difference between the system clocks on the transmitting side and the receiving side. That is, when the area of the upper part is large, it means that the receiving side is behind the time of the transmitting side. When this occurs, the received video coded information is originally waited for decoding. You have to wait longer than you should. If the receive buffer is not sufficient, the receive buffer overflows and the video coded information is discarded, resulting in a significant deterioration in image quality. Further, it is known that even if a sufficient reception buffer is provided, the above-mentioned time lag may be 10 times or more the original delay fluctuation. On the other hand, if the area below is large and the receiver is ahead of the sender's time, the receive buffer underflows and the video must be in the buffer originally required for decoding. A situation occurs in which even encoded information is lost. In this case, when the video coding information with the DTS arrives, the time at which the video coding information should be decoded has already passed, and it is not determined how to handle this case.

[0008]

The conventional technique has three problems when there is a delay fluctuation larger than the one defined in the design. That is, firstly, if there is not enough receiving buffer in terms of hardware, overflow occurs and video coding information is discarded, which hinders video decoding, and secondly, there is sufficient receiving buffer. However, even if it is prepared, a delay of 10 times or more of the delay fluctuation may occur, which is not applicable to real-time communication. Thirdly, there is no established method for underflow.

An object of the present invention is to provide a transmission / reception synchronization method of video coded information that enables video communication with real-time performance without causing overflow of a reception buffer even when delay fluctuation is large. is there.

[0010]

According to the method for transmitting and receiving video coded information of the present invention, the time information counted by the system clock on the transmitting side and the decoding time information for decoding the video coded information are provided together with the video coded information. To the receiving side,
In a video coded information transmission / reception system that performs decoding on the receiving side based on this, if the delay fluctuation that occurs on the communication path used is within the allowable value, the receiving side uses the time information on the transmitting side to When the system clock and time on the transmitting side are reproduced, and when the reproduced time and the decoding time information match, decoding is performed on the receiving side. On the other hand, when the delay fluctuation caused in the communication path used exceeds the allowable value. , The time is obtained by using a clock having a frequency higher than that of the transmission side system clock as the reception side system clock, and when the arrival time of the reception side of certain decoding time information has already passed in time, the decoding time information is It is characterized by setting the current time.

[0011]

According to the transmission / reception synchronization method of video encoded information of the present invention, when the delay fluctuation occurring in the communication path is within the allowable value, the receiving side reproduces the system clock and time of the transmitting side, and the reproduced time and When the decoding time information matches, decoding is performed on the receiving side. On the other hand, when the delay fluctuation exceeds the allowable value, the time is calculated using the clock having a higher frequency than the transmitter system clock as the receiver system clock, the decoding time information and the arrival time are compared, and if the time has already passed, With the decoding time information as the current time,
Decrypt.

[0012]

FIG. 1 shows an embodiment of the present invention. The portion shown by the thick line in the figure is the portion of the present invention. If the delay fluctuation is small enough to withstand the prior art, the switching switch 3
01 and 302 fall to the side of a, which is the same as the prior art shown in FIG. On the other hand, if the delay fluctuation is large,
The changeover switches 301 and 302 fall to the side of b.

When falling to the side of b, the first PCR value is used as the initial value of the counter, and the subsequent PCR is not used. The VCO is set to a predetermined clock set value. This clock setting value is set to have a frequency obviously higher than that of the transmitting clock. For example, if the allowable error of the transmitting clock is 20 ppm on the soil, the clock setting value is a value obtained by adding the error precision of the VCO to 20 ppm.

Since the receiving side system clock has a higher frequency than the transmitting side system clock, the receiving buffer underflows and the receiving buffer becomes empty. In this case, the value of the DTS in the head of the receive buffer is DT
Since S <counter value, the decoding timing is missed. Also in this case, in the present invention, when DTS <counter value, the counter value is reset with the DTS value. As a result, in the conventional technique, the information that causes a decoding error with DTS <counter value also has DTS = counter value and is decoded.

For example, the system clock on the transmitting side is -20.
Even if the receiving side system clock is set to 10 ppm in ppm and there is a deviation of 60 ppm, it is 30 msec.
The shift (shift of one frame) occurs every 8.3 minutes as expressed by the following equation.

30 × 10 ⁻³ / 60 × 10 ⁻⁶ = 500 sec = 8.3 minutes That is, once every 8.3 minutes, the same video frame is repeatedly displayed twice due to lack of video information to be decoded. However, using only the conventional technique, in the case of a large delay fluctuation, the degree of deterioration of the image quality is smaller than that of the reception buffer being broken and the image being disturbed.

If the delay fluctuation is large or small, if the guaranteed value of the delay fluctuation is shown when the transmission channel is set as in the ATM network, the judgment may be made based on the value. Further, when the magnitude of the delay fluctuation is not known in advance, the mode may be switched by determining that the delay fluctuation is large due to overflow or underflow of the reception buffer.

[0018]

According to the present invention, when the delay fluctuation is small, the transmission and reception can be accurately synchronized by using the conventional technique. On the other hand, when the delay fluctuation is large,
There is an effect that the failure of the receiving buffer does not occur and the video communication can be performed in real time.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a transmission / reception synchronization method of video coded information according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a transmission / reception synchronization method of video encoded information according to the related art.

FIG. 3 is a diagram showing an example of progress of a synchronization state by the synchronization method of FIG.

Claims (1)

[Claims] 1. Along with video coding information, time information counted by a system clock on the sending side and decoding time information for decoding the video coding information are sent to the receiving side, and decoding on the receiving side is performed based on this. This is a method for synchronizing transmission / reception of video coded information, and if the delay fluctuation that occurs in the communication path used is within the allowable value, the receiving side determines the system clock and time of the transmitting side based on the time information of the transmitting side. If the reproduced time and the decoded time information match, the receiving side performs decoding.On the other hand, if the delay fluctuation that occurs in the communication path used exceeds the allowable value, the frequency of the system clock of the transmitting side is While obtaining the time using a high clock as the receiving side system clock, the receiving side arrival time of the decoding time information is
A method for transmitting / receiving synchronization of video coded information, wherein the decoding time information is the current time when the time has already passed.