CN104838615A - Signal synchronization system, node synchronization system, signal synchronization method, and node synchronization method - Google Patents

Signal synchronization system, node synchronization system, signal synchronization method, and node synchronization method Download PDF

Info

Publication number
CN104838615A
CN104838615A CN201280077569.7A CN201280077569A CN104838615A CN 104838615 A CN104838615 A CN 104838615A CN 201280077569 A CN201280077569 A CN 201280077569A CN 104838615 A CN104838615 A CN 104838615A
Authority
CN
China
Prior art keywords
reference signal
count value
synchronous
value
count
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201280077569.7A
Other languages
Chinese (zh)
Other versions
CN104838615B (en
Inventor
光井崇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Publication of CN104838615A publication Critical patent/CN104838615A/en
Application granted granted Critical
Publication of CN104838615B publication Critical patent/CN104838615B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0682—Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging

Abstract

The present invention discloses a signal synchronization system, a node synchronization system, a signal synchronization method, and a node synchronization method. A main module in the signal synchronization system performs counting and generates a first reference signal from the count value reaching a preset reference value. A sub-module performs counting, generates a second reference signal from the count value reaching a reference value, counts an interval at which a synchronization correction process is performed, and, after the count value reaches a correction processing interval value for the synchronization correction process to be performed, receives the first reference signal, whereupon the sub-module restarts and continues to count. Then, after a count value indicating an interval at which the synchronization correction process is performed reaches the correction processing interval value, the sub-module acquires a count value for generating the second reference signal and a count value restarted after receiving the first reference signal, and temporarily sets a value for offsetting the difference between the count value for generating the second reference signal and the count value restarted after receiving the first reference signal, the offsetting value being set as a reference value to the count value for generating the second reference signal.

Description

Signal synchronizing system, synchronisation of nodes system, signal synchronizing method and node synchronization method
Technical field
The present invention relates to the signal synchronizing system for making the signal of regulation synchronous, synchronisation of nodes system, signal synchronizing method and node synchronization method.
Background technology
In the past, in the program utilizing processor etc. to put rules into practice under such circumstances, for the extensive process of reply or the object such as speed up processing, scatteredload, there will be a known and utilize multiple processor to perform the multicomputer system of process.In such multicomputer system, in order to realize the synchronous of counter (timer) among multiple processors, make primary processor produce interrupt signal etc. to the counter from processor, realize the synchronous of counter from processor according to this interrupt signal.
In addition, in the industry networks such as existing factory control transmission system, each equipment of construction system needs to come up on the basis of guarantee real-time mutually to carry out jumbo exchanges data.Therefore, be equipped on the generation of the access request of the application program of each equipment in such as basis, when event ground is accessed mutually, network load depends on application program, thus likely cannot ensure real-time.
Therefore, there is following technology: virtual shared storage (common storage) is arranged to each equipment in the past, sent this node data in renewal timing (timing) to all nodes (station) on network.When using above-mentioned technology, each node received by upgrading its data, and visits for application program, thus realizes the data exchange ways that ensure that real-time.In addition, in the past, proposition had for when carrying out above-mentioned exchanges data, realized the method (for example, referring to patent documentation 1) of the effective broadcast communication (BROADCASTCOMMUNICATION) on network.
In patent documentation 1, use the built-in timer correction utilizing the TDMA Time Division Multiple Access mode of the built-in timer of each node and the slave node based on the synchronized frame from main controlled node simultaneously.In addition, in the method shown in patent documentation 1, be configured to the network utilizing bus or serial cable to be connected by transmission path.
Prior art document
Patent documentation
Patent documentation 1: Japanese Patent Laid-Open 2005-159754 publication
Summary of the invention
Invent technical problem to be solved
But, at above-mentioned primary processor and from the counter synchronisation correcting process of carrying out between processor etc., preferred primary processor directly (from hardware) makes the counter resets from processor.But because this counter is the counter of the operative norm as multiple routine processes of carrying out in inside, if therefore can optionally be rewritten by outside, then other process may have problems.In addition, when counter is built in from CPU (Central Processing Unit: central processing unit) of processor etc., directly cannot reset to the counter from processor from primary processor.Therefore, in the past, once send interrupt signal from primary processor to from processor, then receive this signal from processor, and utilize the software of regulation to carry out indirectly the reset processing of (from software) execution counter.
In above-mentioned situation, from processor after receiving interrupt signal from primary processor, until during performing the reset processing of this counter corresponding with this signal, be delayed the time due to overhead (overhead) etc.Therefore, in the past, even if carried out reset processing, primary processor and also still there is counter synchronisation error between processor.
In addition, for internodal counter synchronous between network with master slave relation, consider such as to reset the methods such as timer by receiving synchronized frame.But, same as described above, if reset to make timer via firmware after receiving synchronized frame, then can produce error due to time of delays such as this overheads in counter.
Therefore, for as the existing methodical internodal synchronous method utilizing synchronized frame, when utilizing the firmware of microcomputer to carry out the mensuration correction of the lock in time between main controlled node and each slave node, error can be produced due to the processing time of microcomputer.
Therefore, in order to suppress the impact on other process brought because of the rewriting of counter, consider following methods: count from the interrupt signal of processor being sent to from primary processor from hardware, based on from the difference between the counter in processor, adjust the counting target (fiducial value) from the counter of processor, thus realize synchronous with between processor of primary processor.
Counter due to primary processor is different from the electrical characteristic separately of the counter from processor, is therefore difficult to presumption primary processor and has how many deviations from counter between processor.Therefore, if carry out the synchronous correcting process of the fiducial value adjusting the above-mentioned counter from processor when each interrupt signal, then synchronous with between processor of primary processor can be guaranteed.But if carry out synchronous correcting process continually, then its processing load increases, and likely has an impact to other process that originally will perform.
The present invention is accomplished in view of foregoing, and its object is to provides a kind of signal synchronizing system, synchronisation of nodes system, signal synchronizing method and node synchronization method, can suppress processing load and make the signal of regulation synchronous accurately.
The technical scheme that technical solution problem adopts
In order to solve the problem, signal synchronizing system of the present invention comprises the primary module carrying out action according to the 1st reference signal, and according to the 2nd reference signal carry out action from module, and make the 2nd reference signal synchronous with the 1st reference signal, it is characterized in that, primary module comprises: the 1st reference signal generating section, 1st reference signal generating section is by counting, when count value reaches the fiducial value preset, generate the 1st reference signal, comprise from module: the 2nd reference signal generating section, 2nd reference signal generating section is by counting, when count value reaches fiducial value, generate the 2nd reference signal, gap count portion, this gap count portion counts the interval of carrying out synchronous correcting process, overhead count section, this overhead count section, after gap count portion count value reaches the correcting process spacing value carrying out synchronous correcting process, receives the 1st reference signal, thus restarts, and count, count value acquisition unit, this count value acquisition unit, after gap count portion count value reaches correcting process spacing value, obtains the count value of the 2nd reference signal generating section and the count value of overhead count section according to the reception of the 1st reference signal, and synchronous correction portion, the value of the difference between the count value of counteracting the 2nd reference signal generating section and the count value of overhead count section is temporarily set in the 2nd reference signal generating section as fiducial value by this synchronous correction portion.
In addition, the present invention also comprises the combination in any of inscape of the present invention, performance or inscape is applied to method, device, system, computer program, recording medium, data structure etc. and the technical scheme obtained.
Invention effect
According to the present invention, can the signal of regulation be made accurately synchronous while suppression processing load.
Accompanying drawing explanation
Fig. 1 is the figure of an example of the general configuration of the signal synchronizing system representing execution mode 1.
Fig. 2 is the figure of an example of the hardware configuration representing processor module.
Fig. 3 be for illustration of the synchronous correcting process example in execution mode 1 sequential chart (one of).
Fig. 4 is the sequential chart (two) for illustration of the synchronous correcting process example in execution mode 1.
Fig. 5 is the sequential chart (three) for illustration of the synchronous correcting process example in execution mode 1.
Fig. 6 is the figure of the example of the general sequence representing signal synchronizing method.
Fig. 7 is the figure of an example of the general configuration of the synchronisation of nodes system represented in execution mode 2.
Fig. 8 be for illustration of the synchronous correcting process example in execution mode 2 sequential chart (one of).
Fig. 9 is the sequential chart (two) for illustration of the synchronous correcting process example in execution mode 2.
Figure 10 is the sequential chart (three) for illustration of the synchronous correcting process example in execution mode 2.
Figure 11 is the figure of an example of notifying process for illustration of the propagation delay time in execution mode 2.
Figure 12 represents the figure employing an example of the general configuration of the network transmission system of the synchronisation of nodes system of main controlled node and slave node included in execution mode 2.
Figure 13 is the figure of the example of the general sequence representing node synchronization method.
Embodiment
Below, with reference to accompanying drawing, the preferred embodiment of the present invention is described in detail.The involved size shown in execution mode, material, other concrete numerical value etc. are only be easy to understand the present invention and the example enumerated, except situation about clearly representing, are all not limited to illustrated example.In addition, in this specification and accompanying drawing, about the key element with the identical function of essence, structure, omitting repeat specification by marking same label, in addition, illustrating without the omitting elements of direct relation with the present invention.
(about present embodiment)
In present embodiment, such as carry out between the such module with master slave relation of multiple processor module, the multiple nodes comprising a processor module at least respectively, device, substrate counter (timer) synchronous, the overhead value from module side is obtained for the interrupt signal (counter reset signal) coming autonomous module side.In addition, in the present embodiment, synchronous correcting process is carried out based on the overhead value obtained with the counter from module side.
But, if perform this synchronous correcting process continually, then processing load can increase, therefore in the present embodiment, the interval of carrying out synchronous correcting process is counted, comes termly (intermittently) by the correcting process spacing value of regulation and perform synchronous correcting process.
In addition, in the present embodiment, when the device with master slave relation is set to main controlled node and slave node, the time of delay (propagation delay time) on communication path is also taken into account and carries out synchronous correcting process.
Below, the preferred implementation of accompanying drawing to the signal synchronizing system in present embodiment and synchronisation of nodes system is utilized to be described.
(execution mode 1: signal synchronizing system)
Fig. 1 is the figure of an example of the general configuration of the signal synchronizing system representing execution mode 1.In signal synchronizing system 10 shown in Fig. 1, as an example, show between the multiple processor modules (being processor module 11a ~ 11c in the example of Fig. 1) as module, carry out an example of the multiprocessor of counter synchronisation.
Signal synchronizing system 10 shown in Fig. 1 has: multiple processor module 11a ~ 11c (being called as required below " processor module 11 "), transfer bus 12, I/O (input and output) module 13 (illustrating with 13a ~ 13d in figure), external equipment 14 (illustrating with 14a ~ 14d in Fig. 1) and compilation device 15.Herein, in the example of fig. 1, for convenience of description, processor module 11a is set to main processor modules, processor module 11b, 11c are set to from processor module, the primary structure of each processor module is described.Wherein, two such Fig. 1 are not limited to from the quantity etc. of processor module.
In addition, in present embodiment, be not limited to said structure, single processor module all has same structure, to make it both can become main processor modules 11a, can become again from processor 11b, 11c.In addition, each processor module 11 is connected by transfer bus 12.In addition, in execution mode 1, be set to and can not be delayed the time because of transfer bus 12.
Herein, main processor modules 11a has the 1st reference signal generating section 21, the 1st operational part 22 and storage part 23.In addition, in the example of fig. 1, the 1st reference signal generating section 21 is built in CPU described later, but is not limited thereto, and such as the 1st reference signal generating section 21 and CPU also can separate and form.In addition, above-mentioned " built-in " such as represents that each function part (the 1st reference signal generating section 21, the 1st operational part 22) in only CPU can conduct interviews to the 1st reference signal generating section 21.
In addition, from processor module 11b, 11c, there is the 2nd reference signal generating section 31, the 2nd operational part 32, gap count portion 33, overhead count section 34, count value acquisition unit 35, synchronous judging part 36, synchronous correction portion 37 and storage part 38.In addition, in the example of fig. 1, the 2nd reference signal generating section 31 is built in CPU, but is not limited thereto, and such as the 2nd reference signal generating section 31 and CPU also can separate and form.
1st reference signal generating section 21 by counting, fiducial value count value being reached preset, thus generate the 1st reference signal.In addition, the 1st reference signal generating section 21 plays the function of the counter (below as required also referred to as " timer ") of hardware.Periodically above-mentioned count value is counted based on fiducial value.In Fig. 1, represent the counter of above-mentioned hardware with dotted line.
1st operational part 22, according to the 1st reference signal generated by the 1st reference signal generating section 21, performs the application program etc. that (computing) is stored in the regulation in storage part 23.In addition, the 1st reference signal provides (transmission) extremely from processor module 11b, 11c as interrupt signal (counter reset signal) via transfer bus 12.
Storage part 23 is stored in the application program (SequenceProgram: sequential program) that the 1st operational part 22 carries out the regulation of computing.In addition, the application program that the 1st operational part 22 carries out the regulation of computing sends instruction to the I/O module 13a be such as connected with main processor modules 11a, and utilize the process that I/O module 13a controls external equipment 14a.Therefore, mainly store in storage part 23 for the program processed that puts rules into practice to the I/O module 13a, the external equipment 14a that are connected with present treatment device module 11a.
That is, main processor modules 11a generates the 1st reference signal in each specified period, 1st operational part 22 is by performing (computing) application program (sequential program) according to the 1st reference signal, the equipment of regulation is controlled, periodically performs this application program (sequential program).
Then, be described from processor module 11b, 11c, but due to identical from the structure of processor module 11b, 11c, therefore in the following description, utilize and be described from processor module 11b, omit the explanation from processor module 11c.
2nd reference signal generating section 31 counts, and the fiducial value that setting is identical with fiducial value set in above-mentioned 1st reference signal generating section 21, and by making count value reach fiducial value, thus generate the 2nd reference signal.In addition, the 2nd reference signal generating section 31 plays the function of the counter of hardware.Periodically above-mentioned count value is counted based on fiducial value.In addition, the 1st reference signal generating section 21 and the respective counter of the 2nd reference signal generating section 31 are self-operating counter (free-running counter), advance voluntarily.
2nd operational part 32, according to the 2nd reference signal generated by the 2nd reference signal generating section 31, performs the application program etc. that (computing) is stored in the regulation in storage part 38.
In addition, the 2nd reference signal generating section 31 is the counters that only can conduct interviews from the 2nd operational part 32 in such as CPU, and is built in CPU (the built-in counter of CPU).That is, the 2nd reference signal generating section 31 is cannot from outside counters carrying out hardware type reset such as main processor modules 11a.
In addition, the 1st reference signal (synchronizing datum signal) of the 2nd operational part 32 host processor module 11a in future receives as interrupt signal, starts synchronous correcting process described later.
Gap count portion 33 counts, and is preset with and carries out the suitable correcting process spacing value in the synchronous correcting process interval processed, and when count value reaches correcting process spacing value, generates the correcting process commencing signal representing this situation.
In addition, correcting process spacing value is set by following calculating.Such as, the main processor modules 11a machining accuracy in order to meet required by this signal synchronizing system allowed and be set to 10 μ s from the synchronous error between processor module 11b.In this situation, in present embodiment, to being calculate shortest time 1 ~ 5 μ s to synchronous error.Herein, if synchronous error being set to 1 more than μ s is due to also shorter than 1 μ s, then the frequency gets higher of synchronous correcting process, processing load increases, and synchronous error is set to 5 below μ s and considers the allowance relative to 10 μ s.
Now, main processor modules 11a and the frequency of the oscillator used from processor module 11b are set to 50MHz, vibration precision is set to 50ppm.Under this condition, the shortest time that synchronous error becomes 1 μ s be a clock time × number of oscillation that departs from of synchronous permissible error, that is, 20ns × ((1 μ s/20ns) × (1/50ppm))=20ms.Equally, synchronous error becomes the shortest time of 5 μ s is 100ms.Therefore, the value that obtains after being set to and converting 20ms ~ 100ms to count value of correction time spacing value.By being set in above-mentioned scope by correcting process spacing value, and intermittently perform synchronous correcting process, thus while suppression processing load, higher machining accuracy can be realized, improve the quality of production.
Overhead count section 34 counts, and after receiving correcting process commencing signal, that is, after the count value in gap count portion 33 reaches correcting process spacing value, measure and be received as starting point until perform the overhead value of synchronous correcting process with above-mentioned 1st reference signal.Specifically, the function of the counter (timer) of hardware that restarts after playing and receiving the 1st reference signal of overhead count section 34.
Because overhead count section 34 is the counters be made up of hardware, therefore direct 1st reference signal to be made a response, and synchronous correcting process was such as needing spended time before reading being ready to complete of count value.Overhead is for the required time before reading being ready to complete of this count value.In addition, overhead represent from occur certain event play actual execution for this event process (software) till time of delay, and in this example overhead be the starting point of restarting from overhead count section 34 to the actual time of carrying out synchronous correcting process, but to be not limited thereto.
Count value acquisition unit 35 is after receiving correcting process commencing signal, namely, after the count value in gap count portion 33 reaches correcting process spacing value, according to the reception of the 1st reference signal, obtain the actual count value of the 2nd reference signal generating section 31 and the count value of overhead count section 34 that perform the moment (start time) of synchronous correcting process.
Synchronous judging part 36, when the count value of the 2nd reference signal generating section 31 accessed by count value acquisition unit 35 is identical with the count value of overhead count section 34, is judged as that the 1st reference signal is synchronous with the 2nd reference signal.In addition, synchronous judging part 36, when the count value of the 2nd reference signal generating section 31 accessed by count value acquisition unit 35 is different from the count value of overhead count section 34, is judged as that above-mentioned 1st reference signal is asynchronous with the 2nd reference signal.
In addition, synchronous judging part 36 can carry out time conversion to the count value of the 2nd reference signal generating section 31 accessed by count value acquisition unit 35 and the count value of overhead count section 34, when both time is equal, be judged as synchronous, in addition, when both time is different, be judged as asynchronous.That is, in execution mode 1, manage throughout between device module 11, the unit interval of each clock of each counter may be unequal.Therefore, in this case, each count value is converted into the time, and utilizes the time after converting to carry out synchronously/nonsynchronous judgement.
Synchronous correction portion 37 when synchronous judging part 36 judges that the 1st reference signal is synchronous with the 2nd reference signal, by reference value in the 2nd reference signal generating section 31.In addition, synchronous correction portion 37, under synchronous judging part 36 is judged as the 1st reference signal and the nonsynchronous situation of the 2nd reference signal, is obtained and value that difference between the count value of the 2nd reference signal generating section 31 and the count value of overhead count section 34 offsets.Specifically, the count value of the 2nd reference signal generating section 31 accessed by count value acquisition unit 35 is deducted the count value of overhead count section 34 to obtain synchronous correction value by synchronous correction portion 37.Then, synchronous correction portion 37 deducts calculated synchronous correction value from fiducial value, using the value that obtains after subtracting each other as new reference value in the 2nd reference signal generating section 31.This new fiducial value refers to, the timer fiducial value (fiducial value of acquiescence) used when being judged as synchronous relative to synchronous judging part 36, the timer fiducial value that synchronous judging part 36 temporarily uses when being judged as asynchronous.
In addition, if synchronous judging part 36 is judged as that the 1st reference signal is asynchronous with the 2nd reference signal, and the value obtained after subtracting each other is set in the 2nd reference signal generating section 31 as new fiducial value, and the counting employing the value obtained after this subtracts each other completes, then synchronous correction portion 37 promptly by reference value in the 2nd reference signal generating section 31.Thus, fiducial value can be temporarily made to change the amount of synchronous correction value.Herein, enumerated the example performing the correction of once corresponding to synchronous correction value amount, but be not limited thereto, also can divide and perform several times.In this case, synchronous correction portion 37 after synchronous correcting process completes, by reference value in the 2nd reference signal generating section 31.
In addition, if synchronous judging part 36 is judged as between the 1st reference signal with the 2nd reference signal synchronous, then synchronous correction portion 37 can set the fiducial value of above-mentioned acquiescence again and again to the 2nd reference signal generating section 31, but also can when keeping synchronous, after setting the fiducial value once given tacit consent to, without any further action.
In addition, in the present embodiment, owing to performing synchronous correcting process every correcting process interval, therefore the possibility that the count value of the 2nd reference signal generating section 31 is different from the count value of overhead count section 34 is higher, is judged as that the 1st reference signal is asynchronous with the 2nd reference signal under synchronous judging part 36 most cases.Therefore, synchronous judging part 36 can not be utilized to perform judgement, namely, no matter whether the 1st reference signal is synchronous with the 2nd reference signal, can be obtained by synchronous correction portion 37 and value that difference between the count value of the 2nd reference signal generating section 31 and the count value of overhead count section 34 offsets, and this value is set in the 2nd reference signal generating section 31 as new fiducial value.
Thus, by omitting the structure of synchronous judging part 36, thus without the need to judging process, the processing load corresponding to the treating capacity needed for judgement can be alleviated.
Storage part 38 is stored in the application program (sequential program) that the 2nd operational part 32 carries out the regulation of computing.In addition, the application program that the 2nd operational part 32 carries out the regulation of computing such as sends instruction to the I/O module 13b, the 13c that are connected to from processor module 11b, and utilize the process that I/O module 13b, 13c control external equipment 14b, 14c.Therefore, mainly store in storage part 38 for the program processed that puts rules into practice to the I/O module 13b, the 13c that are connected with present treatment device module 11b, external equipment 14b, 14c.
I/O module 13 carries out the input and output process between external equipment 14 etc.Such as, the data etc. obtained from connected external equipment 14 etc. are exported (transmission) to processor module 11 by I/O module 13, or the result gone out by processor module 11 calculation process are exported to external equipment 14 etc., or store it.That is, the input data that processor module 11 utilizes application program to carry out computing to obtain from I/O module 13, and this operation result is provided to I/O module 13 as output data, thus external equipment 14 is controlled.
External equipment 14 is such as various transducer, motor, tape deck etc.External equipment 14, based on the control signal etc. from I/O module 13, carries out the input and output etc. of the detection of data or driving, data.
Herein, fiducial value can be pre-set in processor module 11a, processor module 11b, processor module 11c respectively, and the compilation device 15 (setting device) that also can be connected by outside respectively sets.
Compilation device 15 can by communicate with processor module 11 to increases such as the PC (Personal Computer: PC) that user etc. uses and the function setting fiducial value realizes, but being not limited thereto, also can be special setting device.Thereby, it is possible at random adjust fiducial value (treatment cycle) for each user.
Herein, in the examples described above, an example as signal synchronizing system 10 is illustrated multiprocessor, as long as and signal system synchronization signal 10 comprises the 1st reference signal generating section 21, the 2nd reference signal generating section 31, overhead count section 34, count value acquisition unit 35, synchronous judging part 36 and synchronous correction portion 37.
In addition, about the application examples of signal synchronizing system 10, be not limited to multiprocessor, also can be applied to such as following timer synchronization system: the dispatching station main device side being set to the digital signal of the date/time information sending atomic clock, and electronic clock will be set to from device side.
(the hardware configuration example of processor module 11)
Then, the hardware configuration example of accompanying drawing to processor module 11 is utilized to be described.Fig. 2 is the figure of an example of the hardware configuration representing processor module 11.Processor module 11 shown in Fig. 2 has input part 41, efferent 42, CPU43, FPGA44, memory 45 and external interface 46, and these parts are connected by shared bus B.
Input part 41 inputs various operation signal, such as, from the execution of the program of user etc.In addition, input part 41 can have the pointing device such as keyboard, mouse, touch panel that such as confession user etc. carries out operating, and when being inputted by voice etc., also can have voice-input device.
Efferent 42 has display, and various windows, data etc. needed for operating the processor module 11 of the process carried out in present embodiment show, and show the implementation, result etc. of the control program performed by CPU43.
CPU43 is based on control program, the executive program be kept in memory 45 of OS (Operating System: operating system) etc., by controlling the process of whole processor module 11, realize each process in present embodiment, the input and output etc. of such as, data between various computing and each hardware constituting portion.In addition, CPU43 and memory 45 link, play in fact the function of above-mentioned 1st operational part 22, the 2nd operational part 32, count value acquisition unit 35, synchronous judging part 36, synchronous correction portion 37, and built-in 1st reference signal generating section 21, the 2nd reference signal generating section 31.In addition, various information etc. required in the process of executive program also can obtain from memory 45, and are stored in memory 45 by execution result etc.
FPGA (Field-Programmable Gate Array: field programmable gate array) 44 is the integrated circuits can rewriting logical circuit.FPGA44 is made up of the various logic circuit of aiding CPU 43, in present embodiment, plays the effect of gap count portion 33, overhead count section 34 especially.Wherein, gap count portion 33 also can be processed by software.
The executive program etc. read out by CPU43 preserved by memory 45.In addition, memory 45 is made up of ROM (Read Only Memory: read-only memory), RAM (Random Access Memory: random access memory) etc.In addition, memory 45 also can have the memory cell such as hard disk, using as auxilary unit.In addition, memory 45 stores the executive program in present embodiment, the control program etc. be arranged in computer, carries out input and output as required.In addition, memory 45 corresponds to above-mentioned storage part 23,38 etc.
External interface 46 is via the transmitting-receiving carrying out data, control signal between transfer bus 12 grade and other processor module 11.In addition, external interface 46 also and carry out the transmitting-receiving etc. of data, control signal between the I/O module 13 be connected.
By above-mentioned hardware configuration, the synchronous correcting process in present embodiment can be performed.In addition, by installing executive program, thus the synchronous correcting process that can easily utilize general personal computer etc. to realize in present embodiment.
Next, below the synchronous correcting process example in execution mode 1 is described.
(the synchronous correcting process example in execution mode 1)
Fig. 3 ~ Fig. 5 is the sequential chart one of (~ three) for illustration of the synchronous correcting process example in execution mode 1.In the example shown in Fig. 3 ~ Fig. 5, show main processor modules 11a and the synchronous example from the count value between processor module 11b.In addition, the fiducial value (treatment cycle) in execution mode 1 is set to 1000 μ s, but is not limited thereto, such as, above-mentioned compilation device 15 also can be utilized suitably to change setting.
In Fig. 3, the 1st reference signal generating section 21 of main processor modules 11a counts.If its count value (1) moment in figure 3 reaches fiducial value, then export the 1st reference signal.Then, the 1st operational part 22 to put rules into practice process according to the 1st reference signal.In Fig. 3, the change of the region representation count value of hatched triangle, count value increases as time goes by, if reach counting target (such as fiducial value), then resets.
In addition, count from the 2nd reference signal generating section 31 of processor module 11b.If its count value (2) moment in figure 3 reaches fiducial value, then export the 2nd reference signal.Then, the 2nd operational part 32 to put rules into practice process according to the 2nd reference signal.Thus, main processor modules 11a and from processor module 11b, respectively according to the process that independently the 1st reference signal and the 2nd reference signal put rules into practice.
In addition, from processor module 11b, gap count portion 33 counts, and when count value reaches correcting process spacing value ((3) of Fig. 3), generates correcting process commencing signal.The preparation of synchronous correcting process is started according to described correcting process commencing signal.
The 1st reference signal generated in main processor modules 11a is sent to from processor module 11b as interrupt signal.Receive the 1st reference signal as interruption from processor module 11b, and utilize software to start synchronous correcting process ((4) of Fig. 3).Meanwhile, from the overhead count section 34 of processor module 11b, the count value of the counter be made up of this hardware is reset, and restart ((5) of Fig. 3).Then, when being ready to complete of synchronous correcting process, in Fig. 3 (6) moment, count value acquisition unit 35 obtains count value ((7) of Fig. 3) from the 2nd reference signal generating section 31, and obtains count value ((8) of Fig. 3) from overhead count section 34.
The count value provided by count value acquisition unit 35 is converted into the time by synchronous judging part 36., such as, obtain 300 μ s according to the count value of the 2nd reference signal generating section 31 herein, obtain 300 μ s according to the count value of overhead count section 34.Thereby, it is possible to measure from the starting point of the interruption of the 1st reference signal, the overhead to getting count value in synchronous correcting process, and the count value that can get the 2nd reference signal generating section 31 in this moment.When the 1st reference signal is synchronous with the 2nd reference signal, described count value should be equal.
The count value (300 μ s) of the 2nd reference signal generating section 31 got by count value acquisition unit 35 and the count value (300 μ s) of overhead count section 34 compare by synchronous judging part 36.In this situation, because two values are equal, therefore synchronous judging part 36 is judged as that the 1st reference signal is synchronous with the 2nd reference signal.
Because synchronous judging part 36 is judged as that the 1st reference signal is synchronous with the 2nd reference signal, therefore fiducial value 1000 μ s is set in the 2nd reference signal generating section 31 (this time inscribe the 2nd reference signal generating section 31 do not restart) by synchronous correction portion 37 as usual.Then, owing to reaching fiducial value 1000 μ s in (9) moment count value of Fig. 3, therefore the 2nd reference signal generating section 31 is restarted.
In addition, the 2nd reference signal generating section 31 is built in above-mentioned CPU43, and in present embodiment, is not limited thereto, and also can be provided separately with CPU43.
In addition, first mention, in the synchronous correcting process shown in Fig. 3, comprise the process of count value acquisition unit 35, synchronous judging part 36, the synchronously program of correction portion 37.
Fig. 4 shows the situation of the counter delay 3 μ s comparing main processor modules 11a from the counter of processor module 11b.
In Fig. 4, count from the gap count portion 33 of processor module 11b, when count value reaches correcting process spacing value ((1) of Fig. 4), generate correcting process commencing signal.The preparation of synchronous correcting process is started according to described correcting process commencing signal.
Because count value reaches fiducial value, therefore the 1st reference signal generating section 21 of primary processor 11a exports the 1st reference signal every 1000 μ s.From processor module 11b after generation correcting process commencing signal, receive the 1st reference signal as interruption, and utilize software to start synchronous correcting process ((2) of Fig. 4).Meanwhile, from the overhead count section 34 of processor module 11b, the count value of the counter be made up of this hardware is reset, and restart ((3) of Fig. 4).Then, when being ready to complete of synchronous correcting process, in (4) moment of Fig. 4, count value acquisition unit 35 obtains count value ((5) of Fig. 4) from the 2nd reference signal generating section 31, and obtains count value ((6) of Fig. 4) from overhead count section 34.
The count value provided by count value acquisition unit 35 is converted into the time by synchronous judging part 36., such as, obtain 297 μ s according to the count value of the 2nd reference signal generating section 31 herein, obtain 300 μ s according to the count value of overhead count section 34.Two count values compare by synchronous judging part 36, due to two count value differences, are therefore judged as that the 1st reference signal is asynchronous with the 2nd reference signal.
Because synchronous judging part 36 is judged as asynchronous, therefore synchronous correction portion 37 is by interim reference value in the 2nd reference signal generating section 31, is cancelled to make the difference between the count value of the 2nd reference signal generating section 31 and the count value of overhead count section 34.Specifically, what this formula that synchronous correction portion 37 utilizes " fiducial value (treatment cycle)-(count value of count value-2 reference signal generating section 31 of overhead count section 34) " obtained the count value of the 2nd reference signal generating section 31 restarts value (reset values), and calculated count value is set in the 2nd reference signal generating section 31 as interim fiducial value.When this example, interim fiducial value is 1000 μ s-(300 μ s-297 μ s)=997 μ s.Then, owing to reaching interim fiducial value 997 μ s in (7) moment count value of Fig. 4, therefore the 2nd reference signal generating section 31 is restarted.That is, the value obtained after the count value of count value-2 reference signal generating section 31 of overhead count section 34 is synchronous correction value.
Thus, in execution mode 1, for the 2nd circulation, the 2nd reference signal generating section 31 can be restarted in the moment roughly the same with the output time of the 1st reference signal that the next 3rd circulates.Therefore, execution mode 1 can make the 1st reference signal synchronous with the 2nd reference signal.In addition, when Fig. 4, after the 3rd circulation, fiducial value is set to 1000 μ s.
Fig. 5 shows the situation that 3 μ s done sth. in advance by the counter comparing main processor modules 11a from the counter of processor module 11b.
In Fig. 5, count from the gap count portion 33 of processor module 11b, when count value reaches correcting process spacing value ((1) of Fig. 5), generate correcting process commencing signal.The preparation of synchronous correcting process is started according to described correcting process commencing signal.
Because count value reaches fiducial value, therefore the 1st reference signal generating section 21 of main processor modules 11a exports the 1st reference signal every 1000 μ s.From processor module 11b after generating correcting process commencing signal, receive the 1st reference signal as interruption, and utilize software to start synchronous correcting process ((2) of Fig. 5).Meanwhile, from the overhead count section 34 of processor module 11b, the count value of the counter be made up of this hardware is reset, and restart ((3) of Fig. 5).Then, when being ready to complete of synchronous correcting process, in (4) moment of Fig. 5, count value acquisition unit 35 obtains count value ((5) of Fig. 5) from the 2nd reference signal generating section 31, and obtains count value ((6) of Fig. 5) from overhead count section 34.
The count value provided by count value acquisition unit 35 is converted into the time by synchronous judging part 36., such as, obtain 303 μ s according to the count value of the 2nd reference signal generating section 31 herein, obtain 300 μ s according to the count value of overhead count section 34.Two count values compare by synchronous judging part 36, due to two count value differences, are therefore judged as that the 1st reference signal is asynchronous with the 2nd reference signal.
Because synchronous judging part 36 is judged as asynchronous, therefore synchronous correction portion 37 sets interim fiducial value to the 2nd reference signal generating section 31, is cancelled to make the difference between the count value of the 2nd reference signal generating section 31 and the count value of overhead count section 34.Specifically, synchronous correction portion 37 calculates identically with the explanation of Fig. 4, obtains interim fiducial value, and by this interim reference value in the 2nd reference signal generating section 31.When this example, interim fiducial value is 1000 μ s-(300 μ s-303 μ s)=1003 μ s.Then, owing to reaching interim fiducial value 1003 μ s in (7) moment count value of Fig. 4, therefore the 2nd reference signal generating section 31 is restarted.That is, the value obtained after the count value of count value-2 reference signal generating section 31 of overhead count section 34 is synchronous correction value.
Thus, in execution mode 1, for the 2nd circulation, the 2nd reference signal generating section 31 can be restarted in the moment roughly the same with the output time of the 1st reference signal that the next 3rd circulates.Therefore, the signal synchronizing system of present embodiment can make the 1st reference signal and the 2nd reference signal synchronised.In addition, after the 3rd circulation of Fig. 5, fiducial value is set to 1000 μ s.As mentioned above, in execution mode 1, no matter in situation about postponing relative to the counter (timer) of main processor modules 11a from the counter (timer) of processor module 11b or when doing sth. in advance, all counter synchronisation can be realized rightly.
(the order example of signal synchronizing method)
Fig. 6 is the figure of the example of the general sequence (sequence) representing signal synchronizing method.In the example of fig. 6, for convenience of description, to employing main processor modules 11a and being synchronously described from processor module 11b, but present embodiment is not limited thereto, and can make multiple from processor module and a main processor modules synchronised.
In the counter synchronisation process of Fig. 6, first, 1st reference signal generating section 21 of main processor modules 11a generates the 1st reference signal (S01), generates the 2nd reference signal (S02) from the 2nd reference signal generating section 31 of processor module 11b.In addition, this process periodically carries out work in hardware.In addition, the 1st reference signal obtained in the process of S01 is also sent to from processor module 11b by main processor modules 11a.Therefore, the state that can receive the 1st reference signal is in all the time from processor module 11b.
In addition, count from the correcting process interval, 33 pairs, gap count portion of processor module 11b, when count value reaches correcting process spacing value, generate correcting process commencing signal, start the preparation (S03) of synchronous correcting process.
If after the count value in gap count portion 33 reaches correcting process spacing value, the 1st reference signal (S04) that main processor modules 11a sends is received from processor module 11b, then utilize software to start synchronous correcting process (S05), and make overhead count section 34 restart (S06) simultaneously.Then, count value acquisition unit 35 obtains two count values (S07) of the 2nd reference signal generating section 31 and overhead count section 34, synchronous judging part 36 comes synchronously to judge (S08) based on described two count values, be judged as in nonsynchronous situation, synchronous correction portion 37 is synchronously revised (S09).
Thereby, it is possible to make the signal of regulation synchronous accurately while suppression processing load.
(execution mode 2: synchronisation of nodes system)
The feature of the 2nd execution mode is, is included the time of delay that the transfer bus 12 in above-mentioned execution mode 1 produces and performs synchronous correcting process.Fig. 7 is the figure of an example of the general configuration of the synchronisation of nodes system represented in execution mode 2.Synchronisation of nodes system 50 shown in Fig. 7 is examples of carrying out counter synchronisation between multiple nodes such as node 51a ~ 51c.
Synchronisation of nodes system 50 has: multiple node 51a ~ 51c (being called as required below " node 51 "), communication path (communication network) 52, I/O (input and output) module 53 (illustrating with 53a ~ 53d in Fig. 7), external equipment 54 (illustrating with 54a ~ 54d in Fig. 7) and compilation device 55.That is, synchronisation of nodes system 50 via the communication path 52 as communication network by main controlled node 51a, be connected with slave node 51b, 51c.
Herein, for convenience of description, to using node 51a as main controlled node, using node 51b, 51c as slave node, the intrinsic structure of its each node is described, but be not limited thereto, the structure that each node both can have a main controlled node also has the structure of slave node, can become main controlled node can become slave node again to make each node.In addition, in execution mode 2, be set to communication path 52 and can produce the propagation delay time.
Herein, first the difference of execution mode 2 (Fig. 7) with execution mode 1 (Fig. 1) is described.Main controlled node 51a is equivalent to the main processor modules 11a in execution mode 1, slave node 51b, 51c be equivalent in execution mode 1 from processor module 11b, 11c.In addition, compilation device 55 is equal with compilation device 15 essence in execution mode 1, and in addition, I/O module 53a ~ 53d is equal with the I/O module 13a in execution mode 1 ~ 13d essence.In addition, external equipment 54a ~ 54d is equal with the external equipment 14a ~ 14d essence in execution mode 1.Thus, in below illustrating, the explanation of the structure identical with execution mode 1 is omitted.
Main controlled node 51a has: the 1st reference signal generating section 61 (the 1st reference signal generating section 21 corresponding to execution mode 1), the 1st operational part 62 (the 1st operational part 22 corresponding to execution mode 1), storage part 63 (storage part 23 corresponding to execution mode 1), gap count portion 64 (the gap count portion 33 corresponding to execution mode 1), propagation delay time notification unit 65 and synchronized frame notification unit 66.
Main difference point between main processor modules 11a in main controlled node 51a and execution mode 1 is, possess in execution mode 1 and be arranged at from the gap count portion 33 of processor module 11b as gap count portion 64, and also newly with the addition of propagation delay time announcement portion 65, synchronized frame notification unit 66.Thus, in below illustrating, the major part of execution mode 2 is described, omits the description the action identical with execution mode 1.
Below, an example of execution mode 2 is described.In execution mode 2, gap count portion 64 counts, and be preset with and carry out the suitable correcting process spacing value in the synchronous correcting process interval processed, when count value reaches correcting process spacing value, generate the correcting process commencing signal representing this situation.In addition, because correcting process spacing value is equal with execution mode 1 essence, therefore omit herein and be described.
In addition, this is in main controlled node 51a side and measures correcting process interval, but also can measure correcting process interval in slave node 51b side.In this situation, if reach correcting process spacing value at slave node 51b count value, then correcting process commencing signal is sent to main controlled node 51a, and starts synchronous correcting process.
After receiving correcting process commencing signal, propagation delay time claim frame is sent to slave node 51b, 51c to calculate the propagation delay time by the propagation delay time notification unit 65 of main controlled node 51a.This propagation delay time claim frame is identical with the form essence of synchronized frame described later, and different from the data of the established part (such as instruction department) in synchronized frame.The 1st reference signal that described propagation delay time claim frame and the 1st reference signal generating section 61 generate synchronizedly is sent out.
Then, propagation delay time notification unit 65 receives and receives framing from the slave node of replying propagation delay time claim frame.Then, moment when propagation delay time notification unit 65 receives according to acknowledgement frame and the difference between moment when sending propagation delay time claim frame, calculate main controlled node 51a and the round-trip transmission time of delay between slave node 51b, 51c.Then, the propagation delay time notification frame comprising the round-trip transmission time of delay calculated synchronizedly is sent to slave node 51b, 51c with next 1st reference signal by propagation delay time notification unit 65, thus notifies time of delay of being produced by communication path 52 to slave node 51b, 51c.
After being notified of round-trip transmission time of delay, pre-prepd synchronized frame, based on the 1st reference signal (with the 1st reference signal synchronised), is sent to slave node 51b, 51c via communication path 52 by main controlled node 51a.In addition, this process is performed by synchronized frame notification unit 66.Can describe in detail below, synchronized frame is the synchronizing datum signal that the count value of the count value of the 2nd reference signal generating section 71 for making slave node 51b, 51c and the 1st reference signal generating section 61 of main controlled node 51a matches.
Then, slave node 51b, 51c are described.Slave node 51b, 51c has: the 2nd reference signal generating section 71 (the 2nd reference signal generating section 31 corresponding to execution mode 1), 2nd operational part 72 (the 2nd operational part 32 corresponding to execution mode 1), overhead count section 74 (the overhead count section 34 corresponding to execution mode 1), count value acquisition unit 75 (the count value acquisition unit 35 corresponding to execution mode 1), synchronous judging part 76 (the synchronous judging part 36 corresponding to execution mode 1), synchronous correction portion 77 (the synchronous correction portion 37 corresponding to execution mode 1), storage part 78 (storage part 38 corresponding to execution mode 1), reception completion notice portion 79 and frame acceptance division 80.In addition, CPU43 is built-in with the 2nd reference signal generating section 71.Because the structure of slave node 51b, 51c is identical, therefore in the following description, utilize slave node 51b to be described, omit the explanation of slave node 51c.
Be with the main difference point of the processor module 11b of execution mode 1, synchronous judging part 76 is different from the synchronous judging part 36 of execution mode 1, and with the addition of reception completion notice portion 79 and frame acceptance division 80.Wherein, because other inscape is equal with execution mode 1 essence, therefore omit herein and be described.Below, the synchronous correcting process of slave node 51b in the propagation delay time comprising communication path 52 is described.
Reception completion notice portion 79 receives above-mentioned propagation delay time claim frame from main controlled node 51a, and will receive framing according to this propagation delay time claim frame and be sent to main controlled node 51a.
Frame acceptance division 80 receives the above-mentioned propagation delay time notification frame that main controlled node 51a sends, and the round-trip transmission time of delay (value) comprised by this frame retreats to above-mentioned memory 45 etc.Thus, slave node 51b gets round-trip transmission time of delay between main controlled node 51a and slave node 51b from main controlled node 51a.
Obtain the slave node 51b reception synchronized frame of round-trip transmission time of delay from main controlled node 51a, produce at the 2nd operational part 72 and interrupt.The 2nd operational part 72 receiving interruption starts synchronous correcting process described later.In addition, in the present embodiment, even if receive synchronized frame when not obtaining round-trip transmission time of delay, also certainly round-trip transmission can be set to zero (0) to start synchronous correcting process time of delay.In addition, if by after receiving synchronized frame, speed from interruption to the 2nd operational part 72 that send takes into account, then although not shown, but preferably use the hardware logics such as FPGA44 to be used as the receiving element of synchronized frame.
In addition, overhead count section 74 is measured and is received as starting point until perform the overhead value of synchronous correcting process with above-mentioned synchronized frame.Specifically, overhead count section 74 carries out the function of the counter (timer) of the hardware of restarting after playing and receiving synchronized frame.
Count value acquisition unit 75 obtains the count value of the 2nd reference signal generating section 71 and the count value of overhead count section 74 that perform the start time of synchronous correcting process in reality according to the reception of synchronized frame.
Synchronous judging part 76 by above-mentioned round-trip transmission time of delay divided by 2, obtain the propagation delay time of the one way of communication path 52, and obtain further the propagation delay time of this one way and the count value elapsed time of said system expense count section 74 are converted after the value that obtains be added and the aggregate delay time obtained.Then, synchronous judging part 76 by the calculated aggregate delay time, convert with the count value elapsed time of the 2nd reference signal generating section 71 accessed by count value acquisition unit 75 after the value that obtains compare.When equal both its comparative result is, synchronous judging part 76 judges that the 1st reference signal is synchronous with the 2nd reference signal, and when both are unequal, synchronous judging part 76 judges that the 1st reference signal is asynchronous with the 2nd reference signal.Herein, what is called synchronously means that the count value of the 1st reference signal generating section 61 is equal with the count value of the 2nd reference signal generating section 71.
In addition, synchronous judging part 76 can certainly be identical with the synchronous judging part 36 of execution mode 1, compares by the count value of each counter being converted into the time, thus judge synchronous/asynchronous.
In execution mode 2, if every correcting process interval, be judged as that the 1st reference signal is synchronous with the 2nd reference signal by synchronous judging part 76, then synchronous correction portion 77 by reference value in the 2nd reference signal generating section 71.In addition, be judged as, in the 1st reference signal and the nonsynchronous situation of the 2nd reference signal, obtaining the value difference between the count value of the 2nd reference signal generating section 71 and aggregate delay time value offseted.Specifically, the count value of the 2nd reference signal generating section 71 accessed by count value acquisition unit 75 is deducted aggregate delay time value to obtain synchronous correction value by synchronous correction portion 77.Then, synchronous correction portion 77 deducts calculated synchronous correction value from fiducial value, and using the value that obtains after subtracting each other as new reference value in the 2nd reference signal generating section 71.This new fiducial value is set in the fiducial value (fiducial value of acquiescence) of the 2nd reference signal generating section 71 and (the interim fiducial value) that temporarily set when being and being judged as synchronous relative to synchronous judging part 76, for the timing value of correction the 2nd reference signal generating section 71.
In addition, present embodiment at the reference value that will give tacit consent in the 2nd reference signal generating section 71, and when being synchronously maintained, can certainly not rewrite the fiducial value of acquiescence afterwards.
Thus, in the present embodiment, the impact in propagation delay time when notifying synchronizing datum signal (synchronized frame) via communication path 52 also take into account can be carried out synchronous correcting process.That is, in execution mode 2, can revise the count value of the overhead containing internodal propagation delay time and slave node 51b, 51c, thus can realize high-precision synchronously internodal.
(the synchronous correcting process example in execution mode 2)
Fig. 8 ~ Figure 10 is the sequential chart for illustration of the synchronous correcting process example in execution mode 2, is the synchronous example of the count value between main controlled node 51a with slave node 51b.In addition, the fiducial value (treatment cycle) in execution mode 2 is identical with execution mode 1, is set to 1000 μ s, and this fiducial value can utilize compilation device 55 suitably to change.
In Fig. 8, the 1st reference signal generating section 61 of main controlled node 51a counts.If this count value reaches fiducial value in (1) moment of Fig. 8, then export the 1st reference signal.Then, the process that puts rules into practice according to the 1st reference signal of the 1st operational part 62.
In addition, the 2nd reference signal generating section 71 of slave node 51b counts.If this count value reaches fiducial value in (2) moment of Fig. 8, then export the 2nd reference signal.Then, the process that puts rules into practice according to the 2nd reference signal of the 2nd operational part 72.Thus, in main controlled node 51a and slave node 51b, respectively according to the process that independently the 1st reference signal and the 2nd reference signal put rules into practice.
In addition, in main processor modules 51a, gap count portion 64 counts, and when count value reaches correcting process spacing value ((3) of Fig. 8), generates correcting process commencing signal.The synchronous correcting process in main controlled node 51a is started according to described correcting process commencing signal.
After synchronous correcting process starts, the propagation delay time notification unit 65 of main controlled node 51a is in order to calculate the propagation delay time and the propagation delay time of transmission claim frame ((4) of Fig. 8).If the reception completion notice portion 79 of slave node 51b receives propagation delay time claim frame from main controlled node 51a, then will receive framing according to this propagation delay time claim frame and be sent to main controlled node 51a ((5) of Fig. 8).
Then, the propagation delay time notification unit 65 of main controlled node 51a is according to receiving framing, calculate the round-trip transmission time of delay between main controlled node 51a and slave node 51b, send containing the round-trip transmission time of delay calculated (400 μ s) in interior propagation delay time notification frame ((6) of Fig. 8).If the frame acceptance division 80 of slave node 51b receives propagation delay time notification frame, then retreat to memory 45 grade ((7) of Fig. 8) the round-trip transmission time of delay (value) comprised by this frame.
After synchronous correcting process starts, synchronized frame is sent to slave node 51b ((8) of Fig. 8) as interrupt signal by the synchronized frame notification unit 66 of main controlled node 51a.Then, slave node 51b through propagation delay time (200 μ s) of the one way of communication path 52 at the reception of (9) of Fig. 8 to synchronized frame, utilize the software in slave node 51b to start synchronous correcting process.In addition, along with the reception of synchronized frame, the counter be made up of hardware of overhead count section 74 is cleared and restarts ((10) of Fig. 8).
Then, when being ready to complete of synchronous correcting process, in (11) moment of Fig. 8, count value acquisition unit 75 obtains count value ((12) of Fig. 8) from the 2nd reference signal generating section 71, and obtains count value ((13) of Fig. 8) from overhead count section 74.
Then, count value acquisition unit 75 carries out time conversion with reference to the count value of the 2nd reference signal generating section 71, thus obtains 400 μ s.Then, synchronous judging part 76 obtains the propagation delay time 200 μ s of one way from round-trip transmission time of delay (400 μ s), the 200 μ s obtained after being converted in calculated propagation delay time and the count value elapsed time of overhead count section 74 are added, thus try to achieve aggregate delay time 400 μ s.Then, the 400 μ s that synchronous judging part 76 obtains after being converted in the count value elapsed time of the 2nd reference signal generating section 71 accessed by aggregate delay time 400 μ s and count value acquisition unit 75 compare, because both are equal, be therefore judged as that the 1st reference signal is synchronous with the 2nd reference signal.
Because synchronous judging part 76 is judged as that the 1st reference signal is synchronous with the 2nd reference signal, therefore synchronous correction portion 77 is by usually like that, fiducial value 1000 μ s is set in the 2nd reference signal generating section 71 (the 2nd reference signal generating section 71 was not restarted in the setting moment).Then, owing to reaching fiducial value 1000 μ s in (14) moment count value of Fig. 8, therefore the 2nd reference signal generating section 71 is restarted.
Fig. 9 shows the situation of counter than the counter delay 3 μ s of main controlled node 51a of slave node 51b.
In Fig. 9, correcting process spacing value is reached in the count value in the gap count portion 64 of main controlled node 51a, and after starting synchronous correcting process, the process retreated to memory 45 grade to the round-trip transmission time of delay (value) that propagation delay time notification frame comprises by the frame acceptance division 80 of slave node 51b is identical with the process essence of Fig. 8, therefore omits the description herein.
After synchronous correcting process starts, in Fig. 9 (1) moment, synchronized frame is sent to slave node 51b as interrupt signal by the synchronized frame notification unit 66 of main controlled node 51a.Then, slave node 51b through propagation delay time (200 μ s) of the one way of communication path 52 at the reception of (2) of Fig. 9 to synchronized frame, utilize the software in slave node 51b to start synchronous correcting process.In addition, along with the reception of synchronized frame, the counter of overhead count section 74 is cleared and restarts ((3) of Fig. 9).
Then, when being ready to complete of synchronous correcting process, in (4) moment of Fig. 9, count value acquisition unit 75 obtains count value ((5) of Fig. 9) from the 2nd reference signal generating section 71, and obtains count value ((6) of Fig. 9) from overhead count section 74.
Then, count value acquisition unit 75 carries out time conversion with reference to the count value of the 2nd reference signal generating section 71, thus obtains 397 μ s.Then, synchronous judging part 76 obtains the propagation delay time 200 μ s of one way from round-trip transmission time of delay (400 μ s), the 200 μ s obtained after being converted in calculated propagation delay time and the count value elapsed time of overhead count section 74 are added, thus try to achieve aggregate delay time 400 μ s.Then, the 397 μ s that synchronous judging part 76 obtains after being converted in the count value elapsed time of the 2nd reference signal generating section 71 accessed by aggregate delay time 400 μ s and count value acquisition unit 75 compare, due to both not etc., be therefore judged as that the 1st reference signal is asynchronous with the 2nd reference signal.
Because synchronous judging part 76 judges that the 1st reference signal is asynchronous with the 2nd reference signal, therefore synchronous correction portion 77 by interim reference value in the 2nd reference signal generating section 71.Specifically, what this formula that synchronous correction portion 77 utilizes " fiducial value (the treatment cycle)-count value of m-2nd reference signal generating section 71 (during the aggregate delay) " obtained the 2nd reference signal generating section 71 restarts value (reset values), and calculated count value is set in the 2nd reference signal generating section 71 as interim fiducial value.When this example, interim fiducial value is 1000 μ s-(400 μ s-397 μ s)=997 μ s.Then, owing to reaching interim fiducial value 997 μ s in (7) moment count value of Fig. 9, therefore the 2nd reference signal generating section 71 is restarted.That is, during aggregate delay m-2nd reference signal generating section 71 count value after the value that obtains be synchronous correction value.
The counter that Figure 10 shows slave node 51b shifts to an earlier date the situation of 3 μ s than the counter of main controlled node 51a.
In Figure 10, correcting process spacing value is reached in the count value in the gap count portion 64 of main controlled node 51a, and after starting synchronous correcting process, the process retreated to memory 45 grade to the round-trip transmission time of delay (value) that propagation delay time notification frame comprises by the frame acceptance division 80 of slave node 51b is identical with the process essence of Fig. 8, Fig. 9, therefore omits the description herein.
After synchronous correcting process starts, in Figure 10 (1) moment, synchronized frame is sent to slave node 51b as interrupt signal by the synchronized frame notification unit 66 of main controlled node 51a.Then, slave node 51b through propagation delay time (200 μ s) of the one way of communication path 52 at the reception of (2) of Figure 10 to synchronized frame, utilize the software in slave node 51b to start synchronous correcting process.In addition, along with the reception of synchronized frame, the counter of overhead count section 74 is cleared and restarts ((3) of Figure 10).
Then, when being ready to complete of synchronous correcting process, in (4) moment of Figure 10, count value acquisition unit 75 obtains count value ((5) of Figure 10) from the 2nd reference signal generating section 71, and obtains count value ((6) of Figure 10) from overhead count section 74.
Then, count value acquisition unit 75 carries out time conversion with reference to the count value of the 2nd reference signal generating section 71, thus obtains 403 μ s.Then, synchronous judging part 76 obtains the propagation delay time 200 μ s of one way from round-trip transmission time of delay (400 μ s), and the 200 μ s obtained after being converted in the propagation delay time of calculated one way and the count value elapsed time of overhead count section 74 are added, thus obtain aggregate delay time 400 μ s.Then, the 403 μ s that synchronous judging part 76 obtains after being converted in the count value elapsed time of the 2nd reference signal generating section 71 accessed by aggregate delay time 400 μ s and count value acquisition unit 75 compare, due to both not etc., be therefore judged as that the 1st reference signal is asynchronous with the 2nd reference signal.
Because synchronous judging part 76 judges that the 1st reference signal is asynchronous with the 2nd reference signal, therefore synchronous correction portion 77 by interim reference value in the 2nd reference signal generating section 71.When this example, interim fiducial value is 1000 μ s-(400 μ s-403 μ s)=1003 μ s.Then, owing to arriving interim fiducial value 1003 μ s in (7) moment count value of Figure 10, therefore the 2nd reference signal generating section 71 is restarted.
In addition, when the example of Fig. 9 and Figure 10, in the 3rd circulation, the counter of master control side and the counter synchronised of subordinate side, therefore, after, original fiducial value 1000 μ s is set in the 2nd reference signal generating section 71 (the 2nd reference signal generating section 71 was not restarted in the setting moment) by synchronous correction portion 77.Then, the 2nd reference signal generating section 71 is restarted when count value reaches fiducial value 1000 μ s.That is, in execution mode 2, relative to the 3rd circulation, the counter of subordinate side can be restarted, therefore, it is possible to make the value of the counter of the value of the counter of master control side and subordinate side be matched to roughly equal value in the roughly the same moment of restarting of the counter with the next 4th master control side of circulating.
In addition, in synchronous correcting process, identical with execution mode 1, comprise the process of count value acquisition unit 75, synchronous judging part 76, the synchronously program of correction portion 77.
In addition, be built in premised on CPU43 by the 2nd reference signal generating section 71 of slave node 51b and be illustrated, but be not limited thereto.That is, the 2nd reference signal generating section 71 also can divide open realization with CPU43.But, because the 2nd reference signal generating section 71 is built in CPU43, the specified signal generated in the outside of CPU43 therefore cannot be utilized from hardware, the 2nd reference signal generating section 71 to be resetted.In other words, the 2nd reference signal generating section 71 has program to control the counter of its action.Therefore, present embodiment needs the reset processing (reboot process) utilizing program to perform the 2nd reference signal generating section 71, and its overhead is relevant with synchronous error.Thus, in present embodiment, need the structure of measuring system expense (also identical in execution mode 1).
In addition, in execution mode 2, synchronous correcting process carries out by the reception of synchronized frame the interrupt processing that starts.
In addition, in the above description, slave node 51b such as obtains from main controlled node 51a and keeps round-trip transmission time of delay, and effectively utilizes kept round-trip transmission time of delay when synchronous correcting process.In addition, following method is also had: round-trip transmission to be contained in synchronized frame and to be sent to slave node 51b, the round-trip transmission time that the slave node 51b receiving this synchronized frame uses synchronized frame to comprise time of delay by main controlled node 51a.Thus, main controlled node 51a suitably can notify round-trip transmission time of delay to slave node 51b according to situation, therefore in time can use the round-trip transmission time of delay corresponding with situation in slave node 51b.
In addition, about propagation delay time notification unit 65, situation round-trip transmission being informed to slave node 51b time of delay is illustrated, but is not limited thereto.Such as, propagation delay time notification unit 65 also can by round-trip transmission time of delay of calculating divided by 2 to obtain the propagation delay time of one way, and the propagation delay time of calculated one way is informed to slave node 51b.In this situation, the synchronous judging part 76 of slave node 51b directly uses the propagation delay time of the one way acquired, and obtains the aggregate delay time.
As explained above, in execution mode 2, make while the signal transmission delay time that communication path 52 produces can be included the 1st reference signal and the 2nd reference signal synchronised.
(notifying process about the propagation delay time in synchronous correcting process)
Then, the notifying process in the propagation delay time in above-mentioned synchronous correcting process is described.Figure 11 is the figure of an example of notifying process for illustration of the propagation delay time in execution mode 2.In addition, in the example of fig. 11, there is above-mentioned main controlled node 51a and slave node 51b, 51c, and each node 51 via communication path 52 can the state of receiving and transmitting signal be connected.In addition, in the following description, the example that main controlled node 51a obtains the propagation delay time of the signal produced because of the communication path 52 between each node 51 is shown.
In addition, the square shown in Figure 11 represents frame, and the square above the line of each node 51 represents transmission frame, and the square below line represents received frame.In addition, the frame shown in Figure 11 has: propagation delay time claim frame 81 (be expressed as " REQ* " in Figure 11 (* such as represent each slave node identifier (being such as b, c) (following identical)), receive framing 82 (" REC* " in Figure 11), propagation delay time notification frame 83 (" SET* " in Figure 11) and the acknowledgement frame 84 (" ANS* " in Figure 11) for propagation delay time notification frame 83.
In the example of Figure 11, main controlled node 51a according to main controlled node synchronous base by propagation delay time claim frame 81b (REQb) broadcast transmission for slave node 51b on communication path 52.Now, the information (Object node information) being expressed as the content that the propagation delay time for slave node 51b asks is included in propagation delay time claim frame 81b.
The propagation delay time claim frame 81b of institute's broadcast transmission via communication path 52, regulation propagation delay time after, by each slave node 51b, 51c receive.In addition, in the example of fig. 11, slave node 51b according to main controlled node synchronous base time of delay D1 receive propagation delay time claim frame 81b, slave node 51c according to main controlled node synchronous base time of delay D2 receive propagation delay time claim frame 81b.
Herein, each slave node 51b, 51c confirm the above-mentioned Object node information that propagation delay time claim frame 81b comprises.Thus, because propagation delay time claim frame 81b is the request for slave node 51b, therefore only slave node 51b receives framing 82b (RECb) to main controlled node 51a broadcast transmission.Now, receive in framing 82b to include and represent it is the information (Object node information) receiving the content of framing for main controlled node 51a.
What sent receives framing 82b via communication path 52, receive by main controlled node 51a and slave node 51c.Then, main controlled node 51a and slave node 51c confirms receiving the above-mentioned Object node information that framing 82b comprises.As mentioned above, receiving framing 82b is frame for main controlled node 51a.Therefore, main controlled node 51a is based on from the transmission of the propagation delay time claim frame 81b sent according to main controlled node synchronous base, to the temporal information received this receives framing 82b, set the propagation delay time for slave node 51b.In addition, the propagation delay time set herein can be the round-trip transmission time of delay that the signal of regulation comes and goes between main controlled node 51a and slave node 51b via communication path 52, also can be the propagation delay time of one way.
In addition, main controlled node 51a generates the propagation delay time notification frame 83b (SETb) being used for being informed to slave node 51b the set propagation delay time, and according to the propagation delay time notification frame 83b that main controlled node synchronous base broadcast transmission generates.In addition, above-mentioned Object node information is comprised in propagation delay time notification frame 83b.
The propagation delay time notification frame 83b of institute's broadcast transmission is identical with above-mentioned propagation delay time claim frame 81b, via communication path 52, regulation propagation delay time after, by each slave node 51b, 51c receive.
Now, slave node 51b is judged as YES the information for this node according to the Object node information of received propagation delay time notification frame 83b, thus carries out the propagation delay time comprised in frame, the synchronous correcting process of execution mode 2 that is included with the said system overhead time etc.In addition, main controlled node 51b generates the acknowledgement frame 84b (ANSb) for propagation delay time notification frame 83b, and carries out broadcast transmission to generated acknowledgement frame 84b.Now, the information (Object node information) representing the content being frame for main controlled node 51a and the information etc. representing the completed content of synchronous correcting process is included in acknowledgement frame 84b.
The acknowledgement frame 84b sent is identical with the above-mentioned framing 82b that receives, via communication path 52, receive by main controlled node 51a and slave node 51c.Then, main controlled node 51a and slave node 51c confirms the above-mentioned Object node information that acknowledgement frame 84b comprises.As mentioned above, acknowledgement frame 84b is the frame for main controlled node 51a.Therefore, main controlled node 51a can complete this situation by holding synchronous correcting process from the acknowledgement frame 84b of slave node 51b.In addition, although slave node 51c receives propagation delay time claim frame 81b (REQb), receives framing 82b (RECb), propagation delay time notification frame 83b (SETb), acknowledgement frame 84b (ANSb), but owing to not being all the frame for this node, therefore abandon received frame.
Content so far is all the propagation delay time notifying process to slave node 51b.Therefore main controlled node 51a is similarly to slave node 51c notification transmission time of delay.
Specifically, in the example of Figure 11, main controlled node 51a according to main controlled node synchronous base by propagation delay time claim frame 81c (REQc) broadcast transmission for slave node 51c on communication path 52.The propagation delay time claim frame 81c of institute's broadcast transmission as described above via communication path 52, regulation propagation delay time (D1, D2), by each slave node 51b, 51c receive.
Due to the request that propagation delay time claim frame 81c is for slave node 51c, therefore only slave node 51c receives framing 82c (RECc) to main controlled node 51a broadcast transmission.What sent receives framing 82c via communication path 52, receive by main controlled node 51a and slave node 51c.Receiving framing 82c is frame for main controlled node 51a.Therefore, main controlled node 51a is based on from the transmission of the propagation delay time claim frame 81c sent according to main controlled node synchronous base, to the temporal information received this receives framing 82c, set the propagation delay time for slave node 51c.In addition, the propagation delay time set herein can be the round-trip transmission time of delay that the signal of regulation comes and goes between main controlled node 51a and slave node 51c via communication path 52, also can be the propagation delay time of one way.
In addition, main controlled node 51a generates the propagation delay time notification frame 83c (SETc) being used for being informed to slave node 51c the set propagation delay time, and according to the propagation delay time notification frame 83c that main controlled node synchronous base broadcast transmission generates.The propagation delay time claim frame 83c of institute's broadcast transmission is identical with above-mentioned propagation delay time claim frame 81c, via communication path 52, regulation propagation delay time (D1, D2), by each slave node 51b, 51c receive.
Now, slave node 51b as described above, be judged as YES the information for this node according to the Object node information of received propagation delay time notification frame 83c, carry out the propagation delay time comprised in frame, the synchronous correcting process of execution mode 2 that is included with the said system overhead time etc.In addition, slave node 51c generates the acknowledgement frame 84c (ANSc) for propagation delay time notification frame 83c, and carries out broadcast transmission to generated acknowledgement frame 84c.Now, the information (Object node information) representing the content being frame for main controlled node 51a and the information etc. representing the completed content of synchronous correcting process is included in acknowledgement frame 84c.
The acknowledgement frame 84c sent is identical with the above-mentioned framing 82c that receives, via communication path 52, receive by main controlled node 51a and slave node 51c.Then, main controlled node 51a and slave node 51b confirms the above-mentioned Object node information that acknowledgement frame 84c comprises.As mentioned above, acknowledgement frame 84c is the frame for main controlled node 51a.Therefore, main controlled node 51a can complete this situation by holding synchronous correcting process from the acknowledgement frame 84c of slave node 51c.In addition, although slave node 51b receives propagation delay time claim frame 81c (REQc), receives framing 82c (RECc), propagation delay time notification frame 83c (SETc), acknowledgement frame 84c (ANSc), but owing to not being all the frame for this node, therefore abandon received frame.
In execution mode 2, by implementing above-mentioned process successively to each slave node 51b, 51c of communication path 52, thus can notification transmission time of delay.
In addition, the notifying process in propagation delay time is not limited to above-mentioned steps.Such as, transmitting counter can be set at above-mentioned each intra-node, and utilize this transmitting counter to control as sending acknowledgement frame 84 in the different moment, so that make on communication path 52, on main controlled node 51a can not due to such as broadcast transmission propagation delay time claim frame 81, and slave node 51b, 51c of receiving this propagation delay time claim frame 81 send acknowledgement frame 84 and produce and block up.
In above-mentioned execution mode 2, in the system such as with the such star topology of Ethernet (registered trade mark), for the common memory network utilizing time multiplexed transmission mode, the counter synchronisation of each node can be made, in whole device, carry out the Synchronization Control matched with the moment controlled.In addition, in execution mode 2, carry out the counter that synchronous counter can utilize microcomputer inside, or utilize the counter based on hardware such as FPGA to form.Therefore, in execution mode 2, by utilizing the hardware such as such as FPGA to carry out configuration example as at the counter synchronous with main controlled node 51a and measure the counter in processing time of the microcomputer time of reception of carrying out the frame received and dispatched, and microcomputer is utilized to carry out its count value of computing, thus can correcting process error.
Herein, in the examples described above, as an example of synchronisation of nodes system 50, the synchronisation of nodes between master control-slave node is illustrated, but in the present embodiment, is not limited thereto, also can be applied to the sample-synchronous technology in such as protection relay etc.
(network transmission system: general configuration example)
Herein, in above-mentioned execution mode 2, there is the situation that the relays such as the HUB (hub) such as utilizing IEEE802.3u (100BASE-TX) or IEEE802.3ab (1000BASE-T) etc. such will be connected between each node.Figure 12 is the figure of an example of the general configuration representing the network transmission system comprising the synchronisation of nodes system 50 that make use of main controlled node 51a in execution mode 2 and slave node 51b, 51c.Network transmission system 90 shown in Figure 12 has as an example: above-mentioned multiple node 51 (being node 51a ~ 51c in the example of Figure 12), HUB91 (being HUB91a ~ 91e in the example of Figure 12) as one or more relay.In addition, the quantity of node, relay, kind, method of attachment are not limited thereto.
In the example of Figure 12, by the main controlled node of Fig. 7, namely node 51a is set to node A (master station), and by the slave node of Fig. 7, namely node 51b, node 51c are set to Node B, node C (slave station).In addition, as shown in figure 12, the communication path of network transmission system 90 is such as have the star-like of relay between main controlled node 51a and slave node 51b.In addition, relay uses HUB as an example, but present embodiment is not limited thereto, such as, also can use router, repeater, photoconverter etc.
In addition, main controlled node 51a and slave node 51b, 51c are such as Programmable Logic Controller (control device or also referred to as PLC (Programmable Logic Controller: programmable logic controller (PLC)), the communication path of network transmission system 90 is the exchanges data buses exchanged these Programmable Logic Controllers data to each other.Be connected to the equipment of this exchanges data bus such as except above-mentioned Programmable Logic Controller, also have PC, server, I/O module, drive unit (being such as inverter, servomechanism etc.) etc.
Network transmission system 90 shown in Figure 12 is connected to the HUB91a identical with node 51a and node 51c, and node 51b is connected with node 51a and node 51c via the HUB (relay) of 5 grades.
Herein, in the HUB of general Ethernet, adopt the interface mode being called as storage forwarding.In this situation, the frame sent all is stored in the reception buffer memory in HUB, sends after carrying out HUB inter-process (such as abnormal judgement or sending destination judgement etc.).
(the order example of node synchronization method)
Figure 13 is the figure of an example of the general sequence representing node synchronization method.In the example of Figure 13, for convenience of description, to employing synchronously being illustrated of main controlled node 51a and slave node 51b, but being not limited thereto in the present embodiment, multiple slave node can be made synchronous with a main controlled node.
In the synchronisation of nodes process of Figure 13, first, the 1st reference signal generating section 61 of main controlled node 51a generates the 1st reference signal (S11), and the 2nd reference signal generating section 71 of slave node 51b generates the 2nd reference signal (S12).In addition, this process periodically carries out work in hardware.
In addition, the correcting process interval, 64 pairs, gap count portion of main controlled node 51a counts, and when count value reaches correcting process spacing value, generates correcting process commencing signal, starts synchronous correcting process (S13).
When the count value in gap count portion 64 reaches correcting process spacing value, start the synchronous correcting process (S13) in main controlled node 51a, the propagation delay time notification unit 65 of main controlled node 51a is in order to calculate propagation delay time and the propagation delay time of transmission claim frame (S14).In addition, propagation delay time claim frame is the frame obtained after only changing the data of the established part that synchronized frame comprises, and in other words also can be called synchronized frame, is described with " propagation delay time claim frame " herein conveniently.
If the reception completion notice portion 79 of slave node 51b receives propagation delay time claim frame, then generate reception completion notice, carry out notifying (S15) to main controlled node 51a.
The propagation delay time notification unit 65 of main controlled node 51a is when receiving reception completion notice, calculate such as round-trip transmission time of delay (S16), and generate the propagation delay time notification frame (S17) containing calculated round-trip transmission time of delay etc., then generated propagation delay time notification frame is sent to slave node 51b (S18) via communication path 52.
If the frame acceptance division 80 of slave node 51b receives propagation delay time notification frame, then the round-trip transmission time of delay (value) comprised by this frame retreats to memory 45 grade (S19).Then, synchronized frame is synchronously sent to slave node 51b (S20) as interrupt signal by the synchronized frame notification unit 66 of main controlled node 51a and the 1st reference signal.Slave node 51b is (S21) when receiving synchronized frame, starts the synchronous correcting process (S22) based on software, and overhead count section 74 is restarted (S23).Then, count value acquisition unit 75 obtains two count values (S24) of the 2nd reference signal generating section 71 and overhead count section 74, synchronous judging part 76 comes synchronously to judge (S25) based on described two count values, be judged as in nonsynchronous situation, calculating the aggregate delay time (S26).The aggregate delay time is the value obtained after being added with overhead value in the such as propagation delay time, but is not limited thereto.In addition, the synchronous correction portion 77 of slave node 51b utilizes the aggregate delay time calculated synchronously to revise (S27).In addition, in the process shown in Figure 13, the acknowledgement frame that the synchronous correction of expression also can have been completed this situation by slave node 51b is sent to main controlled node 51a.In addition, main controlled node 51a also carries out synchronisation of nodes process by the slave node beyond the above-mentioned steps couple slave node 51b be connected with communication path 52.
Herein, in present embodiment, generating the program (node synchronisation procedure) for making computer play the effect of each unit that above-mentioned node 51 has, by generated program is installed on computer etc., thus realizing above-mentioned each synchronisation of nodes process.
As mentioned above, according to the present embodiment, can, while suppression processing load, make the signal of regulation synchronous accurately.Thus, the stabilisation of the throughput of each node 51 can such as be realized.In addition, according to the present embodiment, in the system with the such star topology of such as Ethernet, for the common memory network utilizing time multiplexed transmission mode, the timer synchronization of each node 51 can be made, realize high efficiency, the high efficiency of exchanges data, the stabilisation etc. of throughput of transmission.
In addition, present embodiment can be applicable to utilize multiple operation to carry out synchronous method during a series of action in large-scale equipment such as such as iron and steel factory etc., in addition, can also be widely used in the method for synchronization between each device in whole gigabit Ethernet.
Above, be described the preferred embodiment of the present invention with reference to accompanying drawing, the present invention is not limited to described execution mode.Those skilled in the art, in the category described in the scope of claim, can expect various variation or fixed case, and it also belongs in technical scope of the present invention certainly.
In addition, the signal synchronizing method of this specification and each step of node synchronization method might not be carried out temporally sequence and process along the order described in precedence diagram, also can comprise parallel processing or utilize the process of subprogram.
Industrial practicality
The present invention relates to the signal synchronizing system for making the signal of regulation synchronous, synchronisation of nodes system, signal synchronizing method and node synchronization method.
Label declaration
10 signal synchronizing systems
11 processor modules
12 transfer bus
13,53I/O (input and output) module
14,54 external equipments
15,55 compilation devices
21,61 the 1st reference signal generating section
22,62 the 1st operational parts
23,38,63,78 storage parts
31,71 the 2nd reference signal generating section
32,72 the 2nd operational parts
34,74 overhead count section
35,75 count value acquisition units
36,76 synchronous judging parts
37,77 synchronous correction portions
41 input parts
42 efferents
43 CPU
44 FPGA
45 memories
46 external interfaces
50 synchronisation of nodes systems
51 nodes
52 communication paths
65 propagation delay time notification units
66 synchronized frame notification units
79 reception completion notice portions
80 frame acceptance divisions
81 propagation delay time claim frames
82 receive framing
83 propagation delay time notification frame
84 acknowledgement frames
90 network transmission systems
91 HUB (relay)

Claims (18)

1. a signal synchronizing system, comprise according to the 1st reference signal carry out action primary module and according to the 2nd reference signal carry out action from module, and make the 2nd reference signal synchronous with the 1st reference signal, it is characterized in that,
Described primary module comprises: the 1st reference signal generating section, and the 1st reference signal generating section, by counting, when count value reaches the fiducial value preset, generates described 1st reference signal, describedly comprises from module:
2nd reference signal generating section, the 2nd reference signal generating section, by counting, when count value reaches described fiducial value, generates described 2nd reference signal;
Gap count portion, this gap count portion counts the interval of carrying out synchronous correcting process;
Overhead count section, this overhead count section, after described gap count portion count value reaches the correcting process spacing value carrying out described synchronous correcting process, receives described 1st reference signal, thus restarts, and count;
Count value acquisition unit, this count value acquisition unit, after described gap count portion count value reaches described correcting process spacing value, obtains the count value of described 2nd reference signal generating section and the count value of described overhead count section according to the reception of described 1st reference signal; And
Synchronous correction portion, the value of the difference offset between the count value of described 2nd reference signal generating section and the count value of described overhead count section is temporarily set in described 2nd reference signal generating section as fiducial value by this synchronous correction portion.
2. signal synchronizing system as claimed in claim 1, is characterized in that,
Described comprising from module performs this processor from the computing module,
Described 2nd reference signal generating section is the counter only having described processor to access.
3. signal synchronizing system as claimed in claim 2, is characterized in that,
The described processor comprised from module plays the effect of described count value acquisition unit, described synchronous correction portion.
4. signal synchronizing system as claimed any one in claims 1 to 3, is characterized in that,
Describedly also to comprise from module: synchronous judging part, this synchronous judging part is when the count value of described 2nd reference signal generating section accessed by described count value acquisition unit is different from the count value of described overhead count section, be judged as that described 1st reference signal is asynchronous with described 2nd reference signal
The value offsetting described difference, only under described synchronous judging part is judged as nonsynchronous situation, is temporarily set in described 2nd reference signal generating section as fiducial value by described synchronous correction portion.
5. signal synchronizing system as claimed in claim 4, is characterized in that,
Described synchronous judging part carries out time conversion to the count value of described 2nd reference signal generating section got by described count value acquisition unit and the count value of described overhead count section, is judged as asynchronous when both time is different.
6. the signal synchronizing system according to any one of claim 1 to 5, is characterized in that,
Described 1st reference signal generating section periodically generates described 1st reference signal,
Described 2nd reference signal generating section periodically generates described 2nd reference signal.
7. the signal synchronizing system according to any one of claim 1 to 6, is characterized in that,
The setting device that described fiducial value can be connected by outside sets.
8. a synchronisation of nodes system, comprises and carries out the main controlled node of action according to the 1st reference signal and carry out the slave node of action according to the 2nd reference signal, and make the 2nd reference signal synchronous with the 1st reference signal, it is characterized in that,
Described main controlled node comprises:
1st reference signal generating section, the 1st reference signal generating section, by counting, when count value reaches the fiducial value preset, generates described 1st reference signal;
Gap count portion, this gap count portion counts the interval of carrying out synchronous correcting process;
Propagation delay time notification unit, this propagation delay time notification unit is after described gap count portion count value reaches the correcting process spacing value carrying out described synchronous correcting process, calculate the propagation delay time in the communication path connecting described main controlled node and described slave node, and inform described slave node; And
Synchronized frame notification unit, this synchronized frame notification unit utilizes described communication path that the synchronized frame synchronous with described 1st reference signal is sent to described slave node,
Described slave node comprises:
2nd reference signal generating section, the 2nd reference signal generating section, by counting, when count value reaches described fiducial value, generates described 2nd reference signal;
Overhead count section, this overhead count section receives described synchronized frame, thus restarts, and counts;
Count value acquisition unit, this count value acquisition unit, according to the reception of described synchronized frame, obtains the count value of described 2nd reference signal generating section and the count value of described overhead count section; And
Synchronous correction portion, the value of the difference offset between the count value of described 2nd reference signal generating section and aggregate delay time value is temporarily set in described 2nd reference signal generating section as fiducial value by this synchronous correction portion, wherein, described aggregate delay time value is the count value of described overhead count section and the value sum representing the described propagation delay time.
9. synchronisation of nodes system as claimed in claim 8, is characterized in that,
Propagation delay time claim frame is sent to described slave node by described propagation delay time notification unit, and receive from described slave node and receive framing for described propagation delay time claim frame, the difference between moment during transmission according to moment during this reception and described propagation delay time claim frame calculates the described propagation delay time.
10. synchronisation of nodes system as claimed in claim 8 or 9, is characterized in that,
Described communication path is the star-like communication path between described main controlled node and described slave node with relay.
11. synchronisation of nodes systems according to any one of claim 8 to 10, is characterized in that,
Described slave node comprises the processor of the computing performed in this slave node,
Described 2nd reference signal generating section is the counter only having described processor to access.
12. synchronisation of nodes systems as claimed in claim 11, is characterized in that,
The processor that described slave node comprises plays the effect of described count value acquisition unit, described synchronous correction portion.
13. synchronisation of nodes systems according to any one of claim 8 to 12, is characterized in that,
Described slave node also comprises: synchronous judging part, this synchronous judging part is when the count value of described 2nd reference signal generating section accessed by described count value acquisition unit is different from the described aggregate delay time, be judged as that described 1st reference signal is asynchronous with described 2nd reference signal
The value offsetting described difference, only under described synchronous judging part is judged as nonsynchronous situation, is temporarily set in described 2nd reference signal generating section as fiducial value by described synchronous correction portion.
14. synchronisation of nodes systems as claimed in claim 13, is characterized in that,
Described synchronous judging part carries out time conversion to the count value of described 2nd reference signal generating section got by described count value acquisition unit and the count value of described overhead count section, is judged as asynchronous when both time is different.
15. synchronisation of nodes systems according to any one of claim 8 to 14, is characterized in that,
Described 1st reference signal generating section periodically generates described 1st reference signal,
Described 2nd reference signal generating section periodically generates described 2nd reference signal.
16. synchronisation of nodes systems according to any one of claim 8 to 15, is characterized in that,
The setting device that described fiducial value can be connected by outside sets.
17. 1 kinds of signal synchronizing methods, utilize according to the 1st reference signal carry out action primary module and according to the 2nd reference signal carry out action from module, make the 2nd reference signal synchronous with the 1st reference signal, it is characterized in that,
Described primary module, by counting, when count value reaches the fiducial value preset, generates described 1st reference signal,
Described from module by counting, when count value reaches described fiducial value, generate described 2nd reference signal,
And the interval of carrying out synchronous correcting process is counted,
After count value reaches the correcting process spacing value carrying out described synchronous correcting process, receive described 1st reference signal, thus restart, and count,
After representing that the count value of carrying out the interval of described synchronous correcting process reaches described correcting process spacing value, obtain the count value for generating described 2nd reference signal and receive described 1st reference signal and the count value obtained after restarting,
To the count value that is used for generating described 2nd reference signal be offset and receive described 1st reference signal and the value of difference between the count value obtained after restarting temporarily is set as the counting for generating described 2nd reference signal as fiducial value.
18. 1 kinds of node synchronization method, utilize and carry out the main controlled node of action according to the 1st reference signal and carry out the slave node of action according to the 2nd reference signal, make the 2nd reference signal synchronous with the 1st reference signal, it is characterized in that,
Described main controlled node, by counting, when count value reaches the fiducial value preset, generates described 1st reference signal,
And the interval of carrying out synchronous correcting process is counted,
After the count value at the interval of carrying out described synchronous correcting process reaches correcting process spacing value, calculate the propagation delay time in the communication path connecting described main controlled node and described slave node, and inform described slave node,
Utilize described communication path that the synchronized frame synchronous with described 1st reference signal is sent to slave node,
Described slave node, by counting, when count value reaches described fiducial value, generates described 2nd reference signal,
And receive described synchronized frame, thus restart, and count,
According to the reception of described synchronized frame, obtain the count value for generating described 2nd reference signal and receive described synchronized frame and the count value obtained after restarting,
Using the counting of offsetting the value that is used for the difference generated between the count value of described 2nd reference signal and aggregate delay time value and being temporarily set as generating described 2nd reference signal as fiducial value, wherein, described aggregate delay time value receives described synchronized frame and the count value obtained after restarting and the value sum representing the described propagation delay time.
CN201280077569.7A 2012-12-13 2012-12-13 Signal synchronizing system, node synchronization system, signal synchronizing method and node synchronization method Active CN104838615B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2012/082334 WO2014091592A1 (en) 2012-12-13 2012-12-13 Signal synchronization system, node synchronization system, signal synchronization method, and node synchroniz ation method

Publications (2)

Publication Number Publication Date
CN104838615A true CN104838615A (en) 2015-08-12
CN104838615B CN104838615B (en) 2017-08-18

Family

ID=50933913

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201280077569.7A Active CN104838615B (en) 2012-12-13 2012-12-13 Signal synchronizing system, node synchronization system, signal synchronizing method and node synchronization method

Country Status (4)

Country Link
JP (1) JP5825446B2 (en)
KR (1) KR101636496B1 (en)
CN (1) CN104838615B (en)
WO (1) WO2014091592A1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106557062A (en) * 2015-09-28 2017-04-05 发那科株式会社 Numerical control system with the synchronization control function between unit
CN109644240A (en) * 2017-07-11 2019-04-16 深圳市柔宇科技有限公司 Image pickup method and terminal
CN114116579A (en) * 2020-08-25 2022-03-01 横河电机株式会社 Information processing apparatus, information processing system, and information processing method
CN114285512A (en) * 2021-11-17 2022-04-05 中国电子科技集团公司第五十四研究所 Communication timing method, communication system and communication equipment

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6719994B2 (en) * 2016-06-30 2020-07-08 キヤノン株式会社 Communication system, communication device, and communication method
KR102200451B1 (en) * 2018-09-21 2021-01-08 주식회사 룩시드랩스 Method for synchronizing time and apparatus using the same
FR3108817B1 (en) * 2020-03-26 2022-03-04 Safran Communication method according to a TDMA protocol between a master device and at least one slave device
KR20230079632A (en) * 2021-11-29 2023-06-07 성창 주식회사 System for synchronizing time between server and IoT device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101039145A (en) * 2007-03-30 2007-09-19 华为技术有限公司 Method and apparatus for realizing clock
CN101136737A (en) * 2007-07-16 2008-03-05 中兴通讯股份有限公司 System and method for eliminating long line transmission time delay of source synchronizing signal
US20080107218A1 (en) * 2006-11-02 2008-05-08 Andrew Geissler System and Method of Measurement for a Distributed Computer System
CN101431796A (en) * 2008-12-10 2009-05-13 扬州万方电子技术有限责任公司 Method for clock master-slave synchronization of centered broad band radio communication system
JP2009182659A (en) * 2008-01-30 2009-08-13 Toshiba Corp Timing synchronizing method, synchronization device, synchronization system, and synchronization program
US20110267854A1 (en) * 2011-03-29 2011-11-03 American Superconductor Corporation Power converter with dual ring network control

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6691071B2 (en) * 2002-05-13 2004-02-10 Motorola, Inc. Synchronizing clock enablement in an electronic device
JP4241343B2 (en) * 2003-11-26 2009-03-18 富士電機システムズ株式会社 Transmission timing determination method, bus usage right arbitration method, network system, program
JP2005253033A (en) * 2004-02-06 2005-09-15 Nippon Telegr & Teleph Corp <Ntt> Network synchronization device, clock transmission method, and clock transmission packet network
KR101011314B1 (en) * 2008-03-31 2011-01-28 후지쯔 가부시끼가이샤 Apparatus with clock generation function, method for setting reference frequency, and method for adjusting reference frequency

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080107218A1 (en) * 2006-11-02 2008-05-08 Andrew Geissler System and Method of Measurement for a Distributed Computer System
CN101039145A (en) * 2007-03-30 2007-09-19 华为技术有限公司 Method and apparatus for realizing clock
CN101136737A (en) * 2007-07-16 2008-03-05 中兴通讯股份有限公司 System and method for eliminating long line transmission time delay of source synchronizing signal
JP2009182659A (en) * 2008-01-30 2009-08-13 Toshiba Corp Timing synchronizing method, synchronization device, synchronization system, and synchronization program
CN101431796A (en) * 2008-12-10 2009-05-13 扬州万方电子技术有限责任公司 Method for clock master-slave synchronization of centered broad band radio communication system
US20110267854A1 (en) * 2011-03-29 2011-11-03 American Superconductor Corporation Power converter with dual ring network control

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106557062A (en) * 2015-09-28 2017-04-05 发那科株式会社 Numerical control system with the synchronization control function between unit
CN106557062B (en) * 2015-09-28 2019-05-10 发那科株式会社 Numerical control system with the synchronization control function between unit
CN109644240A (en) * 2017-07-11 2019-04-16 深圳市柔宇科技有限公司 Image pickup method and terminal
CN114116579A (en) * 2020-08-25 2022-03-01 横河电机株式会社 Information processing apparatus, information processing system, and information processing method
CN114285512A (en) * 2021-11-17 2022-04-05 中国电子科技集团公司第五十四研究所 Communication timing method, communication system and communication equipment
CN114285512B (en) * 2021-11-17 2024-01-23 中国电子科技集团公司第五十四研究所 Communication timing method, communication system and communication equipment

Also Published As

Publication number Publication date
JP5825446B2 (en) 2015-12-02
JPWO2014091592A1 (en) 2017-01-05
CN104838615B (en) 2017-08-18
KR101636496B1 (en) 2016-07-05
WO2014091592A1 (en) 2014-06-19
KR20150084917A (en) 2015-07-22

Similar Documents

Publication Publication Date Title
CN104838615A (en) Signal synchronization system, node synchronization system, signal synchronization method, and node synchronization method
JP6152920B2 (en) Programmable controller system, its controller
JP6523497B1 (en) Master controller and synchronous communication system using the same
EP2222003B1 (en) Field control system
JP5935903B2 (en) Control system, master programmable controller, slave programmable controller, and control method
CN101196731A (en) Motion control timing models
EP4050436A1 (en) Control device and distributed control system
US20220413474A1 (en) Control system
US20220147022A1 (en) Control system
US11782431B2 (en) Control device and non-transitory computer-readable recording medium recording program
US20140019793A1 (en) Strictly increasing virtual clock for high-precision timing of programs in multiprocessing systems
KR20190074026A (en) Synchronization method and system among multiple MCUs in EtherCAT-based slave system
JP6045950B2 (en) Communication control device and communication system
Tovar et al. Distributed computing for the factory-floor: a real-time approach using WorldFIP networks
JP4961589B2 (en) Network system and slave synchronization method
JP2011123688A (en) Synchronizing programmable controller and synchronizing programmable controller system
KR20170125405A (en) Time synchronization device and time synchronization system
CN116800366A (en) Clock synchronization method, device and storage medium
CN104115450B (en) Signal synchronization system, multiprocessor and node synchronization system
CN112564938B (en) Equipment controller reconfigurable system based on EtherCAT protocol and implementation method
JP5662119B2 (en) Node system and monitoring node
WO2021240783A1 (en) Time correction device, time correction method, and time correction program
EP4199385A1 (en) Clock synchronization method and device in distributed system, and system
CN113534887A (en) Method and device for time synchronization among board cards based on real-time bus and electronic equipment
Mushenski Analysis and Modeling of Servo Motor Controls in Military Vehicle Control Systems Update

Legal Events

Date Code Title Description
PB01 Publication
EXSB Decision made by sipo to initiate substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant