CN104835720B - A kind of semiconductor structure and forming method thereof - Google Patents
A kind of semiconductor structure and forming method thereof Download PDFInfo
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- CN104835720B CN104835720B CN201510172229.8A CN201510172229A CN104835720B CN 104835720 B CN104835720 B CN 104835720B CN 201510172229 A CN201510172229 A CN 201510172229A CN 104835720 B CN104835720 B CN 104835720B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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Abstract
The present invention provides a kind of semiconductor structure and forming method thereof, pass through the fringe region formation trapping layer in Semiconductor substrate, so that semiconductor substrate edge region can not long monocrystalline during epitaxial growth, ensure that Semiconductor substrate edge forms breach, crack, chipping even fragment because the crystal defect of the presence such as chamfer quality will not be exaggerated in outer Yanzhong, also be not in that extension hat etc. is abnormal, solve and occur the problem of photoetching such as photoresist is accumulated, spin coating is bad, exposure is apprehensive are abnormal in spin coating and exposure technology.
Description
Technical field
The invention belongs to semiconductor fabrication process technical field, it is related to a kind of semiconductor structure and forming method thereof.
Background technology
The substrate that IC manufacturing is used, after cutting into the silicon chip substrate with specific thicknesses from monocrystal rod,
There is mechanical stress and thermal stress in the surface of silicon chip, be easily created damage and slip dislocation etc. abnormal, it usually needs pass through
It can just be made moderate progress after strict last handling process.In silicon chip edge, the stress of silicon chip and the especially prominent of impaired performance, it is necessary to
Silicon chip edge using the grinder buffing with particular edge contouring by cutting, makes silicon chip edge form specific angle and shape
Looks, and then the mechanical stress of silicon chip edge is released, damaged and defect is reduced, and make the stress of silicon chip edge unit area
Reduce, this process is referred to as chamfering.Chamfer process is also to match somebody with somebody after quality and chamfering in the process of a mechanical wear, chamfer process
The quality of set technique determines stress, defect and the clean-up performance of silicon chip edge, has important work to the manufacturing of integrated circuit
With.
In the high-voltage products such as power device VDMOS, IGBT, thick epitaxy technique is the critical process for realizing that device is pressure-resistant.
During actual epitaxial growth, because silicon chip edge crystal orientation is different, have than single crystal surfaces faster during epitaxial growth
Growth rate, thus the epitaxial thickness of silicon chip edge is bigger than the epitaxial thickness of silicon chip center single-crystal surface, forms extension
It is preced with phenomenon.Simultaneously because stress, particle and the out-of-flatness problem of the not good presence of silicon chip edge quality, are passed through during epitaxial growth
It is often abnormal in silicon chip edge formation slip dislocation etc.." extension hat " that silicon chip edge occurs or the anomaly such as slip dislocation with
The increase of the thickness of extension becomes more serious.
Specifically as depicted in figs. 1 and 2, over the semiconductor substrate 10 after grown epitaxial layer 20, the edge of Semiconductor substrate 10 is (such as
Region shown in dotted line circle in Fig. 1) there is extension hat (silicon is raised) A and slip dislocation B.Wherein, the centre bit of Semiconductor substrate 10
The thickness for the epitaxial layer 20 put is Tepi, and the thickness of the epitaxial layer 20 of the center of Semiconductor substrate 10 is Tepi, semiconductor lining
The surface of epitaxial layer 20 of the center of bottom 10 and the epi-layer surface (extension crown portion) of marginal position have a difference in height h1, half
The surface of epitaxial layer 20 of the center of conductor substrate 10 is with having a difference in height h2, whole Semiconductor substrate at the top of slip dislocation B
The epitaxial layer gross thickness at 10 edges is T.Because extension hat and slip dislocation are raised higher in epi-layer surface, in spin coating and exposure
Easily occur photoresist accumulation in technique, caused by spin coating is bad, exposure is apprehensive etc. photoetching it is abnormal, particularly in needs with partly leading
The edge of body substrate 10, which has in the equipment of Mechanical Contact, easily there is breach, crack, the chipping even exception of fragment, simultaneously because sliding
Shifting edge in wrong presence, the transfer process of Semiconductor substrate 10 and being very easy to collide causes breach and fragment.
The content of the invention
It is an object of the present invention to form scarce because the crystal defect of the presence such as chamfer quality will not be exaggerated in outer Yanzhong
Mouth, crack, chipping even fragment, are also not in that extension hat etc. is abnormal, solve photoresist heap occur in spin coating and exposure technology
The problem of product, photoetching exception such as spin coating is bad, exposure is apprehensive.
In order to solve the above problems, the present invention provides a kind of semiconductor structure, including：
Semiconductor substrate with monocrystalline silicon surface；
It is formed at the trapping layer in the semiconductor substrate edge region；And
It is formed at the first epitaxial layer and shape of the central area of the Semiconductor substrate simultaneously by epitaxial growth technology
The second epitaxial layer described in Cheng Yu above trapping layer.
Optionally, in described semiconductor structure, the Semiconductor substrate is monocrystalline substrate, SOI substrate, germanium silicon lining
Doped with N-type impurity ion or p type impurity ion in bottom, III-group Ⅴ element compound substrate, the Semiconductor substrate.
Optionally, in described semiconductor structure, the material of the trapping layer is silica, silicon nitride or polycrystalline
Silicon.
Optionally, in described semiconductor structure, the trapping layer is in annular shape.The width of the trapping layer is 0.5
Between~5mm.The thickness of the trapping layer existsBetween.
The present invention also provides a kind of forming method of semiconductor structure, including：
There is provided one has the Semiconductor substrate of monocrystalline silicon surface；
In the fringe region formation trapping layer of the Semiconductor substrate；And
Epitaxy technique growth is carried out, the first epitaxial layer is formed in the intermediate region of the Semiconductor substrate, is prevented described
The second epitaxial layer is formed on layer.
Optionally, in the forming method of described semiconductor structure, the Semiconductor substrate is monocrystalline substrate, SOI
It is miscellaneous doped with N-type impurity ion or p-type in substrate, germanium silicon substrate, III-group Ⅴ element compound substrate, the Semiconductor substrate
Matter ion.
Optionally, in the forming method of described semiconductor structure, formed in the fringe region of the Semiconductor substrate
The step of trapping layer, includes：
Trapping layer is formed on the semiconductor substrate surface；
By spin coating, exposure, etching and degumming process, the trapping layer of the Semiconductor substrate intermediate region is removed, only
Retain the trapping layer in the semiconductor substrate edge region.
Optionally, in the forming method of described semiconductor structure, using dry method anisotropic etching technique, institute is removed
State the trapping layer of Semiconductor substrate intermediate region.
Optionally, in the forming method of described semiconductor structure, the prevention of the fringe region of the Semiconductor substrate
The material of layer is silica, silicon nitride or polysilicon.The trapping layer of the fringe region of the Semiconductor substrate is wide in annular shape
Degree is between 0.5~5mm.
Optionally, in the forming method of described semiconductor structure, the epitaxial growth technology using SiCL4,
SiHCL3, SiH2CL2 or SiH4 gas, using borine or phosphine as doped source, epitaxial growth temperature 950~1200 DEG C it
Between, epitaxial growth rate is between 0.1~5 μm.
Optionally, in the forming method of described semiconductor structure, 10~200 μm of first epitaxy layer thickness.
Optionally, in the forming method of described semiconductor structure, before progress epitaxial growth technology, using HCL gas
Body is handled the semiconductor substrate surface,
Optionally, in the forming method of described semiconductor structure, chemical machinery throwing is carried out to the Semiconductor substrate
Light processing.
The present invention passes through the fringe region formation trapping layer in Semiconductor substrate so that the semiconductor during epitaxial growth
Substrate edge area can not long monocrystalline, because the defect of the presence such as chamfer quality will not be exaggerated, be also not in extension hat etc.
It is abnormal, solve and occur the problem of photoetching such as photoresist is accumulated, spin coating is bad, exposure is apprehensive are abnormal in spin coating and exposure technology.
Brief description of the drawings
Referring to the drawings, according to following detailed description, the present invention can be more clearly understood from.For the sake of clarity, scheme
In the relative thickness of each layer and the relative size of given zone be not drawn to draw.In the accompanying drawings：
Fig. 1 is that extension hat and the schematic diagram of slip dislocation occurs in semiconductor substrate edge area after traditional epitaxy technique；
Fig. 2 is the enlarged diagram of the fringe region of Semiconductor substrate in Fig. 1；
Fig. 3 is the schematic flow sheet of the forming method of semiconductor structure in one embodiment of the invention；
Fig. 4 is the cross-sectional view of Semiconductor substrate in one embodiment of the invention；
Fig. 5 is the cross-sectional view formed on semiconductor substrate surface after trapping layer in one embodiment of the invention；
Fig. 6 is the cross-section structure signal formed in semiconductor substrate edge region after trapping layer in one embodiment of the invention
Figure；
Fig. 7 is the schematic top plan view after forming trapping layer in semiconductor substrate edge region in one embodiment of the invention；
Fig. 8 is the cross-section structure signal of semiconductor structure for carrying out in one embodiment of the invention being formed after epitaxial growth technology
Figure；
Fig. 9 is the schematic top plan view of semiconductor structure for carrying out in one embodiment of the invention being formed after epitaxial growth technology.
Embodiment
In order to facilitate the understanding of the purposes, features and advantages of the present invention, below in conjunction with the accompanying drawings to the present invention
Embodiment be described in detail.
As shown in Figure 8 and Figure 9, the present invention provides a kind of semiconductor structure, including：
Semiconductor substrate 30 with monocrystalline silicon surface；
It is formed at the trapping layer 31 of the fringe region of Semiconductor substrate 30；
By epitaxial growth technology simultaneously be formed at the Semiconductor substrate 30 central area the first epitaxial layer 33a with
And it is formed at the second epitaxial layer 33b of the top of trapping layer 31.
Referring to Fig. 3, the present invention also provides a kind of forming method of semiconductor structure, comprised the following steps：
S11, offer one have the Semiconductor substrate of monocrystalline silicon surface；
S12, the fringe region formation trapping layer in the Semiconductor substrate；
S13, progress epitaxy technique growth, form the first epitaxial layer, described in the intermediate region of the Semiconductor substrate
The second epitaxial layer is formed on trapping layer.
Semiconductor structure of the present invention and forming method thereof is described in detail with reference to diagrammatic cross-section.
Many details are elaborated in following description to fully understand the present invention.But the present invention can be to be much different from
Other manner described here is implemented, and those skilled in the art can do similar push away in the case of without prejudice to intension of the present invention
Extensively, therefore the present invention is not limited to the specific embodiments disclosed below.
With reference to shown in Fig. 3 and Fig. 4, performing step S11, there is provided the Semiconductor substrate 30 that one has monocrystalline silicon surface.
Specifically, the Semiconductor substrate 30 can be monocrystalline substrate, SOI substrate, germanium silicon substrate, III-group Ⅴ element
Compound substrate, wherein can be doped with N-type impurity ion or p type impurity ion.Use to form power in the present embodiment
The conventional N-type of device<100>The Semiconductor substrate of crystal orientation.Certainly, the present invention does not limit the type of Semiconductor substrate 30, as long as
It is that, with monocrystalline silicon surface in order to carry out epitaxy technique growth on the monocrystalline silicon surface, reality can basis in growing
Part category selects corresponding Semiconductor substrate.
It is preferred that, the Semiconductor substrate 30 has carried out chamfer angle technique, and the chamfer angle technique, which refers to use, has particular edge
The edge of the grinder buffing Semiconductor substrate 30 of contouring, makes the edge of Semiconductor substrate 30 form specific angle and pattern,
And then the mechanical stress at the edge of Semiconductor substrate 30 is released, damaged and defect is reduced, and make the side of Semiconductor substrate 30
The stress of edge unit area is reduced.As shown in figure 3, after chamfering, the edge of Semiconductor substrate 30 has a radian.
Then, step S12 is performed, in the fringe region formation trapping layer 31 of the Semiconductor substrate 30.
Specifically as shown in Figure 5 and Figure 6, certain thickness trapping layer 31 is first formed on the surface of Semiconductor substrate 30, then
By spin coating, exposure, etching and degumming process, the trapping layer 31 of the intermediate region of Semiconductor substrate 30 is removed, exposure half is formed
The first window area 32 of conductor substrate 30, only retains the trapping layer 31 of the fringe region of Semiconductor substrate 30.
Wherein, the trapping layer 31 can be different from the Semiconductor substrate 30 for silica, silicon nitride, polysilicon etc.
Material, certainly, the present invention do not limit its material, as long as can realize selectivity with the material difference of Semiconductor substrate 30
The purpose of extension.
Before epitaxial growth, semiconductor substrate surface is handled according to HCL gases, if trapping layer 31
Thinner thickness does not have trapping layer effect easily by HCL gas attacks；Meanwhile, the thickness of trapping layer 31 be also not suitable for it is too thick, it is too thick
Trapping layer easily form projection at its edge after epitaxial growth, therefore, the thickness of trapping layer 31 described in the present embodiment preferably existsBetween.
As shown in fig. 7, the trapping layer 31 of the fringe region of Semiconductor substrate 30 is in annular shape, its width L1 preferably exists
Between 0.5~5mm, if the too small fringe regions for being unfavorable for covering all Semiconductor substrate 30 of its width L1, if it is too big
More die area can be lost.Certainly, the present invention in the fringe region of Semiconductor substrate 30 trapping layer 31 be not limited to it is above-mentioned
Numerical value, can be determined according to Semiconductor substrate size and specific production technology demand etc..
In the present embodiment, without side washing technique after spin processes, before exposure technology.In the prior art, in semiconductor system
During making, the phenomenon such as particle, white residue in order to reduce semiconductor substrate edge region before spin coating post-exposure, is generally removed
The photoresist in semiconductor substrate edge region, is generally adopted by EBR solution, whole fringe region is showed in a photolithographic process
For opened areas.But, semiconductor substrate edge region needs to protect by trapping layer in the present embodiment, so the semiconductor
The region of edges of substrate need not carry out side washing processing.
In the present embodiment, using dry method anisotropic etching technique, the trapping layer of the intermediate region of Semiconductor substrate 30 is removed,
The dry method anisotropic etching is conducive to making trapping layer edge pattern precipitous, makes hetero-epitaxy mistake during subsequently epitaxial growing
Journey boundary becomes apparent from, and reduces defect.
Carry out before epitaxial growth technology, semiconductor substrate surface can be handled using HCL gases, the HCL gas
Body has two effects：One is that epitaxial chamber can be cleaned, and two be that can remove the impurity on the surface of Semiconductor substrate 30.
Then, step S13 is performed, epitaxial growth technology is carried out, the is formed in the intermediate region of the Semiconductor substrate 30
One epitaxial layer 33a, in the second epitaxial layer 33b of fringe region formation for the Semiconductor substrate 30 protected with trapping layer 31.
In the application, the first epitaxial layer 33a is identical with the material of the Semiconductor substrate 30, is monocrystalline silicon, and
The fringe region of Semiconductor substrate 30 is protected by trapping layer 31, thus the region can not long monocrystalline, prevent in epitaxial process
The second epitaxial layer 33b that the top of layer 31 is formed is polysilicon, thus, the fringe region of Semiconductor substrate 30 is deposited due to chamfer quality etc.
Defect will not be exaggerated during epitaxial growth, be also not in that extension hat etc. is abnormal.
With reference to shown in Fig. 8 and Fig. 9, in epitaxial process is carried out, due to the silicon of the intermediate region of Semiconductor substrate 30
The direction of trapping layer 31 extension that monocrystalline can retain along crystal orientation, thus the first epitaxial layer 33a ultimately formed side is typically to incline
Oblique, i.e. the first epitaxial layer 33a is structure wide at the top and narrow at the bottom, and the second epitaxial layer 33b is in annular shape, and the second epitaxial layer 33b
The structure of upper narrow complimentary close (the width L2 at the top of the second epitaxial layer 33b is less than the width of its bottom).
It is preferred that, the thickness of the first epitaxial layer 33a is between 10~200 μm, and the epitaxial growth technology is used
SiCL4, SiHCL3, SiH2CL2 or SiH4 gas, can using borine or phosphine as doped source, epitaxial growth temperature 950~
Between 1200 DEG C, epitaxial growth rate is between 0.1~5 μm/min.
Find that after epitaxial growth technology, the first epitaxial layer 33a and the second epitaxial layer 33b height are basic through experiment
Unanimously, and the first epitaxial layer 33a and the second epitaxial layer 33b are relatively flat.Certainly, in order to obtain more preferably profile pattern,
Carry out after epitaxial growth, can also be chemically-mechanicapolish polished (CMP) processing.In the present embodiment, the chemically mechanical polishing work
Skill, using the polishing fluid that can be chemically reacted with polysilicon and monocrystalline silicon, the selection ratio of polysilicon and monocrystalline silicon elects 1 as:1,
Grinding-material is used for the alkaline silicon dioxide ultrafine particles containing ammonium hydroxide (NH4OH), the pH value of the NH4OH for 9~
11, its polishing disk rotating speed is 10~200 circles/Min, and polish temperature is 20~50 degree, and polish pressure is 0.5~10 newton/cm-2。
In summary, the present invention is by the fringe region formation trapping layer in Semiconductor substrate, during epitaxial growth
Semiconductor substrate edge region can not long monocrystalline, be also not in outer because the defect of the presence such as chamfer quality will not be exaggerated
Prolong hat etc. abnormal, solve in spin coating and exposure technology easily there is photoresist accumulation, spin coating is bad, exposure is apprehensive etc., and photoetching is different
Often the problem of, reduce equipment contact in process of production and the caused semiconductor substrate edge breach of collision, crack, chipping even
The risk of fragment.
Although the embodiment of the present invention is disclosed as above with preferred embodiment, its be not for limiting claim, it is any
Those skilled in the art without departing from the spirit and scope of the present invention, can make possible variation and modification, therefore this
The scope that the protection domain of invention should be defined by the claims in the present invention is defined.
Claims (16)
1. a kind of semiconductor structure, it is characterised in that including：
Semiconductor substrate with monocrystalline silicon surface；
It is formed at the trapping layer in the semiconductor substrate edge region；
It is formed at the first epitaxial layer of the central area of the Semiconductor substrate simultaneously by epitaxial growth technology and is formed at
The second epitaxial layer above the trapping layer, after epitaxial growth technology, the top of first epitaxial layer and the second epitaxial layer
Face is basically identical.
2. semiconductor structure as claimed in claim 1, it is characterised in that the Semiconductor substrate is monocrystalline substrate, SOI linings
Doped with N-type impurity ion or p type impurity in bottom, germanium silicon substrate, III-group Ⅴ element compound substrate, the Semiconductor substrate
Ion.
3. semiconductor structure as claimed in claim 1, it is characterised in that the material of the trapping layer is silica, nitridation
Silicon or polysilicon.
4. semiconductor structure as claimed in claim 1, it is characterised in that the trapping layer is in annular shape.
5. semiconductor structure as claimed in claim 4, it is characterised in that the width of the trapping layer is between 0.5~5mm.
6. a kind of forming method of semiconductor structure, it is characterised in that including：
There is provided one has the Semiconductor substrate of monocrystalline silicon surface；
In the fringe region formation trapping layer of the Semiconductor substrate；
Epitaxy technique growth is carried out, the first epitaxial layer is formed in the intermediate region of the Semiconductor substrate, on the trapping layer
The second epitaxial layer is formed, after epitaxial growth technology, the top surface of first epitaxial layer and the second epitaxial layer is basically identical.
7. the forming method of semiconductor structure as claimed in claim 6, it is characterised in that the Semiconductor substrate is monocrystalline silicon
Doped with N-type impurity ion in substrate, SOI substrate, germanium silicon substrate, III-group Ⅴ element compound substrate, the Semiconductor substrate
Or p type impurity ion.
8. the forming method of semiconductor structure as claimed in claim 6, it is characterised in that at the edge of the Semiconductor substrate
The step of region forms trapping layer includes：
Trapping layer is formed on the semiconductor substrate surface；
By spin coating, exposure, etching and degumming process, the trapping layer of the Semiconductor substrate intermediate region is removed, is only retained
The trapping layer in the semiconductor substrate edge region.
9. the forming method of semiconductor structure as claimed in claim 8, it is characterised in that use dry method anisotropic etching work
Skill, removes the trapping layer of the Semiconductor substrate intermediate region.
10. the forming method of semiconductor structure as claimed in claim 6, it is characterised in that the edge of the Semiconductor substrate
The material of the trapping layer in region is silica, silicon nitride or polysilicon.
11. the forming method of semiconductor structure as claimed in claim 6, it is characterised in that the edge of the Semiconductor substrate
The trapping layer in region is in annular shape.
12. the forming method of semiconductor structure as claimed in claim 11, it is characterised in that the edge of the Semiconductor substrate
The width of the trapping layer in region is between 0.5~5mm.
13. the forming method of semiconductor structure as claimed in claim 6, it is characterised in that the epitaxial growth technology is used
SiCL4, SiHCL3, SiH2CL2 or SiH4 gas, using borine or phosphine as doped source, epitaxial growth temperature 950~
Between 1200 DEG C, epitaxial growth rate is between 0.1~5 μm.
14. the forming method of semiconductor structure as claimed in claim 6, it is characterised in that first epitaxy layer thickness 10
~200 μm.
15. the forming method of semiconductor structure as claimed in claim 6, it is characterised in that before progress epitaxial growth technology,
The semiconductor substrate surface is handled using HCL gases.
16. the forming method of semiconductor structure as claimed in claim 6, it is characterised in that carried out to the Semiconductor substrate
Chemical mechanical polish process.
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| CN111162040A (en) * | 2020-01-02 | 2020-05-15 | 长江存储科技有限责任公司 | Method for manufacturing semiconductor device |
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| WO2008067854A1 (en) * | 2006-12-08 | 2008-06-12 | Lumilog | Method for manufacturing a single crystal of nitride by epitaxial growth on a substrate preventing growth on the edges of the substrate |
| US8928120B1 (en) * | 2013-06-28 | 2015-01-06 | Taiwan Semiconductor Manufacturing Company Limited | Wafer edge protection structure |
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