CN104822197A - Analog dimming control method, control circuit and LED drive circuit using the analog dimming control method and control circuit - Google Patents
Analog dimming control method, control circuit and LED drive circuit using the analog dimming control method and control circuit Download PDFInfo
- Publication number
- CN104822197A CN104822197A CN201510189332.3A CN201510189332A CN104822197A CN 104822197 A CN104822197 A CN 104822197A CN 201510189332 A CN201510189332 A CN 201510189332A CN 104822197 A CN104822197 A CN 104822197A
- Authority
- CN
- China
- Prior art keywords
- pwm pulse
- pulse signal
- current
- clock
- current unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
Landscapes
- Circuit Arrangement For Electric Light Sources In General (AREA)
Abstract
The invention discloses an analog dimming control method, a control method and an LED drive circuit using the analog dimming control method and the control circuit. When a clock signal is used to represent a PWM pulse signal of current dimming brightness to perform clocking, a clock counting result representing information of the duty ratio of the PWM pulse signal, and the magnitude of current flowing through a switching circuit is adjusted according to the clock counting result, so that the magnitude of current flowing through an LED load is controlled, thereby rapidly obtaining precise analog dimming current. The method does not need a large filter, and allows the PWM pulse signal to have a relatively wide frequency range.
Description
Technical field
The present invention relates to a kind of power electronic technology, more particularly, relate to a kind of adjusting control circuit be applied in LED driver.
Background technology
Simulation light modulation refers to that control signal is analog quantity instead of digital quantity.Under certain brightness of LED setting, the brightness of lamp is all the same in the time of any length, the meaning that Here it is " simulation ".
In prior art, the control method of simulation light modulation is generally utilize RC filter pwm pulse signal to be filtered into a direct current signal, thus obtain simulating dimming effect, its basic theory diagram is as shown in Figure 1: wherein, the complementary conducting of controlled transistor M1 and controlled transistor M2, the on off state of controlled transistor M1 is consistent with the high level of pwm pulse signal, and the on off state of controlled transistor M2 is consistent with the low level of pwm pulse signal.The result that the duty ratio D that so just can obtain comprising in pwm pulse signal is multiplied with reference voltage V set.The voltage of resistance R and electric capacity C1 to the points of common connection place of controlled transistor M1 and controlled transistor M2 carries out filtering operation, thus generates simulation dim signal Vref in one end of electric capacity C1.The in-phase input end of operational amplifier receives simulation dim signal Vref, and inverting input receives the sampled signal V of the present drive current characterizing LED load
iLEDthe error signal of output compensates computing through building-out capacitor C2, the voltage of building-out capacitor C2 one end is the control signal of brightness adjustment control transistor M3, brightness adjustment control transistor M3 is under the control of this control signal, be operated in linear model, flow through corresponding LED drive current, reach the object of light modulation.
But the weak point of the method is: when pwm pulse signal frequency more hour, corresponding RC time constant needs larger, just can reach good filter effect, and the ripple of namely simulating dim signal Vref could be smaller, is similar to a direct voltage.And the size of RC time constant and RC area proportional, so when pwm pulse signal frequency more hour, required RC area is larger.And chip internal generally RC area cannot be done very large, thus when without filtered external, the frequency of pwm pulse signal receives serious restriction.
Summary of the invention
In view of this, the invention provides a kind of simulation dimming controlling method and circuit, this analog light-adjusting circuit adopts digital method to obtain clock count result corresponding to the duty ratio of pwm pulse signal, and flow through the size of LED load electric current according to described clock count output control, thus can to solve in prior art due to chip area the problem that the frequency of pwm pulse signal is restricted.
First aspect, provide a kind of simulation dimming controlling method, be applied in LED driver, it is characterized in that, described dimming controlling method comprises:
By a clock signal, clock timing is carried out to the pwm pulse signal characterizing current light modulation brightness, obtain the clock count result characterizing pwm pulse signal duty cycle information;
The size flowing through the electric current of switching circuit is regulated, to control the size flowing through LED load electric current according to described clock count result;
Wherein, the frequency of described clock signal is the Nth power times of two of pwm pulse signal frequency,
Described switching circuit is made up of the current unit parallel connection of N road, and the size of current that described N road current unit flows through under the same conditions is different.
Preferably, described clock count result is N bit, and described N bit characterizes the size of described pwm pulse signal duty ratio.
Preferably, regulate the size flowing through the electric current of switching circuit according to described clock count result, comprising:
The clock count result of described N bit and the conducting state one_to_one corresponding of described N road current unit, when a certain position of N bit is 1, the current unit conducting of corresponding figure place; When a certain position of N bit is 0, the current unit of corresponding figure place disconnects.
Preferably, the size of current that described N road current unit flows through under the same conditions become common ratio be two geometric ratio relation.
Preferably, described clock signal is the clock signal by obtaining after the Nth power frequency multiplication of pwm pulse signal two.
Preferably, described clock signal is external timing signal.
Second aspect, provide a kind of simulation adjusting control circuit, be applied in LED driver, it is characterized in that, described adjusting control circuit comprises:
Clock counting circuit, carries out clock timing in order to receive a clock signal to the pwm pulse signal characterizing current light modulation brightness, obtains the clock count result characterizing pwm pulse signal duty cycle information;
Switching circuit, in order to regulate the size flowing through LED load electric current according to described clock count result;
Wherein, the frequency of described clock signal is the Nth power times of two of pwm pulse signal frequency,
Described switching circuit is made up of the current unit parallel connection of N road, and the size of current that described N road current unit flows through under the same conditions is different.
Preferably, described clock count result is N bit, and described N bit characterizes the size of described pwm pulse signal duty ratio.
Preferably, the clock count result of described N bit and the conducting state one_to_one corresponding of described N road current unit, when a certain position of N bit is 1, the current unit conducting of corresponding figure place; When a certain position of N bit is 0, the current unit of corresponding figure place disconnects.
Preferably, the size of current that described N road current unit flows through under the same conditions become common ratio be two geometric ratio relation.
Preferably, described clock signal is the clock signal by obtaining after the Nth power frequency multiplication of pwm pulse signal two.
Preferably, described current unit is composed in series by controlled transistor and sampling resistor.
The third aspect, provides a kind of LED drive circuit, in order to driving LED load, it is characterized in that, comprises the simulation adjusting control circuit according to any one of claim 7 to 12.
The technology of the present invention one clock signal carries out clock timing to the pwm pulse signal characterizing current light modulation brightness, obtains the clock count result characterizing pwm pulse signal duty cycle information; And the size flowing through the electric current of switching circuit is regulated according to described clock count result, to control the size flowing through LED load electric current, thus light modulation electric current can be simulated accurately rapidly, the method without the need to large filter, and allows pwm pulse signal to have wider frequency range.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only embodiments of the invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to the accompanying drawing provided.
Fig. 1 is the theory diagram of analog light-adjusting circuit in prior art;
Fig. 2 is the circuit structure diagram of the simulation adjusting control circuit according to the technology of the present invention;
Fig. 3 is the circuit structure diagram of frequency multiplier circuit;
Fig. 4 is the circuit structure diagram of clock counting circuit;
Fig. 5 is the working waveform figure of clock counting circuit;
Embodiment
Based on embodiment, present invention is described below, but the present invention is not restricted to these embodiments.In hereafter details of the present invention being described, detailedly describe some specific detail sections.Do not have the description of these detail sections can understand the present invention completely for a person skilled in the art yet.In order to avoid obscuring essence of the present invention, known method, process, flow process, element and circuit do not describe in detail.
In addition, it should be understood by one skilled in the art that the accompanying drawing provided at this is all for illustrative purposes, and accompanying drawing is not necessarily drawn in proportion.
Meanwhile, should be appreciated that in the following description, " circuit " refers to the galvanic circle connected and composed by electrical connection or electromagnetism by least one element or electronic circuit.When " being connected to " another element when claiming element or circuit or claiming element/circuit " to be connected to " between two nodes, it can be directly couple or be connected to another element or can there is intermediary element, the connection between element can be physically, in logic or its combine.On the contrary, " be directly coupled to " when claiming element or " being directly connected to " another element time, mean that both do not exist intermediary element.
Unless the context clearly requires otherwise, similar words such as " comprising ", " comprising " otherwise in whole specification and claims should be interpreted as the implication that comprises instead of exclusive or exhaustive implication; That is, be the implication of " including but not limited to ".
In describing the invention, it is to be appreciated that term " first ", " second " etc. are only for describing object, and instruction or hint relative importance can not be interpreted as.In addition, in describing the invention, except as otherwise noted, the implication of " multiple " is two or more.
Fig. 2 is the circuit structure diagram of the simulation adjusting control circuit according to the technology of the present invention, and described simulation adjusting control circuit 20 comprises: clock counting circuit 201, switching circuit 202 and error compensation circuit 203.
Wherein, clock counting circuit 201 carries out clock timing in order to receive a clock signal clk to the pwm pulse signal characterizing current light modulation brightness, obtain the clock count result Vcount characterizing pwm pulse signal duty cycle information, clock count result Vcount is by VN, VN-1 ... the binary number of V2, V1 composition, in the present embodiment, VN is high-order, and V1 is low level.Described binary clock count results Vcount is corresponding with the duty ratio of current pwm pulse signal, utilizes this binary clock count results Vcount, can control the size flowing through LED load electric current.
Described switching circuit 202, in order to regulate the size flowing through LED load electric current according to described clock count result Vcount.Described switching circuit 202 is made up of the current unit parallel connection of N road, every road current unit is composed in series by controlled transistor and sampling resistor, in the current unit of every road, the first end of controlled transistor is connected in parallel on same node, second end is connected with the first end of sampling resistor, and the second end of sampling resistor is connected to ground.
Wherein, the frequency of described clock signal is the Nth power times of two of described pwm pulse signal frequency, and N is the number of the current unit forming switching circuit 202.
It should be noted that, employing frequency is the Nth power clock signal doubly of two of described pwm pulse signal frequency, can by the cycle normalization of the pwm pulse signal of different frequency.Specifically, frequency is utilized to be that the Nth power clock signal doubly of two of current pwm pulse signal frequency carries out timing to the time of current pwm pulse signal frequency between high period, what the clock count result Vcount obtained characterized is the time of pwm pulse signal at high level and the ratio in whole pwm pulse signal cycle, i.e. the duty cycle information of current pwm pulse signal.If the frequency of pwm pulse signal changes to some extent, the frequency of clock signal also can along with change, but the clock pulse number in the whole cycle can not change, or 2
nindividual, therefore under different pwm pulse signals, clock count result all can characterize the duty cycle information of current pwm pulse signal, reaches normalized for the cycle of pwm pulse signal object.
The size of current that in switching circuit 202, N road current unit flows through under the same conditions is different, and the conducting state one_to_one corresponding of the clock count result of described N bit and described N road current unit, when a certain position of N bit is 1, the switch of corresponding figure place closes the current unit conducting making corresponding figure place; When a certain position of N bit is 0, the switch of corresponding figure place disconnects and the current unit of corresponding figure place is disconnected.Switching circuit 202 and LED load are connected in series, so the electric current flowing through switching circuit 202 is the electric current flowing through LED load.Particularly, suppose that flowing through the total size of current of LED load is M, when the lowest order V1 of the clock count result Vcount of binary number is 1, switch S 11 and switch S 12 close simultaneously, drive singal Vg is connected to the control end of controlled transistor Q1, then by the first current unit conducting that controlled transistor Q1 and sampling resistor R1 is in series, the size of current flowing through it is M/2
n; When the second V2 of the clock count result Vcount of binary number is 1, switch S 21 and switch S 22 close simultaneously, drive singal Vg is connected to the control end of controlled transistor Q2, then by the second current unit conducting that controlled transistor Q2 and sampling resistor R2 is in series, the size of current flowing through it is M/2
n-1; By that analogy, when the highest order VN of the clock count result Vcount of binary number is 1, switch S N1 and switch S N2 closes simultaneously, drive singal Vg is connected to the control end of controlled transistor QN, then by the N current unit conducting that controlled transistor QN and sampling resistor RN is in series, the size of current flowing through it is M/2.According to this rule, can be summarized as: when n-th Vn of the clock count result Vcount of binary number is 1, switch S n1 and switch S n2 closes simultaneously, drive singal Vg is connected to the control end of controlled transistor Qn, then by the n-th current unit conducting that controlled transistor Qn and sampling resistor Rn is in series, the size of current flowing through this road is M/2
n-n+1, namely described N road current unit is under the same conditions, from the first via to the size of current that N road is flow through become common ratio be two geometric ratio relation.Described identical condition refers to, described N road current unit receives same driving voltage V
lED, and the controlled transistor in the current unit of described N road has identical driving voltage at synchronization.
In circuit design, realizing the size of current diverse ways that in described switching circuit 202, N road current unit flows through under the same conditions can be: choose controlled transistor Q1 ~ QN and be of a size of, be operated in linear zone and under same gate-source voltage Vg drives time, conducting resistance becomes a group transistor of the proportionate relationship of Gongwei two.Further, in order to the size of current realizing N road current unit become common ratio be two geometric ratio relation, the size of the sampling resistor of connecting in each road correspondingly become from the first via to N road common ratio be 1/2nd geometric ratio relation, i.e. R1=2R2=...=2
n-1rN.
Error compensation circuit 203, comprise trsanscondutance amplifier GM1 and building-out capacitor C3, the in-phase end of trsanscondutance amplifier GM1 receives predeterminated voltage Vref1, and end of oppisite phase receives the current sampling signal Vs of N road circuital current unit, and described current sampling signal Vs is the voltage of each sampling resistor first end.The electric current flow through due to each road current unit become from the first via to N road common ratio be two geometric ratio relation, and the resistance of the sampling resistor of connecting in the current unit of each road become from the first via to N road common ratio be 1/2nd geometric ratio relation, so, in circuit working process, during synchronization, the current sampling signal of each road current unit is substantially equal.Certainly, be understandable that, in order to the current sampling signal of Shi Ge road current unit is completely equal, also likely increase other balance module in circuit, do not elaborate at this.
Error compensation circuit 203 specifically can adopt circuit as shown in Figure 2 to realize, but it is easily understood that those skilled in the art otherwise can realize concrete circuit according to above setting.
Error compensation circuit 203 is according to predeterminated voltage Vref1 and current sampling signal Vs generated error compensating signal, and described error compensating signal is the voltage at bucking voltage C3 two ends.This error compensating signal is used as the drive singal Vg of controlled transistor in each current unit, so just can regulate by regulating the driving voltage of controlled transistor in the current unit of described N road the size of current flowing through N road current unit, the difference of current sampling signal Vs and predeterminated voltage Vref1 is minimized.
So far, foregoing circuit can form the basic scheme of the technology of the present invention.Simulation dimming controlling method provided by the invention and circuit, adopt a clock signal to carry out clock timing to the pwm pulse signal characterizing current light modulation brightness, obtains the clock count result characterizing pwm pulse signal duty cycle information; And the size flowing through the electric current of switching circuit is regulated according to described clock count result, to control the size flowing through LED load electric current, the technology of the present invention can not only to solve in prior art due to chip area the problem that the frequency of pwm pulse signal is restricted, and light modulation electric current can be simulated accurately rapidly, the method, without the need to large filter, also allows pwm pulse signal to have wider frequency range.
It should be noted that, clock counting circuit 201 in simulation adjusting control circuit 20 receives a clock signal clk and carries out clock timing to the pwm pulse signal characterizing current light modulation brightness, described clock signal clk can be outer clocking information, also can be the clock signal by obtaining after the Nth power frequency multiplication of pwm pulse signal two.In the present embodiment, the clock signal of employing is the clock signal clk obtained after Nth power frequency multiplication by pwm pulse signal two.
Fig. 3 is the circuit structure diagram of frequency multiplier circuit.Frequency multiplier circuit 40 is in order to obtain clock signal clk by after the Nth power frequency multiplication of pwm pulse signal two, and the frequency of this clock signal clk is 2 of pwm pulse signal frequency
ndoubly.Preferably, frequency multiplier circuit 40 is phase-locked loop circuit.The frequency multiplier circuit be made up of phase-locked loop circuit comprises: the through path that phase comparator PD, filter LPF and voltage controlled oscillator VCO three part form, and by 2
nthe feedback network of the frequency plot of frequency divider composition.
The operation principle of frequency multiplier circuit is: phase comparator PD is by pwm pulse signal with through 2
nthe phase difference of the clock signal clk after frequency division converts voltage signal to and exports, the control voltage of voltage controlled oscillator is formed after low pass filter LPF filtering, what voltage controlled oscillator exported is the constant-amplitude signal very close with the frequency of required clock signal clk, described constant-amplitude signal 2
nsend into phase comparator PD with pwm pulse signal after frequency division, make the frequency of voltage controlled oscillator to the direction consecutive variations reducing Error Absolute Value by the error comparing formation by control circuit, realize phase-locked, thus reach pwm pulse signal 2
nthe object of frequency multiplication.
Fig. 4 is the circuit structure diagram of the clock counting circuit 201 in simulation adjusting control circuit 20, clock counting circuit 201 is the clock signal clk of the Nth power times pwm pulse signal frequency of two in order to utilize frequency, carries out clock timing to the pwm pulse signal characterizing current light modulation brightness.Clock counting circuit 201 comprises counting circuit 2011 and register circuit 2012.
Counting circuit 2011 is in order to when pwm pulse signal is high level, and when carrying out this period with clock signal clk, thus obtain the clock count result Vcount of high level, this clock count result is digital signal.In the present embodiment, counting circuit 2011 comprises not circuit 301 and N number of d type flip flop: D1 trigger, D2 trigger ... DN trigger.The D input of each d type flip flop is connected to the reversed-phase output of self, the reversed-phase output of each d type flip flop is connected to the clock signal input terminal of next d type flip flop, the clock signal input terminal receive clock signal CLK of D1 trigger, the reset terminal of each d type flip flop receives the pwm pulse signal through not circuit.
Register circuit 2012 in order at pwm pulse signal by being converted to the low level trailing edge moment during high level, above-mentioned clock count result Vcount is deposited.In the present embodiment, register circuit 2012 comprises single-shot trigger circuit oneshot302 and N number of d type flip flop: D1 ' trigger, D2 ' trigger ... DN ' trigger.The output signal of reference numeral d type flip flop in the D input count pick up circuit 2011 of each d type flip flop, such as: the D input of D1 ' trigger receives the output signal Q1 of D1 trigger, the D input of D2 ' trigger receives the output signal Q2 of D2 trigger.The clock signal input terminal of each d type flip flop receives single triggering signal Vp of single-shot trigger circuit oneshot output.
Clock counting circuit 201 its specifically can adopt circuit as shown in Figure 4 to realize, but it is easily understood that those skilled in the art otherwise can realize concrete circuit according to above setting.
Fig. 5 is the working waveform figure of clock counting circuit, composition graphs 5, and the operation principle of clock counting circuit 201 is described at this.Counting circuit 2011 in clock counting circuit 201 is made up of d type flip flop, because trigger has 0 and 1 two states, therefore just can represent a bit with a d type flip flop, in the present embodiment, N number of d type flip flop is together in series, then can represent that N is binary number.Get 3 for N, when pwm pulse signal is high level, if initial count result is 0 entirely, then the output Q1 of D1 trigger is 0, now
when the rising edge of first pulse of clock signal clk arrives, Q1=D1=1, after this,
be 0, when the rising edge of second pulse of clock signal clk arrives,
the Output rusults of the reversed-phase output of the clock input D1 trigger of D2 trigger
because d type flip flop is rising edge circuits for triggering, the trailing edge of Q1 is
rising edge, at this moment,
when the Output rusults of the reversed-phase output of Q2 trigger
rising edge and the trailing edge of Q2 when arriving, when the 3rd trigger will start to count, pwm pulse signal will become low level, and the reset signal now inputting each d type flip flop is for high, and counting circuit 2011 resets, and timing result resets.Register circuit 2012 in clock counting circuit 201 is also made up of d type flip flop, when pwm pulse signal becomes the arrival of low level trailing edge from high level, single-shot trigger circuit oneshot (herein for trailing edge triggers) produces a trigger impulse Vp, at the rising edge time of trigger impulse Vp, the clock count result of D input is passed to output by each d type flip flop in register circuit 2012, clock count result Vcount and binary number VN is latched before counting circuit 2011 resets count results ... V2V1, until the arrival of next cycle., be between high period at pwm pulse signal, have the pulse of 2 clock signal clks as can be seen from Fig. 5 also: in the one-period and second period of pwm pulse signal, therefore count results Vcount is 010, namely decimal numeral 2; At the one-period of pwm pulse signal with in the 3rd cycle, be between high period at pwm pulse signal, have the pulse of 4 clock signal clks, therefore count results Vcount is 100, namely decimal numeral 4.But within each pwm pulse signal cycle, have 2
3the i.e. pulse of 8 clock signal clks, achieves normalized for the cycle of the pwm pulse signal of different frequency object.So according to the clock count result in each cycle, the duty cycle information of current pwm pulse signal just can be reflected.Thus, just the counting utilizing clock signal clk to pwm pulse signal high level time can be realized, obtain clock count result Vcount and the binary number VN of digital signal ... V2V1, utilize this clock count results Vcount, the number of N road current unit conducting in control switch circuit, reaches the object regulating and flow through the size of LED load electric current.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, to those skilled in the art, the present invention can have various change and change.All do within spirit of the present invention and principle any amendment, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (13)
1. simulate a dimming controlling method, be applied in LED driver, it is characterized in that, described dimming controlling method comprises:
By a clock signal, clock timing is carried out to the pwm pulse signal characterizing current light modulation brightness, obtain the clock count result characterizing pwm pulse signal duty cycle information;
The size flowing through the electric current of switching circuit is regulated, to control the size flowing through LED load electric current according to described clock count result;
Wherein, the frequency of described clock signal is the Nth power times of two of pwm pulse signal frequency,
Described switching circuit is made up of the current unit parallel connection of N road, and the size of current that described N road current unit flows through under the same conditions is different.
2. simulate dimming controlling method according to claim 1, it is characterized in that, described clock count result is N bit, and described N bit characterizes the size of described pwm pulse signal duty ratio.
3. simulate dimming controlling method according to claim 2, it is characterized in that, regulate the size flowing through the electric current of switching circuit according to described clock count result, comprising:
The clock count result of described N bit and the conducting state one_to_one corresponding of described N road current unit, when a certain position of N bit is 1, the current unit conducting of corresponding figure place; When a certain position of N bit is 0, the current unit of corresponding figure place disconnects.
4. simulate dimming controlling method according to claim 1, it is characterized in that, the size of current that described N road current unit flows through under the same conditions become common ratio be two geometric ratio relation.
5. simulate dimming controlling method according to claim 1, it is characterized in that, described clock signal is the clock signal by obtaining after the Nth power frequency multiplication of pwm pulse signal two.
6. simulate dimming controlling method according to claim 1, it is characterized in that, described clock signal is external timing signal.
7. simulate an adjusting control circuit, be applied in LED driver, it is characterized in that, described adjusting control circuit comprises:
Clock counting circuit, carries out clock timing in order to receive a clock signal to the pwm pulse signal characterizing current light modulation brightness, obtains the clock count result characterizing pwm pulse signal duty cycle information;
Switching circuit, in order to regulate the size flowing through LED load electric current according to described clock count result;
Wherein, the frequency of described clock signal is the Nth power times of two of pwm pulse signal frequency,
Described switching circuit is made up of the current unit parallel connection of N road, and the size of current that described N road current unit flows through under the same conditions is different.
8. simulate adjusting control circuit according to claim 7, it is characterized in that, described clock count result is N bit, and described N bit characterizes the size of described pwm pulse signal duty ratio.
9. simulate adjusting control circuit according to claim 8, it is characterized in that, the clock count result of described N bit and the conducting state one_to_one corresponding of described N road current unit, when a certain position of N bit is 1, the current unit conducting of corresponding figure place; When a certain position of N bit is 0, the current unit of corresponding figure place disconnects.
10. simulate adjusting control circuit according to claim 7, it is characterized in that, the size of current that described N road current unit flows through under the same conditions become common ratio be two geometric ratio relation.
11. simulate adjusting control circuit according to claim 7, it is characterized in that, described clock signal is the clock signal by obtaining after the Nth power frequency multiplication of pwm pulse signal two.
12. simulate adjusting control circuit according to claim 7, it is characterized in that, described current unit is composed in series by controlled transistor and sampling resistor.
13. 1 kinds of LED drive circuits, in order to driving LED load, is characterized in that, comprise the simulation adjusting control circuit according to any one of claim 7 to 12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510189332.3A CN104822197B (en) | 2015-04-20 | 2015-04-20 | A kind of simulation dimming controlling method, control circuit and apply its LED drive circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510189332.3A CN104822197B (en) | 2015-04-20 | 2015-04-20 | A kind of simulation dimming controlling method, control circuit and apply its LED drive circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104822197A true CN104822197A (en) | 2015-08-05 |
| CN104822197B CN104822197B (en) | 2018-07-24 |
Family
ID=53732328
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510189332.3A Active CN104822197B (en) | 2015-04-20 | 2015-04-20 | A kind of simulation dimming controlling method, control circuit and apply its LED drive circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104822197B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107027222A (en) * | 2017-05-11 | 2017-08-08 | 南京矽力杰半导体技术有限公司 | Load current adjusting circuit and adjusting method |
| CN108207054A (en) * | 2016-12-19 | 2018-06-26 | 上海莱狮半导体科技有限公司 | The power expansion circuit and power expansion method of load |
| CN109450421A (en) * | 2018-12-17 | 2019-03-08 | 上海艾为电子技术股份有限公司 | A kind of analog switch opens circuit and method |
| CN111090965A (en) * | 2018-10-23 | 2020-05-01 | 武汉上水微电子科技有限公司 | Method for realizing data and clock by using single pin |
| CN111901938A (en) * | 2020-08-31 | 2020-11-06 | 深圳市明微电子股份有限公司 | LED driving signal processing method and circuit, LED driving device and lamp |
| CN111954341A (en) * | 2020-09-03 | 2020-11-17 | 广州彩熠灯光股份有限公司 | Double-frequency control device and method and LED stage lamp |
| CN114630469A (en) * | 2020-12-11 | 2022-06-14 | 美芯晟科技(北京)股份有限公司 | Digital filter, LED dimming driving system and method |
| CN114630469B (en) * | 2020-12-11 | 2024-06-07 | 美芯晟科技(北京)股份有限公司 | Digital filter, LED dimming driving system and method |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1201969A (en) * | 1997-06-02 | 1998-12-16 | 精工爱普生株式会社 | Digital-analog converter, circuit board, electronic device, and liquid crystal display unit |
| WO2006039789A1 (en) * | 2004-10-12 | 2006-04-20 | Tir Systems Ltd. | Method and system for feedback and control of a luminaire |
| CN101175353A (en) * | 2007-10-23 | 2008-05-07 | 无锡市爱芯科微电子有限公司 | Integrated circuit for controlling and driving LED |
| CN101605417A (en) * | 2009-07-15 | 2009-12-16 | 西安英洛华微电子有限公司 | The LED constant-current drive circuit of band light modulation |
| CN101873109A (en) * | 2009-04-27 | 2010-10-27 | 武汉市创佳源电子有限公司 | Electronic potentiometer module having complete operating characteristic and function |
| CN102215616A (en) * | 2010-04-08 | 2011-10-12 | 无锡博赛半导体技术有限公司 | PWM (pulse width modulation)-based LED (light emitting diode) linear dimming circuit |
| CN103037573A (en) * | 2012-11-20 | 2013-04-10 | 无锡中星微电子有限公司 | Dimming circuit |
| CN103731151A (en) * | 2014-01-15 | 2014-04-16 | 南京矽力杰半导体技术有限公司 | Method and circuit for converting duty ratio into analog signal |
-
2015
- 2015-04-20 CN CN201510189332.3A patent/CN104822197B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1201969A (en) * | 1997-06-02 | 1998-12-16 | 精工爱普生株式会社 | Digital-analog converter, circuit board, electronic device, and liquid crystal display unit |
| WO2006039789A1 (en) * | 2004-10-12 | 2006-04-20 | Tir Systems Ltd. | Method and system for feedback and control of a luminaire |
| CN101175353A (en) * | 2007-10-23 | 2008-05-07 | 无锡市爱芯科微电子有限公司 | Integrated circuit for controlling and driving LED |
| CN101873109A (en) * | 2009-04-27 | 2010-10-27 | 武汉市创佳源电子有限公司 | Electronic potentiometer module having complete operating characteristic and function |
| CN101605417A (en) * | 2009-07-15 | 2009-12-16 | 西安英洛华微电子有限公司 | The LED constant-current drive circuit of band light modulation |
| CN102215616A (en) * | 2010-04-08 | 2011-10-12 | 无锡博赛半导体技术有限公司 | PWM (pulse width modulation)-based LED (light emitting diode) linear dimming circuit |
| CN103037573A (en) * | 2012-11-20 | 2013-04-10 | 无锡中星微电子有限公司 | Dimming circuit |
| CN103731151A (en) * | 2014-01-15 | 2014-04-16 | 南京矽力杰半导体技术有限公司 | Method and circuit for converting duty ratio into analog signal |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108207054A (en) * | 2016-12-19 | 2018-06-26 | 上海莱狮半导体科技有限公司 | The power expansion circuit and power expansion method of load |
| CN107027222A (en) * | 2017-05-11 | 2017-08-08 | 南京矽力杰半导体技术有限公司 | Load current adjusting circuit and adjusting method |
| CN107027222B (en) * | 2017-05-11 | 2019-06-11 | 南京矽力杰半导体技术有限公司 | Load current adjusting circuit and adjusting method |
| CN111090965A (en) * | 2018-10-23 | 2020-05-01 | 武汉上水微电子科技有限公司 | Method for realizing data and clock by using single pin |
| CN109450421A (en) * | 2018-12-17 | 2019-03-08 | 上海艾为电子技术股份有限公司 | A kind of analog switch opens circuit and method |
| CN109450421B (en) * | 2018-12-17 | 2023-09-01 | 上海艾为电子技术股份有限公司 | Analog switch starting circuit and method |
| CN111901938A (en) * | 2020-08-31 | 2020-11-06 | 深圳市明微电子股份有限公司 | LED driving signal processing method and circuit, LED driving device and lamp |
| CN111901938B (en) * | 2020-08-31 | 2022-12-02 | 深圳市明微电子股份有限公司 | LED driving signal processing method and circuit, LED driving device and lamp |
| CN111954341A (en) * | 2020-09-03 | 2020-11-17 | 广州彩熠灯光股份有限公司 | Double-frequency control device and method and LED stage lamp |
| CN114630469A (en) * | 2020-12-11 | 2022-06-14 | 美芯晟科技(北京)股份有限公司 | Digital filter, LED dimming driving system and method |
| CN114630469B (en) * | 2020-12-11 | 2024-06-07 | 美芯晟科技(北京)股份有限公司 | Digital filter, LED dimming driving system and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104822197B (en) | 2018-07-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104822197A (en) | Analog dimming control method, control circuit and LED drive circuit using the analog dimming control method and control circuit | |
| CN107027222B (en) | Load current adjusting circuit and adjusting method | |
| US7565559B2 (en) | Method and system for communicating filter compensation coefficients for a digital power control system | |
| US8067967B2 (en) | Phase delay line | |
| KR20210131471A (en) | Charge balanced charge pump control | |
| CN100555872C (en) | Spread spectrum clock generation circuit and control method thereof | |
| US8884676B2 (en) | Clock generator with duty cycle control and method | |
| CN106059290B (en) | Multi-channel DC-DC converter and control circuit and method | |
| WO2020241048A1 (en) | Circuit system | |
| CN207802451U (en) | Equipment for powering for electric loading | |
| CN104362854A (en) | Switching power supply, control circuit and method | |
| CN108471303B (en) | Programmable nanosecond timing precision pulse generator based on FPGA | |
| US8525609B1 (en) | Pulse width modulation circuits, systems and methods | |
| CN107797442B (en) | Time-to-digital conversion device and digital phase-locked loop | |
| CN102386893B (en) | Adjustable square signal generation circuit and switch-type regulator utilizing same | |
| CN105188201B (en) | A kind of high speed light adjusting circuit applied to LED illumination | |
| CN101707040A (en) | PWM driving method for displaying and driving LED | |
| US20120105135A1 (en) | Integrated circuit capacitor | |
| US10833665B2 (en) | Phase error correction for clock signals | |
| CN102933003B (en) | Dimming circuit | |
| EP3512096B1 (en) | Clock delay circuit | |
| CN104981075A (en) | Multifunctional LED light modulation interface circuit | |
| CN110784104A (en) | PID control circuit of DC-DC switching power supply | |
| CN103378726A (en) | Switching power supply and control circuit and control method thereof | |
| CN102427350B (en) | PWM (Pulse-Width Modulation) signal phase-shift circuit and control method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| EXSB | Decision made by sipo to initiate substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 210023 Nanjing, Jiangsu Xuanwu Avenue, building 699-27, room 7, No. 302 Patentee after: Nanjing Sili Microelectronics Technology Co., Ltd Address before: 210023 Nanjing, Jiangsu Xuanwu Avenue, building 699-27, room 7, No. 302 Patentee before: Silergy Semiconductor Technology (Hangzhou) Ltd. |
|
| CP01 | Change in the name or title of a patent holder |