CN114630469A - Digital filter, LED dimming driving system and method - Google Patents
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Abstract
The utility model provides a digital filter, LED drive system and method of adjusting luminance, directly carry out digital filtering to the PWM signal and produce duty cycle code and export a corresponding analog signal through digital-to-analog conversion, go to control the corresponding drive unit of LED through this analog signal, thereby realize LED adjusts luminance, realize not having stroboscopic dimming control when avoiding the circuit to produce the noise, and need not resistance and electric capacity filtering, thereby reduce LED drive system volume of adjusting luminance, reduce its cost of manufacture, be convenient for the user to install and use, provide good use experience for the user.
Description
Technical Field
The present disclosure relates to the field of linear LED (Light Emitting Diode) driving, and in particular, to a digital filter, an LED dimming driving system and a method thereof.
Background
Along with the requirement of people on intelligent illumination, the technology that intelligent illumination is realized through LED dimming is applied more and more extensively, can realize adjusting the effect of LED load current through the dimming control ware, and then realize that LED adjusts luminance. Some current dimming controllers directly utilize Pulse Width Modulation (PWM) signals to chop LED load current to control output current, and because the frequency of the PWM signals is usually in the range of 500Hz to 5KHz and is in an audio frequency range, the dimming mode may generate noise in a switching power supply system, which affects user experience.
Fig. 1 is a schematic diagram of an LED dimming driving device in the prior art, a PWM signal realizes conversion of an analog quantity through RC filtering, and then drives an LED through an analog signal to realize dimming, a large resistor and a large capacitor need to be integrated on the LED dimming driving device, and due to limitation of the volume and size of the resistor and the capacitor, the LED dimming driving device cannot be integrated on a control chip (a part framed by a dotted line in fig. 1), which is difficult to integrate, if the LED dimming driving device is used as an external device, the volume of the dimming driving device is seriously affected, the manufacturing cost is increased, and the LED dimming driving device is not beneficial to installation and use by a user, and the user experience is poor.
Disclosure of Invention
The disclosed embodiment aims to provide a digital filter, an LED dimming driving system and an LED dimming driving method, so as to solve the problems of noise, high integration difficulty and high manufacturing cost in a dimming mode in the prior art.
In order to solve the technical problem, the embodiment of the present disclosure adopts the following technical solutions: a digital filter comprising at least: the device comprises a sampling counting unit, a division unit, an error comparison unit, an output control unit and a digital-to-analog conversion unit; wherein the sampling counting unit is configured to output the collected data of the pulse width modulation signal based on the input pulse width modulation signal and the sampling clock signal; the dividing unit is connected with the output end of the sampling counting unit and is configured to determine and output the duty ratio code of the current period of the pulse width modulation signal based on the sampling data; the error comparison unit is connected with the output end of the division unit and the output end of the output control unit and is configured to compare the duty cycle code of the current period of the pulse width modulation signal with the duty cycle code of the previous period of the current period; when the absolute value of the difference value between the duty ratio code of the current period and the duty ratio code of the previous period is greater than a preset threshold value, the error comparison unit outputs a refresh signal; the output control unit is connected with the output end of the division unit and the output end of the error comparison unit and is configured to output the duty ratio code of the current period output by the division unit as an output code under the condition of receiving the refresh signal; the digital-to-analog conversion unit is connected with the output end of the output control unit and is configured to convert the output codes into analog signals to be output.
Further, the output control unit is further configured to output the output code output in the previous cycle as the output code of the current cycle in a case where the refresh signal is not received.
Further, still include: a synchronization unit configured to amplify a high level of an input pulse width modulation signal proportionally, synchronize the amplified pulse width modulation signal with a sampling clock signal, and output the amplified pulse width modulation signal and the sampling clock signal; the sampling counting unit is connected with the output end of the synchronization unit and is specifically configured to sample and count the amplified pulse width modulation signal based on the synchronized sampling clock signal.
Further, the sampling data includes at least two of: the number of high level clocks of the pulse width modulation signal, the number of low level clocks of the pulse width modulation signal, and the number of period clocks of the pulse width modulation signal.
Further, the error comparing unit includes at least: the error adder, the error subtracter and the progressive comparator are arranged; wherein the error adder is configured to add the duty cycle encoding of the current period and a first error to obtain a positive offset signal; the error subtractor is configured to subtract the duty cycle encoding of the current period from a second error to obtain a negative bias signal; the progressive comparator is connected with the error adder, the error subtractor and the output end of the output control unit respectively, and is configured to maintain the duty cycle encoding of the previous period when the duty cycle encoding of the previous period is between the positive bias signal and the negative bias signal; outputting the refresh signal if the duty cycle encoding of the previous cycle is not between the positive bias signal and the negative bias signal.
Further, the output control unit at least includes a register.
Further, the output control unit further includes: a subtractor and an addition-subtraction counter; the register is connected with the output ends of the error comparison unit and the division unit and is configured to output the duty ratio code of the current period output by the division unit as an output code under the condition of receiving the refresh signal; the subtractor is connected with the register and the output end of the addition and subtraction counter, and is configured to compare the input value and the output value of the addition and subtraction counter and output a counting control signal according to the comparison result; the addition and subtraction counter is connected with the output ends of the register and the subtracter and is configured to add, subtract or maintain the output codes output by the register based on a counter clock.
Further, the subtractor is configured to output an addition control signal when the output value of the addition-subtraction counter is smaller than the input value thereof; when the output value of the addition and subtraction counter is greater than the input value of the addition and subtraction counter, outputting a subtraction control signal; outputting a maintaining control signal when the output value of the addition and subtraction counter is equal to the input value; the up-down counter is configured to add 1 to the output value of the up-down counter based on the counter clock to form a new output value when the adding control signal is received; under the condition that the subtraction control signal is received, subtracting 1 from the output value of the addition and subtraction counter based on the counter clock to form a new output value; and when the maintaining control signal is received, keeping the output value of the addition and subtraction counter unchanged and stopping counting.
Further, the counter clock is a sampling clock signal or a frequency division signal of the sampling clock signal; or, the counter clock is an operating frequency of the dimming driving system or a frequency division signal of the operating frequency.
The embodiment of the present disclosure further provides an LED dimming driving system, which at least includes: the above-mentioned digital filter; a drive unit; the load unit at least comprises an LED load and a power control unit; the input end of the digital filter inputs a pulse width modulation signal, the output end of the digital filter is connected with the input end of the driving unit, the driving unit generates a driving signal based on an analog signal output by the digital filter, and the power control unit controls the on-off of the LED load or adjusts the brightness of the LED load based on the driving signal output by the driving unit.
The embodiment of the present disclosure further provides an LED dimming driving method, which is applied to the dimming driving system, and includes: acquiring sampling data of a pulse width modulation signal; determining a duty cycle encoding of a current period of the pulse width modulated signal based on the sampled data; outputting a first duty ratio code according to a comparison result of the duty ratio code of the previous period and the duty ratio code of the current period; and converting the output first duty cycle code into an analog quantity for controlling LED dimming.
Further, the acquiring of the sampling data of the pwm signal includes: after the pulse width modulation signal is synchronized with the sampling clock signal, at least two of the number of high level clocks, the number of low level clocks, and the number of period clocks of the pulse width modulation signal are obtained.
Further, the outputting the first duty cycle code according to the comparison result of the duty cycle code of the previous period and the duty cycle code of the current period includes: when the absolute value of the difference between the duty cycle code of the previous period and the duty cycle code of the current period is greater than a preset threshold value, outputting the duty cycle code of the current period as the first duty cycle code; and when the absolute value of the difference between the duty cycle code of the last period and the duty cycle code of the current period is less than or equal to a preset threshold value, outputting the duty cycle code of the last period as the first duty cycle code.
Further, the outputting the first duty cycle code according to the comparison result of the duty cycle code of the previous period and the duty cycle code of the current period includes: adding the duty ratio code of the current period and the first error to obtain a forward bias signal; subtracting the current period duty ratio code from the second error to obtain a negative bias signal; when the last cycle duty cycle code is between the positive bias signal and the negative bias signal, outputting the last cycle duty cycle code as the first duty cycle code; when the last period duty cycle code is not between the positive bias signal and the negative bias signal, outputting the current period duty cycle code as the first duty cycle code.
Further, still include: if the first duty cycle code is larger than the last cycle duty cycle code, the last cycle duty cycle code is increased progressively until the first duty cycle code is equal to the first duty cycle code; if the first duty cycle code is smaller than the last cycle duty cycle code, the last cycle duty cycle code is decreased until the first duty cycle code is equal to the first duty cycle code; if the first duty cycle code is equal to the last period duty cycle code, then the first duty cycle code remains unchanged.
The beneficial effects of this disclosed embodiment lie in: through comparing the duty cycle code of PWM signal in the adjacent cycle, when the relatively big jump appears in the duty cycle of PWM signal, can be based on the duty cycle code of the current cycle of PWM signal, through a corresponding analog signal of digital-to-analog conversion output, go to control the corresponding drive unit of LED through this analog signal, thereby realize LED and adjust luminance, realize not stroboscopic dimming control when avoiding the circuit to produce the noise, and need not resistance and capacitive filtering, thereby reduce LED and adjust luminance actuating system volume, reduce its cost of manufacture, be convenient for the user to install and use, provide good use experience for the user.
Drawings
Fig. 1 is a schematic diagram of a prior art LED dimming driving apparatus;
fig. 2 is a schematic structural diagram of a digital filter according to a first embodiment of the disclosure;
fig. 3 is another schematic structural diagram of the digital filter according to the first embodiment of the disclosure;
fig. 4 is a schematic structural diagram of a first preferred implementation of the digital filter in the first embodiment of the present disclosure;
FIG. 5 is a schematic diagram of the input and output of the digital filter shown in FIG. 4 according to the first embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a second preferred implementation of the digital filter in the first embodiment of the present disclosure;
FIG. 7 is a schematic diagram of the input and output of the digital filter shown in FIG. 6 according to the first embodiment of the present disclosure;
fig. 8 is a system diagram of an LED dimming driving system according to a second embodiment of the present disclosure;
fig. 9 is a flowchart of a LED dimming driving method according to a third embodiment of the present disclosure.
Reference numerals
10-sample counting unit 20-division unit 30-error comparison unit
40-output control unit 50-digital-to-analog conversion unit 60-synchronization unit
11-sample counter 12-first sample register 13-second sample register
21-N bit divider 31-error adder 32-error subtractor
33-bit-by-bit comparator 41-N bit register 42-N bit subtracter
43-N bit addition and subtraction counter 51-digital-to-analog converter 61-synchronizer
62-reference clock signal 100-digital filter 200-drive unit
300-load unit 301-load circuit 302-power control device 303-load detection unit
Detailed Description
Various aspects and features of the present application are described herein with reference to the drawings.
It will be understood that various modifications may be made to the embodiments of the present application. Accordingly, the foregoing description should not be construed as limiting, but merely as exemplifications of embodiments. Those skilled in the art will envision other modifications within the scope and spirit of the application.
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the application and, together with a general description of the application given above and the detailed description of the embodiments given below, serve to explain the principles of the application.
These and other characteristics of the present application will become apparent from the following description of preferred forms of embodiment, given as non-limiting examples, with reference to the attached drawings.
It should also be understood that, although the present application has been described with reference to some specific examples, a person of skill in the art shall certainly be able to achieve many other equivalent forms of application, having the characteristics as set forth in the claims and hence all coming within the field of protection defined thereby.
The above and other aspects, features and advantages of the present application will become more apparent in view of the following detailed description when taken in conjunction with the accompanying drawings.
Specific embodiments of the present application are described hereinafter with reference to the accompanying drawings; however, it is to be understood that the disclosed embodiments are merely exemplary of the application, which can be embodied in various forms. Well-known and/or repeated functions and constructions are not described in detail to avoid obscuring the application of unnecessary or unnecessary detail. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present application in virtually any appropriately detailed structure.
The specification may use the phrases "in one embodiment," "in another embodiment," "in yet another embodiment," or "in other embodiments," which may each refer to one or more of the same or different embodiments in accordance with the application.
Along with the requirement of people on intelligent illumination, the technology that intelligent illumination is realized through LED dimming is applied more and more extensively, can realize adjusting the effect of LED load current through the dimming control ware, and then realize that LED adjusts luminance. Some current dimming controllers directly utilize PWM signals to chop LED load current to control output current, because the frequency of the PWM signals is usually 500 Hz-5 KHz and is in an audio frequency range, the dimming mode can generate noise in a switching power supply system, and because the PWM chopping dimming can enable the LED current to be zero, obvious high-frequency flicker is caused, and discomfort of human eyes is caused; in addition, the PWM dimmer can cause the LED brightness to generate obvious step feeling during the continuous dimming process, which affects the dimming experience.
In order to solve the noise problem in the dimming process, analog dimming is often used in the prior art to avoid noise generation. Fig. 1 is a schematic diagram of an LED dimming driving apparatus in the prior art, which mainly includes a resistor R, a capacitor C, a control chip and a load unit, where the control chip has a driving unit therein, the load unit mainly includes a load circuit (i.e., an LED circuit), a power control device and a load detection unit, which are sequentially connected in series, a PWM signal is filtered by an RC to realize analog conversion, so as to form a first analog signal, the driving unit drives the power control device based on the first analog signal, so as to realize on-off and dimming of the load circuit, when a load is too large, the load detection unit outputs a load detection signal to the driving unit, and the driving unit correspondingly generates a control signal to turn off the load circuit. For the LED dimming driving device shown in fig. 1, a large resistor and a large capacitor need to be integrated on the LED dimming driving device, and the resistor and the capacitor cannot be integrated on the control chip due to the limitations of the volume and the size of the resistor and the capacitor, and if the resistor and the capacitor are used as an external device, the volume of the dimming driving device is seriously affected, the manufacturing cost is increased, and the LED dimming driving device is not favorable for the installation and the use of a user, and the user experience is poor.
In order to solve the above problem, a first embodiment of the present disclosure provides a digital filter, which is mainly installed in an LED dimming driving system and is configured to perform filtering processing, convert a PWM signal into an analog signal and output the analog signal, and implement mute driving of LED brightness. The schematic structural diagram of the digital filter is shown in fig. 2, and mainly includes: the digital-to-analog converter comprises a sampling counting unit 10, a dividing unit 20, an error comparing unit 30, an output control unit 40 and a digital-to-analog conversion unit 50, wherein an input end of the sampling counting unit 10 inputs a PWM signal and a high-frequency sampling clock signal, an output end of the sampling counting unit is connected with an input end of the dividing unit 20, an output end of the dividing unit 20 is respectively connected with input ends of the error comparing unit 30 and the output control unit 40, an input end of the output control unit 40 is simultaneously connected with an output end of the error comparing unit 30, an output end of the output control unit 40 is connected with an input end of the error comparing unit 30 and an input end of the digital-to-analog conversion unit 50, and an output end of the digital-to-analog conversion unit 50 serves as an output end of the digital filter to output an analog signal.
Specifically, the sampling counting unit 10 performs sampling statistics on the input PWM signal based on the high-frequency sampling clock signal to obtain relevant sampling data of the PWM signal, for example, at least two of the high-level clock number, the low-level clock number, and the periodic clock number of the PWM signal. It should be noted that, the higher the frequency of the sampling clock signal CLK, the denser the sampling times of the sampling counting unit 10 are, and the more accurate the obtained PWM signal is in one period and in one period, the higher the time of the PWM signal at the high level or the low level, therefore, in this embodiment, the sampling clock signal CLK with a higher frequency is preferably used, and the specific frequency thereof may be determined according to the frequency of the PWM signal, the calculation accuracy of the sampling counting unit 10, and the actual sampling accuracy requirement.
Specifically, the sampling counting unit 10 sends out a wave sample every time a sampling clock signal CLK arrives, and collects the waveform of the PWM signal at this time, because the sampling clock signal CLK has a high frequency, continuous high-frequency sampling forms a plurality of collection points, and a square wave is formed after the collection points are connected together, so that the time of one period of the PWM signal, the time of the PWM signal at a high level in one period, the time of the PWM signal at a low level in one period, and the like can be determined according to the waveform diagram of the square wave, and the number of high-level clocks, the number of low-level clocks, and the number of periodic clocks of the PWM signal can be correspondingly obtained.
After the sampling counting unit 10 determines sampling data of a PWM signal period, the sampling data is output to the dividing unit 20, and after the dividing unit 20 receives the sampling data, the duty ratio of the current period of the PWM signal can be calculated and determined. Because the high level represents the on signal and the low level represents the off signal, when the high level signal time in one period is longer, namely the on time is longer along with the longer, the corresponding LED load power-on time is longer, and further the brightness of the LED is improved, when the LED dimming is needed, the adjustment of the LED brightness can be realized by changing the duty ratio of the PWM signal. It should be appreciated that the division unit 20 is primarily a divider whose calculated duty cycle is primarily output in the form of an N-bit binary code.
The error comparing unit 30 is mainly used for comparing the duty cycle code of the current period of the PWM signal with the duty cycle code of the previous period of the current period. Specifically, the duty cycle code of the current period of the PWM signal is output by the division unit 20, the duty cycle code of the previous period is input to the error comparison unit 30 while the output control unit 40 sends the output code to the digital-to-analog conversion unit 50 in the previous period, since the duty cycle codes are all represented in the form of N-bit binary codes, the error comparing unit 30 can determine whether the duty cycle of the PWM signal in the adjacent period has a large-amplitude jump or not based on the absolute value of the difference between the duty cycle code of the current period and the duty cycle code of the previous period, when the absolute value is larger than a preset threshold value, the PWM signal is proved to have larger amplitude jump in the duty ratio of the adjacent period, and further indicates that the brightness of the LED needs to be adjusted at this time, the error comparing unit 30 outputs a refresh signal, for instructing the output control unit 40 to perform output control according to the adjusted duty ratio code. Specifically, the refresh signal may be a digital signal with a predetermined value or a digital signal with a predetermined number of bits, so that the output control unit 40 can know that the signal is the refresh signal when receiving the digital signal.
In practical use, if the absolute value of the difference between the duty cycle code of the current period and the duty cycle code of the previous period is less than or equal to the preset threshold, the duty cycle of the PWM signal may change due to the transmission environment, and at this time, even if the LED brightness adjustment is performed, the brightness change before and after the adjustment may not be obvious, so that, under the condition that the absolute value is less than or equal to the preset threshold, the error comparing unit 30 does not output the refresh signal or output a maintenance signal different from the refresh signal, and the output control unit 40 does not refresh or adjust the duty cycle code when receiving no refresh signal or receiving the maintenance signal.
Under the condition that the output control unit 40 receives the refresh signal, it proves that the LED brightness adjustment is required currently, at this time, the output control unit 40 updates the output content output by itself, and outputs the duty ratio code of the current period output by the division unit 20 as the output code, and the output code is converted into an analog signal after passing through the digital-to-analog conversion unit 50, and correspondingly drives the LED to change the brightness. When the output control unit 40 does not receive the refresh signal or the sustain signal, the output control unit 40 does not update the duty cycle code, and still uses the output code output from the previous period as the output code of the current period for outputting, and the brightness of the corresponding LED remains unchanged.
This embodiment is through comparing the duty cycle code to PWM signal in the adjacent cycle, when the relatively big jump appears in the duty cycle of PWM signal, can be based on the duty cycle code of the current cycle of PWM signal, through a corresponding analog signal of digital-to-analog conversion output, go to control the corresponding drive unit of LED through this analog signal, thereby realize LED and adjust luminance, realize not stroboscopic dimming control when avoiding the circuit to produce the noise, and need not resistance and capacitive filtering, thereby reduce LED and adjust luminance actuating system volume, reduce its cost of manufacture, be convenient for the user to install and use, experience for the user provides good use.
In some embodiments, the digital filter may further include a synchronizing unit 60, as shown in fig. 3, configured to proportionally amplify a high level of the input PWM signal to meet an internal voltage processing requirement of the LED dimming driving system, and at the same time, the synchronizing unit 60 is further configured to synchronize the amplified PWM signal with the sampling clock signal CLK, so that the sampling counting unit 10 performs sampling counting on the amplified PWM signal based on the synchronized sampling clock signal CLK, thereby avoiding that, under the condition that the PWM duty ratio is not changed due to the CLK being asynchronous with the PWM, the sampling counting unit 10 may affect a deviation between duty ratios obtained by the dividing unit 20 due to a statistical deviation between a first clock number and a second clock number of the PWM signal of adjacent periods.
Fig. 4 shows a schematic structural diagram of a first preferred embodiment of the digital filter. As shown in fig. 4, the synchronizing unit 60 at least includes a synchronizer 61 and a reference clock signal 62, the synchronizer 61 performs proportional amplification on the input PWM signal based on the input reference voltage VREF1, and realizes synchronization between the reference clock signal 62 and the amplified PWM signal, and the output clock signal is used as the sampling clock signal CLK of the sampling counting unit 10; the sampling counting unit 10 at least includes a sampling counter 11, a first sampling register 12, and a second sampling register 13 in this embodiment, the sampling counter 11 collects the number of high-level clocks and the number of periodic clocks of the PWM signal based on CLK, the number of the periodic clocks collected and counted is registered in the second sampling register 13, the number of the high-level clocks collected and counted is registered in the first sampling register 12, and the sampling counting unit 10 outputs the number of the high-level clocks and the number of the periodic clocks as sampling data to the division unit 20 every PWM period. It should be noted that when other clock numbers are sampled as the sampling data, the first sampling register 12 and the second sampling register 13 may register the other clock numbers correspondingly.
The dividing unit 20 may be an N-bit divider 21, which determines the duty ratio of the PWM current period based on the sampling data, and outputs the duty ratio to the error comparing unit 30 as an N-bit binary code. The error comparing unit 30 mainly includes an error adder 31, an error subtractor 32, and a progressive comparator 33, each time the dividing unit 20 outputs a new duty ratio code, the error adder 31 adds the duty ratio code and the first error E1 to obtain a positive bias signal, and outputs the positive bias signal to the progressive comparator 33, the error subtractor 32 subtracts the duty ratio code and the second error E2 to obtain a negative bias signal, and outputs the negative bias signal to the progressive comparator 33, at this time, the positive bias signal and the negative bias signal form a preset range, the progressive comparator 33 compares the output code output by the output control unit 40 in the previous period (i.e. the duty ratio code output in the previous period) with the preset range formed by the positive bias signal and the negative bias signal, if the output code output in the previous period is in the preset range, it indicates that the duty ratio of the current period does not change greatly with the duty ratio of the previous period, if the output code output from the previous period is not within the preset range, it indicates that the change between the duty cycle of the current period and the duty cycle of the previous period is large, and at this time, the bit-by-bit comparator 33 outputs a refresh signal to the output control unit 40 to control the output control unit to output the refresh signal with the duty cycle code of the current period.
The output control unit 40 may select the N-bit register 41, which stores the duty ratio code output from the previous period, and when receiving the refresh signal, the output control unit covers the currently stored duty ratio code from the previous period with the N-bit binary code output from the N-bit divider 21, and outputs the covered code as a new output code; the digital-to-analog conversion unit 50 is preferably an N-bit digital-to-analog converter (DAC)51, which may perform the conversion of an N-bit binary code into an analog signal.
Fig. 5 shows an input-output schematic diagram of the digital filter shown in fig. 4. As shown in fig. 5, when Ton2 in the second period T is greater than Ton1 in the first period T in fig. 5, the corresponding output analog signal will become larger at the beginning of the third period T, when Ton3 in the fifth period T is smaller than Ton2 in the fourth period T, the corresponding output analog signal will become smaller at the beginning of the sixth period T, and the high-level durations of the second, third and fourth periods are the same, and the waveforms of the analog signals will remain unchanged in the waveform diagram of the analog signals (i.e., from the beginning of the third period T to the end of the fifth period T). Therefore, in this embodiment, when the duty ratio of the PWM signal has a relatively large jump, the analog signal output by the DAC and reflecting the duty ratio information also has a fast jump, so as to achieve the effect of responding in time.
Fig. 6 shows a schematic diagram of a second preferred embodiment of the digital filter, in which, based on the structure shown in fig. 4, the output control unit 40 further includes an N-bit subtractor 42 and an N-bit up-down counter 43, in this case, the N-bit subtractor 42 is connected to the N-bit register 41 and the output end of the N-bit up-down counter 43, and is configured to compare the magnitude between the input value and the output value of the N-bit up-down counter 43 and output a count control signal according to the comparison result, where the count control signal mainly includes an up-count signal, a down-count signal and a sustain control signal; the N-bit up-down counter 43 is connected to the output terminals of the N-bit register 41 and the N-bit subtractor 42, and the N-bit up-down counter 43 further includes a counter clock for performing up-counting, down-counting or maintaining on the output code outputted from the N-bit register 41 by the counter clock. It should be noted that the counter clock of the N-bit up-down counter 43 may directly use the CLK clock signal output by the synchronization unit 60, or may use a frequency-divided signal of the CLK clock signal, and in some embodiments, the counter clock may also directly use the operating frequency of the dimming driving system or a frequency-divided signal thereof.
Specifically, if the output of the N-bit up-down counter 43 is smaller than the input thereof, the N-bit subtractor 42 outputs an up-count signal; if the output of the N-bit up-down counter 43 is larger than its input, the N-bit subtractor 42 outputs a down-count signal; if the output of the N-bit up-down counter 43 is equal to the input, the N-bit subtractor 42 outputs the hold control signal, and the N-bit up-down counter 43 stops counting. Under the control of the counting control signal output by the N-bit subtractor 42, the N-bit addition/subtraction counter 43 performs +1 operation, -1 operation and stop counting operation on the current output according to the CLK clock signal, so that the output code output by the N-bit addition/subtraction counter can be gradually increased or decreased according to the frequency of the CLK clock signal, the corresponding input/output schematic diagram is shown in fig. 7, when the duty ratio of the PWM changes suddenly, due to the presence of the N-bit addition/subtraction counter 43, the output code output by the N-bit addition/subtraction counter gradually changes from the duty ratio code of the previous period to the duty ratio code of the current period, and the corresponding output analog signal forms a gradual change process as shown in fig. 7, so that the LED dimming process is smoother and the dimming effect is better.
A system schematic diagram of the LED dimming driving system is shown in fig. 8, and mainly includes the digital filter 100, the driving unit 200, and the load unit 300 provided in the first embodiment of the present disclosure, wherein a specific structure and a filtering principle of the digital filter 100 have been described in detail in the first embodiment, and are not repeated herein; the input end of the driving unit 200 is connected to the output end of the digital filter 100, which can realize the control of the load unit 300 based on the analog signal output by the digital filter 100; the load unit 300 mainly includes a load circuit 301 (mainly an LED lamp or an LED lamp group), a power control device 302, and a load detection unit 303, which are sequentially connected in series, wherein the power control device 302 receives a driving signal output by the driving unit 200 to implement on/off and dimming of the load circuit, when the load is too large, the load detection unit 303 outputs a load detection signal to the driving unit 200, and the driving unit 200 correspondingly generates a control signal to turn off the load circuit or adjust the intensity of the LED load.
In this embodiment, the digital filter 100 and the driving unit 200 may be directly integrated on the same control chip (the portion enclosed by the dotted line in fig. 8), for example, an RC filter circuit used in the prior art is replaced by the digital filter, and under the condition of preventing noise generation through analog signal control, it is not necessary to integrate a resistor and a capacitor in the LED dimming driving system, so as to reduce the volume of the LED dimming driving system, reduce the manufacturing cost thereof, facilitate the installation and use by a user, and provide a good use experience for the user.
A third embodiment of the present disclosure provides an LED dimming driving method, which is mainly applied to the LED dimming driving system provided in the second embodiment of the present disclosure, and a flowchart of the method is shown in fig. 9, and mainly includes steps S1 to S4:
s1, acquiring sampling data of the pulse width modulation signal;
s2, determining the duty ratio code of the current period of the pulse width modulation signal based on the sampling data;
s3, outputting a first duty ratio code according to the comparison result of the duty ratio code of the previous period and the duty ratio code of the current period;
and S4, converting the output first duty cycle code into an analog quantity for controlling LED dimming.
Compared with the prior art in which the LED is directly controlled to be dimmed through the pulse width modulation signal, the method provided by the embodiment reduces the noise of frequent on-off of the LED, is more stable, and simultaneously saves filtering elements such as a capacitance resistor and the like, thereby reducing the volume of the LED dimming driving system, reducing the manufacturing cost of the LED dimming driving system, facilitating the installation and use of a user, and providing good use experience for the user.
Further, acquiring the sampling data of the pulse width modulation signal includes: after the pulse width modulation signal is synchronized with the sampling clock signal, at least two of the number of high level clocks, the number of low level clocks, and the number of period clocks of the pulse width modulation signal are obtained. The synchronous PWM signals can avoid errors when the pulse width modulation signals and the sampling clock signals are asynchronous, the precision is improved, and at least two of the number of high-level clocks, the number of low-level clocks and the number of periodic clocks of the PWM signals can be collected as sampling data to serve as the basis for calculating the duty ratio during sampling.
In order to avoid that the dimming signal is influenced by tiny fluctuation and unstable light emission of the LED is avoided, the embodiment sets an error comparison link, wherein when a difference between a duty cycle code of a previous period and a duty cycle code of a current period is greater than a preset threshold, the duty cycle code of the current period is output; and outputting the duty ratio code of the previous period when the difference between the duty ratio code of the previous period and the duty ratio code of the current period is smaller than a preset threshold value.
In practical use, the duty ratio code of the current period can be added with the first error to obtain a positive bias signal; subtracting the current period duty ratio code from the second error to obtain a negative bias signal; when the last period of duty cycle code is positioned between the positive bias signal and the negative bias signal, outputting the last period of duty cycle code as a first duty cycle code; and when the duty cycle code of the last period is not between the positive bias signal and the negative bias signal, outputting the duty cycle code of the current period as a first duty cycle code.
For a better dimming experience, the LED is set to dim slowly or dim slowly, and the duty cycle code of the output can be adjusted gradually to change slowly, in the following way:
if the first duty ratio code is larger than the last period duty ratio code, the last period duty ratio code is increased progressively until the first duty ratio code is equal to the first duty ratio code;
if the first duty ratio code is smaller than the previous period duty ratio code, the previous period duty ratio code is decreased until the first duty ratio code is equal to the first duty ratio code;
if the first duty cycle code is equal to the last cycle duty cycle code, then it remains unchanged.
In the adjusting mode, when the brightness of the LED needs to be adjusted, the LED light source can be slowly changed, and discomfort caused by human eyes is prevented.
On the basis of the technical scheme, the dimming speed can be changed according to the change condition of the duty ratio, when the change range of the duty ratio is the first range, the first stepping value can be selected to change the dimming speed, when the change range of the duty ratio is the second range, the second stepping value can be selected to change the dimming speed, different dimming speeds are changed according to different conditions, and better experience is brought to a user.
The above embodiments are merely exemplary embodiments of the present disclosure, which is not intended to limit the present disclosure, and the scope of the present disclosure is defined by the claims. Various modifications and equivalents of the disclosure may occur to those skilled in the art within the spirit and scope of the disclosure, and such modifications and equivalents are considered to be within the scope of the disclosure.
Claims (15)
1. A digital filter, comprising at least: the device comprises a sampling counting unit, a division unit, an error comparison unit, an output control unit and a digital-to-analog conversion unit; wherein the content of the first and second substances,
the sampling counting unit is configured to output the acquired data of the pulse width modulation signal based on the input pulse width modulation signal and the sampling clock signal;
the dividing unit is connected with the output end of the sampling counting unit and is configured to determine and output the duty ratio code of the current period of the pulse width modulation signal based on the sampling data;
the error comparison unit is connected with the output end of the division unit and the output end of the output control unit and is configured to compare the duty cycle code of the current period of the pulse width modulation signal with the duty cycle code of the previous period of the current period; when the absolute value of the difference value between the duty ratio code of the current period and the duty ratio code of the previous period is greater than a preset threshold value, the error comparison unit outputs a refresh signal;
the output control unit is connected with the output end of the division unit and the output end of the error comparison unit and is configured to output the duty ratio code of the current period output by the division unit as an output code under the condition of receiving the refresh signal;
the digital-to-analog conversion unit is connected with the output end of the output control unit and is configured to convert the output codes into analog signals to be output.
2. The digital filter according to claim 1, wherein the output control unit is further configured to output the output code output in the previous cycle as the output code of the current cycle in a case where the refresh signal is not received.
3. The digital filter of claim 1, further comprising:
a synchronization unit configured to perform proportional amplification on a high level of an input pulse width modulation signal, synchronize the amplified pulse width modulation signal with a sampling clock signal, and output the amplified pulse width modulation signal and the sampling clock signal;
the sampling counting unit is connected with the output end of the synchronization unit and is specifically configured to sample and count the amplified pulse width modulation signal based on the synchronized sampling clock signal.
4. The digital filter of claim 1, wherein the sampled data comprises at least two of: the number of high level clocks of the pulse width modulation signal, the number of low level clocks of the pulse width modulation signal, and the number of period clocks of the pulse width modulation signal.
5. The digital filter according to claim 1, wherein the error comparing unit comprises at least: the error adder, the error subtracter and the progressive comparator are arranged; wherein the content of the first and second substances,
the error adder is configured to add the duty cycle encoding of the current period and a first error to obtain a forward bias signal;
the error subtractor is configured to subtract the duty cycle encoding of the current period from a second error to obtain a negative bias signal;
the progressive comparator is connected with the error adder, the error subtractor and the output end of the output control unit respectively, and is configured to maintain the duty cycle encoding of the previous period when the duty cycle encoding of the previous period is between the positive bias signal and the negative bias signal; outputting the refresh signal if the duty cycle encoding of the previous cycle is not between the positive bias signal and the negative bias signal.
6. The digital filter according to claim 5, wherein the output control unit comprises at least a register.
7. The digital filter according to claim 6, wherein the output control unit further comprises: a subtractor and an addition-subtraction counter; wherein the content of the first and second substances,
the register is connected with the output ends of the error comparison unit and the division unit and is configured to output the duty ratio code of the current period output by the division unit as an output code under the condition of receiving the refresh signal;
the subtractor is connected with the register and the output end of the addition and subtraction counter, and is configured to compare the input value and the output value of the addition and subtraction counter and output a counting control signal according to the comparison result;
the addition and subtraction counter is connected with the output ends of the register and the subtracter and is configured to add, subtract or maintain the output codes output by the register based on a counter clock.
8. The digital filter according to claim 7, wherein the subtractor is configured to output an addition control signal when the output value of the up-down counter is smaller than the input value thereof; when the output value of the addition and subtraction counter is greater than the input value of the addition and subtraction counter, outputting a subtraction control signal; outputting a maintaining control signal when the output value of the addition and subtraction counter is equal to the input value;
the up-down counter is configured to add 1 to the output value of the up-down counter based on the counter clock to form a new output value when the adding control signal is received; under the condition that the subtraction control signal is received, subtracting 1 from the output value of the addition and subtraction counter based on the counter clock to form a new output value; and when the maintaining control signal is received, keeping the output value of the addition and subtraction counter unchanged and stopping counting.
9. The digital filter according to claim 7, wherein the counter clock is a sampling clock signal or a divided signal of the sampling clock signal;
alternatively, the first and second electrodes may be,
the counter clock is the working frequency of the dimming driving system or a frequency division signal of the working frequency.
10. An LED dimming driving system, comprising at least:
the digital filter of any one of claims 1 to 9;
a drive unit;
the load unit at least comprises an LED load and a power control unit;
the input end of the digital filter inputs a pulse width modulation signal, the output end of the digital filter is connected with the input end of the driving unit, the driving unit generates a driving signal based on an analog signal output by the digital filter, and the power control unit controls the on-off of the LED load or adjusts the brightness of the LED load based on the driving signal output by the driving unit.
11. An LED dimming driving method applied to the dimming driving system according to claim 10, comprising:
acquiring sampling data of a pulse width modulation signal;
determining a duty cycle encoding of a current period of the pulse width modulated signal based on the sampled data;
outputting a first duty ratio code according to a comparison result of the duty ratio code of the previous period and the duty ratio code of the current period;
and converting the output first duty cycle code into an analog quantity for controlling LED dimming.
12. The method of claim 11, wherein obtaining sample data of a pulse width modulated signal comprises:
after the pulse width modulation signal is synchronized with the sampling clock signal, at least two of the number of high-level clocks, the number of low-level clocks, and the number of periodic clocks of the pulse width modulation signal are obtained.
13. The method of claim 12, wherein outputting the first duty cycle code according to the comparison of the previous cycle duty cycle code and the current cycle duty cycle code comprises:
when the absolute value of the difference between the duty cycle code of the previous period and the duty cycle code of the current period is greater than a preset threshold value, outputting the duty cycle code of the current period as the first duty cycle code;
and when the absolute value of the difference between the duty cycle code of the last period and the duty cycle code of the current period is less than or equal to a preset threshold value, outputting the duty cycle code of the last period as the first duty cycle code.
14. The method of claim 12, wherein outputting the first duty cycle code according to the comparison of the previous cycle duty cycle code and the current cycle duty cycle code comprises:
adding the duty ratio code of the current period and the first error to obtain a forward bias signal;
subtracting the current period duty ratio code from the second error to obtain a negative bias signal;
when the last period duty cycle code is positioned between the positive bias signal and the negative bias signal, outputting the last period duty cycle code as the first duty cycle code; when the last period duty cycle code is not between the positive bias signal and the negative bias signal, outputting the current period duty cycle code as the first duty cycle code.
15. The method of claim 13 or 14, further comprising:
if the first duty cycle code is larger than the last cycle duty cycle code, the last cycle duty cycle code is increased progressively until the first duty cycle code is equal to the first duty cycle code;
if the first duty cycle code is smaller than the last cycle duty cycle code, the last cycle duty cycle code is decreased until the first duty cycle code is equal to the first duty cycle code;
if the first duty cycle code is equal to the last period duty cycle code, then the first duty cycle code remains unchanged.
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