CN104821335B - N型埋层覆盖型半超结横向双扩散金属氧化物半导体场效应管 - Google Patents

N型埋层覆盖型半超结横向双扩散金属氧化物半导体场效应管 Download PDF

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CN104821335B
CN104821335B CN201510112412.9A CN201510112412A CN104821335B CN 104821335 B CN104821335 B CN 104821335B CN 201510112412 A CN201510112412 A CN 201510112412A CN 104821335 B CN104821335 B CN 104821335B
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段宝兴
董超
范玮
杨银堂
朱樟明
马剑冲
李春来
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Huayi Microelectronics Co Ltd
Xidian University
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Xi'an Hua Yi Electronic Ltd By Share Ltd
Xidian University
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816Lateral DMOS transistors, i.e. LDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]

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Abstract

N型埋层覆盖型半超结横向双扩散金属氧化物半导体场效应管。本发明公开一种新的SJ‑LDMOS器件,在P型外延层上制作半超级结,并且在半超级结区和部分外延片上引入N型埋层。与传统的SJ‑LDMOS相比,本发明通过N型埋层的作用,补偿了超级结内N型柱区和P型柱区之间的电荷不平衡,克服了衬底辅助效应,提高了击穿电压;并且由于是半超级结,在表面引入一个电场峰,进一步提高击穿电压。同时,N型埋层额外增加一条新的导电路径,降低比导通电阻。可以看出该结构的特点是高击穿电压,低导通电阻和超级结层电荷的平衡。本发明提供的新的SJ‑LDMOS器件结构还具有制造工艺相对简单,工艺难度较低的特点。本发明更易满足功率电子系统的应用要求。

Description

N型埋层覆盖型半超结横向双扩散金属氧化物半导体场效 应管
技术领域
本发明涉及半导体功率器件技术领域,具体涉及是一种半超结横向双扩散金属氧化物半导体场效应管。
背景技术
横向功率半导体器件LDMOS(Lateral Double-diffused MOSFET)的特点在于具有横向沟道,同时栅极、源极和漏极都在芯片的同一侧表面,易于通过内部连接实现与低压信号的集成,另外在频率特性、增益、线性度、开关性能等方面的优点,成为实现引起第二次电子革命的核心技术:PIC(Power Integrated Circuit)和HVIC(High Voltage IntegratedCircuit)的关键。
超结(super junction)结构是交替排列的N型柱区和P型柱区,如果用超结结构来取代LDMOS的漂移区,就形成了超结LDMOS,简称SJ-LDMOS。理论上,超结结构通过N型柱区和P型柱区之间的电荷平衡能够得到高的击穿电压,而通过重掺杂的N型柱区和P型柱区可以获得很低的导通电阻,因此,超结器件可以在击穿电压和导通电阻两个关键参数之间取得一个很好的折衷。
但是对于SJ-LDMOS,由于衬底辅助耗尽N型柱区(或P型柱区),使得器件击穿时,P型柱区(或N型柱区)不能完全耗尽,打破了N型柱区和P型柱区之间的电荷平衡,降低了SJ-LDMOS器件的横向击穿电压。
半超级结,即超级结区占漂移区的一半或部分,相对于普通超级结而言,增加一个电场峰,从而提高击穿电压,但是同样存在着和普通超结一样的衬底辅助效应的缺陷。
发明内容
本发明提出一种N型埋层覆盖型半超结横向双扩散金属氧化物半导体场效应管,改善了击穿电压与比导通电阻之间的矛盾关系,实现了高的击穿电压和低的比导通电阻。
本发明方案如下:
N型埋层覆盖型半超结横向双扩散金属氧化物半导体场效应管,包括:
P型衬底;
位于所述P型衬底上P型外延层表面的P型基区;
位于所述P型基区部分表面的N型源区;
半超级结区,包括N型柱区和P型柱区;该半超级结区的P型底端辅助层(bottomassist layer)位于所述P型衬底上P型外延层表面并与P型基区邻接;
位于半超级结区部分表面的N型漏区;
其特殊之处在于:
所述P型基区与N型漏区之间设置有N型掺杂埋层,覆盖在P型底端辅助层和半超级结区余下部分的表面。
基于以上方案,本发明还进一步作如下优化:
上述半超级结区采用N型柱区与P型柱区横向周期间隔排放,各个N型柱区的宽度相同,各个P型柱区的宽度相同。进一步的,每个N型柱区与每个P型柱区的宽度最好也相同。
上述N型掺杂埋层的横截面为规则图形(当然,也可以为不规则的图形),以圆形或矩形为佳。
上述N型掺杂埋层的纵截面为规则图形(当然,也可以为不规则的图形),以圆形或矩形为佳。
上述N型掺杂埋层的浓度是均匀的(当然,也可以是非均匀的)。
当然,本发明的LDMOS也可以为P沟道,则结构与以上N沟道方案的“P”、“N”关系对调,即改为“N型衬底”、“N型基区”、“P型源区”、“P型漏区”、“N型底端辅助层”、“P型掺杂埋层”……在此不再赘述。
本发明的有益效果如下:
通过在传统的SJ-LDMOS器件结构中引入一层N型埋层,该埋层位于半超级结层及相邻P区上方。与传统的SJ-LDMOS相比,本发明通过N型埋层的作用,补偿了超级结内N型柱区和P型柱区之间的电荷不平衡,克服了衬底辅助效应,提高了击穿电压;并且由于是半超级结,在表面引入一个电场峰,进一步提高击穿电压。同时,N型埋层额外增加一条新的导电路径,降低比导通电阻。因此比一般的方案击穿电压和比导通电阻的优化可以得到进一步的提升。
本方案器件制造简单,可操作性较强。
附图说明
图1为本发明N型埋层覆盖型半超结横向双扩散金属氧化物半导体场效应管结构的三维示意图。
图2是图1中漂移区沿AOC方向的截面图。
具体实施方式
参见图1和图2,下面以一种N型埋层覆盖型(N沟道)半超结横向双扩散金属氧化物半导体场效应管为例来具体介绍本发明实施例中新结构。本领域技术人员应当能够认识到,该实施例并非对本发明保护范围的限制。
该N型埋层覆盖型半超结横向双扩散金属氧化物半导体场效应管,其包括:
P型衬底1;
位于所述P型衬底上P型外延层表面的P型基区2;
位于所述P型基区部分表面的N型源区7;
半超级结区,采用N型柱区4与P型柱区5横向周期间隔排放(图中示意了两个周期),各个N型柱区的宽度相同,各个P型柱区的宽度相同。进一步的,每个N型柱区与每个P型柱区的宽度最好也相同。
半超级结区的P型底端辅助层3位于所述P型衬底上P型外延层的表面并与P型基区2邻接;
半超级结区上形成重掺杂N型漏区;
P型基区2与N型漏区6之间设置有N型掺杂埋层8,覆盖在P型底端辅助层和半超级结区余下部分的表面,即如图1中P型基区与N型漏区之间的所有区域完全被N型掺杂埋层覆盖。
上述N型埋层覆盖型半超结横向双扩散金属氧化物半导体场效应管的制作过程,其步骤包括:
在所述P型半导体衬底上P型外延层上形成P型基区;
在所述P型基区中形成N型源区;
在所述半导体衬底与N型漏区相邻接的位置形成半超级结区,包括横向周期间隔排放的N型柱区和P型柱区;
在所述半超级结区及相邻P区上形成N型埋层;
在所述N型埋层及半超级结区上形成重掺杂N型漏区。
具体的掺杂过程,现有技术中已有很成熟的技术,在此不再详述。
本发明的技术方案,通过N型埋层的作用,补偿了超级结内N型柱区和P型柱区之间的电荷不平衡,克服了衬底辅助效应,提高了击穿电压;并且由于是半超级结,在表面引入一个电场峰,进一步提高击穿电压。同时,N型埋层额外增加一条新的导电路径,降低比导通电阻。由此改善了LDMOS的击穿电压与比导通电阻之间的矛盾关系,因此为实现集成技术提供了一种新的器件结构。

Claims (10)

1.一种N型埋层覆盖型半超结横向双扩散金属氧化物半导体场效应管,包括:
P型衬底;
位于所述P型衬底上P型外延层表面的P型基区;
位于所述P型基区部分表面的N型源区;
半超级结区,包括N型柱区和P型柱区;该半超级结区的P型底端辅助层位于所述P型衬底上P型外延层表面并与P型基区邻接;
位于半超级结区部分表面的N型漏区;
其特征在于:
所述P型基区与N型漏区之间设置有N型掺杂埋层,覆盖在P型底端辅助层和半超级结区余下部分的表面。
2.根据权利要求1所述的N型埋层覆盖型半超结横向双扩散金属氧化物半导体场效应管,其特征在于:所述半超级结区采用N型柱区与P型柱区横向周期间隔排放,各个N型柱区的宽度相同,各个P型柱区的宽度相同。
3.根据权利要求1或2所述的N型埋层覆盖型半超结横向双扩散金属氧化物半导体场效应管,其特征在于:所述N型掺杂埋层的横截面和/或纵截面为规则图形。
4.根据权利要求3所述的N型埋层覆盖型半超结横向双扩散金属氧化物半导体场效应管,其特征在于:所述规则图形为圆形或矩形。
5.根据权利要求1所述的N型埋层覆盖型半超结横向双扩散金属氧化物半导体场效应管,其特征在于:所述N型掺杂埋层的浓度是均匀的。
6.一种P型埋层覆盖型半超结横向双扩散金属氧化物半导体场效应管,包括:
N型衬底;
位于所述N型衬底上N型外延层表面的相邻接的N型基区;
位于所述N型基区部分表面的P型源区;
半超级结区,包括N型柱区和P型柱区;该半超级结区的N型底端辅助层位于所述N型衬底上N型外延层表面并与N型基区邻接;
位于半超级结区部分表面的P型漏区;
其特征在于:
所述N型基区与P型漏区之间设置有P型掺杂埋层,覆盖在N型底端辅助层和半超级结区余下部分的表面。
7.根据权利要求6所述的P型埋层覆盖型半超结横向双扩散金属氧化物半导体场效应管,其特征在于:所述半超级结区采用N型柱区与P型柱区横向周期间隔排放,各个N型柱区的宽度相同,各个P型柱区的宽度相同。
8.根据权利要求6或7所述的P型埋层覆盖型半超结横向双扩散金属氧化物半导体场效应管,其特征在于:所述P型掺杂埋层的横截面和/或纵截面为规则图形。
9.根据权利要求8所述的P型埋层覆盖型半超结横向双扩散金属氧化物半导体场效应管,其特征在于:所述规则图形为圆形或矩形。
10.根据权利要求6所述的P型埋层覆盖型半超结横向双扩散金属氧化物半导体场效应管,其特征在于:所述P型掺杂埋层的浓度是均匀的。
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CN103165678A (zh) * 2013-03-12 2013-06-19 电子科技大学 一种超结ldmos器件

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TWI408811B (zh) * 2011-02-25 2013-09-11 Richtek Technology Corp 高壓元件及其製造方法

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US6528849B1 (en) * 2000-08-31 2003-03-04 Motorola, Inc. Dual-gate resurf superjunction lateral DMOSFET
CN101819998A (zh) * 2010-04-29 2010-09-01 哈尔滨工程大学 具有应变硅结构的高压低功耗soi ldmos 晶体管
CN102130176A (zh) * 2010-12-31 2011-07-20 中国科学院上海微系统与信息技术研究所 一种具有缓冲层的soi超结ldmos器件
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