CN104796135A - Low-distortion spike suppression phase selector - Google Patents
Low-distortion spike suppression phase selector Download PDFInfo
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- CN104796135A CN104796135A CN201510196901.7A CN201510196901A CN104796135A CN 104796135 A CN104796135 A CN 104796135A CN 201510196901 A CN201510196901 A CN 201510196901A CN 104796135 A CN104796135 A CN 104796135A
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Abstract
The invention relates to a low-distortion spike suppression phase selector comprising first and second resistive load differential amplifiers, first and second double-phase switch controllers and a clock signal generator used for spike suppression and complementary overlapping; the output end of the second resistive load differential amplifier is connected to the second double-phase switch controller; the positive and negative output signal ends of the first and second double-phase switch controllers are shorted and are connected to positive and negative ends of an output port VOUT; the clock signal generator is connected with the first and second double-phase switch controllers. The low-distortion spike suppression phase selector according to the technical scheme, the spike suppression and complementary overlapping clock signal generator is used to provide the switches with control signals, a delay phase inverter in the clock signal generator is used to overlap switch control signals which control the phases of output signals, the output signals of the selector are therefore smoothly transitional during phase conversion, and distortion performance and phase noise performance of a whole phase-locked loop is improved.
Description
Technical field
The present invention relates to signal handling equipment field, be specifically related to the implantation methods of a kind of vegetables.
Background technology
The four phase phase selectors used in previous phase-locked loop can provide the Selecting phasing of 0 °, 90 °, 180 ° and 270 °, according to digital controlled signal, its output signal carries out selecting and phase transition in 0 °, 90 °, 180 ° and 270 ° of four phase signal branch roads, thus completes required division function; The selection of phase place adopts switch to realize with conversion usually, but the moment of switch opens and turns off and can produce spike waveform, such as, at 0-T in phase transition place in the output signal
1in the moment, phase selector selects the input signal of 0 ° of phase place as output always, at T
2in the moment, phase selector selects the input signal of 90 ° of phase places as output, therefore, at T
2in the moment, signal phase will make to appear as spike waveform output signal from the conversion of 0 ° to 90 ° instantaneously, and these spike waveforms can be present in the output signal of whole phase-locked loop, thus affect distortion performance and the phase noise performance of whole phase-locked loop.
Summary of the invention
Object of the present invention is just to provide a kind of low distortion peak restrained phase selector, and it can effectively solve the problem, and the output signal of phase selector is shown as in phase transition process and seamlessly transits.
For achieving the above object, the present invention implements by the following technical solutions:
A kind of low distortion peak restrained phase selector, it is characterized in that: comprise first and second ohmic load differential amplifier, first and second Double-phase switch controller and for the complementary overlapping clock signal generator of peak restrained, the input of the first ohmic load differential amplifier connects signal input part VIN0, VIN180 of 0 °, 180 °, and the output of the first ohmic load differential amplifier connects the first Double-phase switch controller; The input of the second ohmic load differential amplifier connects signal input part VIN90, VIN270 of 90 °, 270 °, the output of the second ohmic load differential amplifier connects the second Double-phase switch controller, the positive and negative output signal end difference short circuit of first and second Double-phase switch controller also connects the positive and negative terminal of output port VOUT respectively, and clock signal generator is connected with first and second Double-phase switch controller respectively.
In technique scheme, by the complementary overlapping clock signal generator of employing peak restrained for phase selector switch provides control signal, in this clock signal generator, adopting delaying type inverter to make to control each switch controlling signal outputed signal mutually produces overlapping, thus the output signal of phase selector is shown as in phase transition process seamlessly transit, and then improve distortion performance and the phase noise performance of overall phase-locked loop.
Accompanying drawing explanation
Fig. 1 is structural principle block diagram of the present invention;
Fig. 2 be first and second ohmic load differential amplifier and first and second Double-phase switch controller realize schematic diagram;
Fig. 3 is the circuit structure schematic diagram of the complementary overlapping clock signal generator of peak restrained;
Fig. 4 is the circuit structure schematic diagram of inverter INV1, INV3, INV5, INV7;
Fig. 5 is the circuit structure schematic diagram of inverter INV2, INV4, INV6, INV8;
Fig. 6 is the circuit structure schematic diagram of NAND gate NAND4, NAND gate NAND2, NAND gate NAND3, NAND gate NAND1;
The switching circuit structure schematic diagram of Fig. 7 for using in Fig. 2.
Embodiment
In order to make objects and advantages of the present invention clearly understand, below in conjunction with embodiment, the present invention is specifically described.Should be appreciated that following word only in order to describe one or more concrete execution modes of the present invention, considered critical is not carried out to the protection range that the present invention specifically asks.
The technical scheme that the present invention takes as shown in Figure 1, a kind of low distortion peak restrained phase selector, comprise first and second ohmic load differential amplifier 31,32, first and second Double-phase switch controls, 21,22 and for the complementary overlapping clock signal generator 10 of peak restrained, the input of the first ohmic load differential amplifier 31 connects signal input part VIN0, VIN180 of 0 °, 180 °, and the output of the first ohmic load differential amplifier 31 connects the first Double-phase switch controller 21; The input of the second ohmic load differential amplifier 32 connects signal input part VIN90, VIN270 of 90 °, 270 °, the output of the second ohmic load differential amplifier 32 connects the second Double-phase switch controller 22, the positive and negative output signal end difference short circuit of first and second Double-phase switch controller also connects the positive and negative terminal of output port VOUT respectively, and clock signal generator 10 is connected with first and second Double-phase switch controller respectively.First Double-phase switch controller is 0 °/180 ° Double-phase switch controllers, and the second Double-phase switch controller is 90 °/270 ° Double-phase switch controllers.The complementary overlapping clock signal generator 10 of peak restrained is respectively 0 °/180 °, 90 °/270 ° Double-phase switch controllers provides control signal, input signal enters first and second ohmic load differential amplifier from VIN0, VIN90, VIN180, VIN270 port respectively and carries out pre-amplification, signal after amplification enters in first and second Double-phase switch controller respectively, the positive and negative output signal end short circuit respectively of the positive and negative output signal end of 0 °/180 ° of Double-phase switch controllers and 90 °/270 ° of Double-phase switch controllers, and connect the positive and negative port of output port VOUT.The present invention is on the basis of traditional four phase phase selectors, the complementary overlapping clock signal generator 10 of peak restrained is adopted to provide control signal for the switch of first and second Double-phase switch controller kind, by arranging the delay of control signal, the output signal of phase selector is shown as in phase transition process seamlessly transit, and unconventional spike waveform.
Concrete operations are:
First and second ohmic load differential amplifier and first and second Double-phase switch controller form the core circuit module of four phase phase selectors, and as shown in Figure 2, VIN0, VIN90, VIN180, VIN270 are four phase signals inputs to core circuit module; Supply voltage VDD divides one end of four tunnels difference contact resistance R1, R2, R3 and R4, the input of the other end connecting valve S1, S3 of resistance R1 and the drain electrode of transistor M1, the output of the other end connecting valve S2, S4 of resistance R2 and the drain electrode of transistor M2, the input of the other end connecting valve S5, S7 of resistance R3 and the drain electrode of transistor M3, the output of the other end connecting valve S6, S8 of resistance R4 and the drain electrode of transistor M4; The cathode output end of the output of switch S 1 input of connecting valve S2, the output of switch S 5, the input of switch S 6 and output VOUT respectively; The cathode output end of the output of switch S 3 input of connecting valve S4, the output of switch S 7, the input of switch S 8 and output VOUT respectively; Switch S 1 is identical with the control signal of S4, and switch S 2 is identical with the control signal of S3, and switch S 5 is identical with the control signal of S8, and switch S 6 is identical with the control signal of S7; Four phase signals input VIN0, VIN90, VIN180, VIN270 connect the grid of transistor M1, M3, M2 and M4 respectively; The source shorted of transistor M1, M2 also connects the input of current source I1, the output access ground GND of current source I 1; The source shorted of transistor M3, M4 also connects the input of current source I2, the output access ground GND of current source I2.
Fig. 3 is the circuit structure schematic diagram of clock signal generator 10, clock signal generator 10 comprises series connection successively and connects and composes the inverter INV2 of loop from beginning to end, NAND gate NAND1, inverter INV3, inverter INV4, NAND gate NAND2, inverter INV5, inverter INV6, NAND gate NAND3, inverter INV7, inverter INV8, NAND gate NAND4 and inverter INV1, the short circuit point connection control signal output terminals A 0 of NAND gate NAND4 and inverter INV1, the short circuit point connection control signal output terminals A 3 of NAND gate NAND1 and inverter INV3, the short circuit point connection control signal output terminals A 2 of NAND gate NAND2 and inverter INV5, the short circuit point connection control signal output terminals A 1 of NAND gate NAND3 and inverter INV7, control signal output terminals A 0, A3 is connected with the first Double-phase switch controller, control signal output terminals A 1, A2 is connected with the second Double-phase switch controller, concrete can be: control signal output terminals A 0 is for control chart 2 breaker in middle S1 and S4, control signal output terminals A 3, for control chart 2 breaker in middle S2 and S3, control signal output terminals A 2 is for control chart 2 breaker in middle S5 and S8, control signal output terminals A 1 is for control chart 2 breaker in middle S6 and S7.NAND gate NAND4, NAND gate NAND2, NAND gate NAND3, NAND gate NAND1 connect respectively the complementary overlap signal C0 of two-phase that external circuit provides,
c1 and
The circuit structure of inverter INV1, INV3, INV5, INV7 is identical, Fig. 4 is the circuit structure schematic diagram of inverter INV1, INV3, INV5, INV7, inverter INV1 bag inverter input signal end VIN, inverter output signal end VOUT, transistor M5, M6, the source electrode of transistor M5, M6 connects power vd D, and the grid short circuit of transistor M5, M6 also connects input signal end VIN; The drain electrode short circuit of transistor M5, M6 also connects one end and the output signal end VOUT of load capacitance CL respectively; The source ground of transistor M6, the other end ground connection of load capacitance CL.
The circuit structure of inverter INV2, INV4, INV6, INV8 is identical, and Fig. 5 is the circuit structure schematic diagram of inverter INV2, INV4, INV6, INV8; VIN2 comprises inverter input signal end VIN, inverter output signal end VOUT, transistor M7, M8, M9; The source electrode of transistor M7 connects power vd D, and the grid short circuit of transistor M7, M9 also connects the input signal end VIN of inverter, and the drain electrode short circuit of transistor M7, M8 also connects the output signal end VOUT of inverter; The grid of transistor M8 connects the bias voltage input VB that external circuit provides, the source electrode of transistor M8 and the drain electrode short circuit of transistor M9, the source ground of transistor M9.
The circuit structure of NAND gate NAND4, NAND gate NAND2, NAND gate NAND3, NAND gate NAND1 is identical, Figure 6 shows that the circuit structure schematic diagram of NAND gate NAND4, NAND gate NAND2, NAND gate NAND3, NAND gate NAND1, NAND gate NAND1 comprises input signal end IN1, IN2 of NAND gate, the output signal end OUT of NAND gate and transistor M10, M12, M13, M14; The source electrode of transistor M10, M14 connects power vd D respectively, and the grid short circuit of transistor M10, M12 also connects input signal end IN1; The grid short circuit of transistor M11, M13 also connects input signal end IN2; The drain electrode of transistor M10 and the source shorted of transistor M11, the drain electrode short circuit of transistor M12, M13 also connects the drain electrode of transistor M11 and the grid of transistor M14, M15 respectively; The drain electrode short circuit of transistor M14, M15 also connects the output signal end OUT of NAND gate; The source grounding of transistor M12, M13, M15.
The switching circuit structure schematic diagram of Fig. 7 for using in Fig. 2; IN is switch input signal end, and OUT is switch output signal end, D and
for switch controlling signal end, when D is digital signal " 1 ",
during for digital signal " 0 ", switch conduction; When D is digital signal " 0 ",
during for digital signal " 1 ", switch cuts out; The grid connection control signal end D of transistor M17, the source shorted of drain electrode and transistor M18, and connecting valve input signal end IN; The source electrode of transistor M17 and the drain electrode short circuit of transistor M18, and connecting valve output signal end OUT; The grid connection control signal end of transistor M18
In a word, the present invention can make the output signal of phase selector show as in phase transition process to seamlessly transit, avoid the distortion performance and the phase noise performance that appear as the whole phase-locked loop of spike waveform influence.
The above is only the preferred embodiment of the present invention; should be understood that; for those skilled in the art; to know in the present invention after contents; under the premise without departing from the principles of the invention; can also make some equal conversion to it and substitute, these convert on an equal basis and substitute and also should be considered as belonging to protection scope of the present invention.
Claims (5)
1. a low distortion peak restrained phase selector, it is characterized in that: comprise first and second ohmic load differential amplifier, first and second Double-phase switch controller and for the complementary overlapping clock signal generator of peak restrained, the input of the first ohmic load differential amplifier connects signal input part VIN0, VIN180 of 0 °, 180 °, and the output of the first ohmic load differential amplifier connects the first Double-phase switch controller; The input of the second ohmic load differential amplifier connects signal input part VIN90, VIN270 of 90 °, 270 °, the output of the second ohmic load differential amplifier connects the second Double-phase switch controller, the positive and negative output signal end difference short circuit of first and second Double-phase switch controller also connects the positive and negative terminal of output port VOUT respectively, and clock signal generator is connected with first and second Double-phase switch controller respectively.
2. low distortion peak restrained phase selector according to claim 1, is characterized in that: clock signal generator comprises series connection successively and connects and composes the inverter INV2 of loop from beginning to end, NAND gate NAND1, inverter INV3, inverter INV4, NAND gate NAND2, inverter INV5, inverter INV6, NAND gate NAND3, inverter INV7, inverter INV8, NAND gate NAND4 and inverter INV1, the short circuit point connection control signal output terminals A 0 of NAND gate NAND4 and inverter INV1, the short circuit point connection control signal output terminals A 3 of NAND gate NAND1 and inverter INV3, the short circuit point connection control signal output terminals A 2 of NAND gate NAND2 and inverter INV5, the short circuit point connection control signal output terminals A 1 of NAND gate NAND3 and inverter INV7, control signal output terminals A 0, A3 is connected with the first Double-phase switch controller, control signal output terminals A 1, A2 is connected with the second Double-phase switch controller, NAND gate NAND4, NAND gate NAND2, NAND gate NAND3, NAND gate NAND1 connects the complementary overlap signal C0 of two-phase that external circuit provides respectively,
c1 and
3. low distortion peak restrained phase selector according to claim 2, it is characterized in that: the circuit structure of inverter INV1, INV3, INV5, INV7 is identical, inverter INV1 bag inverter input signal end VIN, inverter output signal end VOUT, transistor M5, M6, the source electrode of transistor M5, M6 connects power vd D, and the grid short circuit of transistor M5, M6 also connects input signal end VIN; The drain electrode short circuit of transistor M5, M6 also connects one end and the output signal end VOUT of load capacitance CL respectively; The source ground of transistor M6, the other end ground connection of load capacitance CL.
4. low distortion peak restrained phase selector according to claim 2, it is characterized in that: the circuit structure of inverter INV2, INV4, INV6, INV8 is identical, VIN2 comprises inverter input signal end VIN, inverter output signal end VOUT, transistor M7, M8, M9; The source electrode of transistor M7 connects power vd D, and the grid short circuit of transistor M7, M9 also connects the input signal end VIN of inverter, and the drain electrode short circuit of transistor M7, M8 also connects the output signal end VOUT of inverter; The grid of transistor M8 connects the bias voltage input VB that external circuit provides, the source electrode of transistor M8 and the drain electrode short circuit of transistor M9, the source ground of transistor M9.
5. low distortion peak restrained phase selector according to claim 2, it is characterized in that: the circuit structure of NAND gate NAND4, NAND gate NAND2, NAND gate NAND3, NAND gate NAND1 is identical, NAND gate NAND1 comprises input signal end IN1, IN2 of NAND gate, the output signal end OUT of NAND gate and transistor M10, M12, M13, M14; The source electrode of transistor M10, M14 connects power vd D respectively, and the grid short circuit of transistor M10, M12 also connects input signal end IN1; The grid short circuit of transistor M11, M13 also connects input signal end IN2; The drain electrode of transistor M10 and the source shorted of transistor M11, the drain electrode short circuit of transistor M12, M13 also connects the drain electrode of transistor M11 and the grid of transistor M14, M15 respectively; The drain electrode short circuit of transistor M14, M15 also connects the output signal end OUT of NAND gate; The source grounding of transistor M12, M13, M15.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510196901.7A CN104796135B (en) | 2015-04-23 | 2015-04-23 | A kind of low distortion peak restrained phase selector |
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| CN201510196901.7A CN104796135B (en) | 2015-04-23 | 2015-04-23 | A kind of low distortion peak restrained phase selector |
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| CN104796135B CN104796135B (en) | 2017-12-26 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106026991A (en) * | 2016-05-06 | 2016-10-12 | 龙迅半导体（合肥）股份有限公司 | Phase interpolator and control method thereof |
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| US20130147569A1 (en) * | 2011-12-12 | 2013-06-13 | Stephen Beccue | RTWO-Based Pulse Width Modulator |
| CN103259535A (en) * | 2012-02-15 | 2013-08-21 | 联咏科技股份有限公司 | Delay phase locking return circuit and delay phase locking method |
| CN103780252A (en) * | 2012-10-22 | 2014-05-07 | 联发科技股份有限公司 | Clock generating apparatus, method for clock generating apparatus, and fractional frequency divider |
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2015
- 2015-04-23 CN CN201510196901.7A patent/CN104796135B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130147569A1 (en) * | 2011-12-12 | 2013-06-13 | Stephen Beccue | RTWO-Based Pulse Width Modulator |
| CN103259535A (en) * | 2012-02-15 | 2013-08-21 | 联咏科技股份有限公司 | Delay phase locking return circuit and delay phase locking method |
| CN103780252A (en) * | 2012-10-22 | 2014-05-07 | 联发科技股份有限公司 | Clock generating apparatus, method for clock generating apparatus, and fractional frequency divider |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106026991A (en) * | 2016-05-06 | 2016-10-12 | 龙迅半导体（合肥）股份有限公司 | Phase interpolator and control method thereof |
| CN106026991B (en) * | 2016-05-06 | 2018-08-10 | 龙迅半导体（合肥）股份有限公司 | A kind of phase interpolator and its control method |
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| CN104796135B (en) | 2017-12-26 |
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