CN104796135B - A kind of low distortion peak restrained phase selector - Google Patents
A kind of low distortion peak restrained phase selector Download PDFInfo
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- CN104796135B CN104796135B CN201510196901.7A CN201510196901A CN104796135B CN 104796135 B CN104796135 B CN 104796135B CN 201510196901 A CN201510196901 A CN 201510196901A CN 104796135 B CN104796135 B CN 104796135B
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- phase inverter
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Abstract
The present invention relates to a kind of low distortion peak restrained phase selector, including first and second ohmic load difference amplifier, first and second Double-phase switch controller and for the complementary overlapping clock signal generator of peak restrained, the output end of second resistance load differential amplifier connects the second Double-phase switch controller, the positive and negative output signal end difference short circuit of first and second Double-phase switch controller simultaneously connects output port VOUT positive and negative terminal respectively, and clock signal generator is connected with first and second Double-phase switch controller respectively.In above-mentioned technical proposal, the complementary overlapping clock signal generator of peak restrained is used to provide control signal for phase selector switch, in the clock signal generator, make it that controlling the switch controlling signal of each phase output signal to produce overlaps using delaying type phase inverter, so that the output signal of phase selector shows as seamlessly transitting during phase transition, and then improve the distortion performance and phase noise performance of overall phaselocked loop.
Description
Technical field
The present invention relates to signal handling equipment field, and in particular to a kind of implantation methods of vegetables.
Background technology
Four phase phase selectors used in previous phaselocked loop can provide 0 °, 90 °, 180 ° and 270 ° of phase choosing
Select, according to digital controlled signal, its output signal selected in 0 °, 90 °, 180 ° and 270 ° four phase signal branch roads and
Phase transition, so as to complete required division function；The selection of phase is realized with conversion generally use switch, however, switch
Moment be switched on and off can be in the output signal phase transition at produce spike waveform, for example, in 0-T1Moment, phase choosing
Select device and select the input signal of 0 ° of phase always as output, in T2Moment, phase selector select the input signal of 90 ° of phases
As output, therefore, in T2Moment, signal phase moment changing from 0 ° to 90 ° will make to occur into peaked wave in output signal
Shape, these spike waveforms can be present in the output signal of whole phaselocked loop, so as to influence the distortion performance of whole phaselocked loop and
Phase noise performance.
The content of the invention
It is an object of the invention to provide a kind of low distortion peak restrained phase selector, and it can effectively solve above-mentioned ask
Topic so that the output signal of phase selector shows as seamlessly transitting during phase transition.
To achieve the above object, the present invention is implemented using following technical scheme：
A kind of low distortion peak restrained phase selector, it is characterised in that：Including first and second ohmic load differential amplification
Device, first and second Double-phase switch controller and the clock signal generator overlapping for peak restrained complementation, first resistor load
The input of difference amplifier connects 0 °, 180 ° signal input part VIN0, VIN180, first resistor load differential amplifier
Output end connects the first Double-phase switch controller；The input of second resistance load differential amplifier connects 90 °, 270 ° of signal
Input VIN90, VIN270, output end the second Double-phase switch controller of connection of second resistance load differential amplifier, first,
The positive and negative output signal end difference short circuit of two Double-phase switch controllers simultaneously connects output port VOUT positive and negative terminal respectively, clock letter
Number generator is connected with first and second Double-phase switch controller respectively.
In above-mentioned technical proposal, switched by using the complementary overlapping clock signal generator of peak restrained for phase selector
Control signal is provided, in the clock signal generator, the switch for controlling each phase output signal is caused using delaying type phase inverter
Control signal, which produces, to be overlapped, so that the output signal of phase selector shows as seamlessly transitting during phase transition,
And then improve the distortion performance and phase noise performance of overall phaselocked loop.
Brief description of the drawings
Fig. 1 is the structural principle block diagram of the present invention；
Fig. 2 is the realization principle figure of first and second ohmic load difference amplifier and first and second Double-phase switch controller；
Fig. 3 is the circuit structure schematic diagram of the complementary overlapping clock signal generator of peak restrained；
Fig. 4 is phase inverter INV1, INV3, INV5, INV7 circuit structure schematic diagram；
Fig. 5 is phase inverter INV2, INV4, INV6, INV8 circuit structure schematic diagram；
Fig. 6 is NAND gate NAND4, NAND gate NAND2, NAND gate NAND3, NAND gate NAND1 circuit structure schematic diagram；
Fig. 7 is the switching circuit structure schematic diagram used in Fig. 2.
Embodiment
In order that objects and advantages of the present invention are more clearly understood, the present invention is carried out specifically with reference to embodiments
It is bright.It should be appreciated that following word only to describe the present invention one or more of specific embodiments, not to the present invention
The protection domain specifically asked carries out considered critical.
Technical scheme that the present invention takes as shown in figure 1, a kind of low distortion peak restrained phase selector, including first,
Two ohmic load difference amplifiers 31,32, the control of first and second Double-phase switch, 21,22 and complementary overlapping for peak restrained
Clock signal generator 10, the input of first resistor load differential amplifier 31 connect 0 °, 180 ° of signal input part VIN0,
VIN180, the output end of first resistor load differential amplifier 31 connect the first Double-phase switch controller 21；Second resistance loads
The input of difference amplifier 32 connects 90 °, 270 ° signal input part VIN90, VIN270, the amplification of second resistance load differential
The output end of device 32 connects the second Double-phase switch controller 22, the positive and negative output signal end point of first and second Double-phase switch controller
Other short circuit and the positive and negative terminal for connecting output port VOUT respectively, clock signal generator 10 respectively with first and second Double-phase switch control
Device processed is connected.First Double-phase switch controller is 0 °/180 ° Double-phase switch controllers, the second Double-phase switch controller is 90 °/
270 ° of Double-phase switch controllers.The complementary overlapping clock signal generator 10 of peak restrained is respectively 0 °/180 °, 90 °/270 ° two-phases
Switch controller provides control signal, and input signal enters first and second from VIN0, VIN90, VIN180, VIN270 port respectively
Pre-amplification is carried out in ohmic load difference amplifier, the signal after amplification is respectively enterd in first and second Double-phase switch controller,
The positive and negative output signal end of 0 °/180 ° Double-phase switch controllers and the positive and negative output signal end of 90 °/270 ° Double-phase switch controllers
Short circuit respectively, and connect output port VOUT positive and negative port.The present invention is on the basis of traditional four phase phase selectors, is adopted
With the complementary overlapping clock signal generator 10 of peak restrained control letter is provided for the switch of first and second Double-phase switch controller kind
Number, by the delay for setting control signal so that the output signal of phase selector is shown as smoothly during phase transition
Transition, and unconventional spike waveform.
Concrete operations are：
First and second ohmic load difference amplifier and first and second Double-phase switch controller form four phase phase selectors
Core circuit module, core circuit module is as shown in Fig. 2 VIN0, VIN90, VIN180, VIN270 are four phase signals inputs；
VDD points of four tunnels of supply voltage connect resistance R1, R2, R3 and R4 one end respectively, resistance the R1 other end connecting valve S1, S3's
The drain electrode of input and transistor M1, the resistance R2 other end connecting valve S2, S4 output end and transistor M2 leakage
Pole, the drain electrode of resistance the R3 other end connecting valve S5, S7 input and transistor M3, resistance R4 other end connection are opened
Close S6, S8 output end and transistor M4 drain electrode；Switch S1 output end difference connecting valve S2 input, switch S5
Output end, switch S6 input and output end VOUT cathode output end；Switch S3 output end difference connecting valve
S4 input, switch S7 output end, switch S8 input and output end VOUT cathode output end；Switch S1 and S4
Control signal it is identical, switch that S2 and S3 control signal is identical, it is identical to switch S5 and S8 control signal, switch S6 and S7
Control signal is identical；Four phase signals input VIN0, VIN90, VIN180, VIN270 connect transistor M1, M3, M2 and M4 respectively
Grid；Transistor M1, M2 source shorted and the input for connecting current source I1, current source I 1 output end access ground
GND；Transistor M3, M4 source shorted and the input for connecting current source I2, current source I2 output end access ground GND.
Fig. 3 is the circuit structure schematic diagram of clock signal generator 10；Clock signal generator 10 include be sequentially connected in series and
Head and the tail connect and compose the phase inverter INV2 of loop, NAND gate NAND1, phase inverter INV3, phase inverter INV4, NAND gate NAND2, anti-
Phase device INV5, phase inverter INV6, NAND gate NAND3, phase inverter INV7, phase inverter INV8, NAND gate NAND4 and phase inverter
INV1, NAND gate NAND4 and phase inverter INV1 short circuit point connection control signal output terminals A 0, NAND gate NAND1 and phase inverter
INV3 short circuit point connection control signal output terminals A 3, NAND gate NAND2 and phase inverter INV5 short circuit point connection control signal
Output terminals A 2, NAND gate NAND3 and phase inverter INV7 short circuit point connection control signal output terminals A 1, control signal output
A0, A3 are connected with the first Double-phase switch controller, and control signal output A1, A2 are connected with the second Double-phase switch controller
Connect, can be specifically：Control signal output A0 is used to switch S1 and S4 in control figure 2；Control signal output A3, for controlling
S2 and S3 is switched in drawing 2；Control signal output A2 is used to switch S5 and S8 in control figure 2；Control signal output A1 is used
S6 and S7 is switched in control figure 2.NAND gate NAND4, NAND gate NAND2, NAND gate NAND3, NAND gate NAND1 are connected respectively
The two-phase complementation overlap signal C0 of external circuit offer,C1 and
Phase inverter INV1, INV3, INV5, INV7 circuit structure are identical, Fig. 4 be phase inverter INV1, INV3, INV5,
INV7 circuit structure schematic diagram, phase inverter INV1 bag phase inverter input signals end VIN, inverter output signal end VOUT, crystalline substance
Body pipe M5, M6, transistor M5, M6 source electrode connect power vd D, and transistor M5, M6 grid short circuit simultaneously connect input signal end
VIN；Transistor M5, M6 drain electrode short circuit and one end and the output signal end VOUT for connecting load capacitance CL respectively；Transistor M6
Source ground, load capacitance CL the other end ground connection.
Phase inverter INV2, INV4, INV6, INV8 circuit structure are identical, Fig. 5 be phase inverter INV2, INV4, INV6,
INV8 circuit structure schematic diagram；VIN2 includes phase inverter input signal end VIN, inverter output signal end VOUT, transistor
M7、M8、M9；Transistor M7 source electrode connection power vd D, transistor M7, M9 grid short circuit and the input letter for connecting phase inverter
Number end VIN, transistor M7, M8 drain electrode short circuit simultaneously connects the output signal end VOUT of phase inverter；Transistor M8 grid connection
The bias voltage input VB that external circuit provides, transistor M8 source electrode and transistor M9 drain electrode short circuit, transistor M9's
Source ground.
NAND gate NAND4, NAND gate NAND2, NAND gate NAND3, NAND gate NAND1 circuit structure are identical, shown in Fig. 6
For NAND gate NAND4, NAND gate NAND2, NAND gate NAND3, NAND gate NAND1 circuit structure schematic diagram, NAND gate NAND1
Input signal end IN1, IN2 including NAND gate, the output signal end OUT and transistor M10, M12, M13, M14 of NAND gate；
Transistor M10, M14 source electrode connect power vd D respectively, and transistor M10, M12 grid short circuit simultaneously connect input signal end
IN1；Transistor M11, M13 grid short circuit simultaneously connect input signal end IN2；Transistor M10 drain electrode and transistor M11 source
Extremely short to connect, transistor M12, M13 drain electrode short circuit simultaneously connect transistor M11 drain electrode and transistor M14, M15 grid respectively
Pole；Transistor M14, M15 drain electrode short circuit simultaneously connect the output signal end OUT of NAND gate；Transistor M12, M13, M15 source electrode
It is grounded.
Fig. 7 is the switching circuit structure schematic diagram used in Fig. 2；IN is switch input signal end, and OUT exports for switch
Signal end, D andFor switch controlling signal end, when D is data signal " 1 ",For data signal " 0 " when, switch conduction；When D is
Data signal " 0 ",For data signal " 1 " when, switch close；Transistor M17 grid connection control signal end D, drain electrode and crystalline substance
Body pipe M18 source shorted, and connecting valve input signal end IN；The drain electrode of transistor M17 source electrode and transistor M18 is short
Connect, and connecting valve output signal end OUT；Transistor M18 grid connection control signal end
In a word, the present invention may be such that the output signal of phase selector shows as seamlessly transitting during phase transition,
Avoid the occurrence of as the distortion performance and phase noise performance of the whole phaselocked loop of spike waveform influence.
Described above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, after content described in the present invention is known, under the premise without departing from the principles of the invention, it can also be made some
Equal conversion and replacement, these, which convert and substituted on an equal basis, also should be regarded as belonging to protection scope of the present invention.
Claims (4)
- A kind of 1. phase selector, it is characterised in that：Including first and second ohmic load difference amplifier, first and second Double-phase switch Controller and the clock signal generator overlapping for peak restrained complementation, the input of first resistor load differential amplifier 0 °, 180 ° signal input part VIN0, VIN180 are connected, the output end of first resistor load differential amplifier connects the first two-phase Switch controller；The input of second resistance load differential amplifier connect 90 °, 270 ° of signal input part VIN90, VIN270, the output end of second resistance load differential amplifier connect the second Double-phase switch controller, first and second Double-phase switch control The positive and negative output signal end difference short circuit of device processed simultaneously connects output port VOUT positive and negative terminal respectively, clock signal generator difference It is connected with first and second Double-phase switch controller；Clock signal generator includes being sequentially connected in series and head and the tail connect and compose the phase inverter INV2 of loop, NAND gate NAND1, anti-phase It is device INV3, phase inverter INV4, NAND gate NAND2, phase inverter INV5, phase inverter INV6, NAND gate NAND3, phase inverter INV7, anti- Phase device INV8, NAND gate NAND4 and phase inverter INV1, NAND gate NAND4 are connected control letter with phase inverter INV1 short circuit point Number output terminals A 0, NAND gate NAND1 and phase inverter INV3 short circuit point connection control signal output terminals A 3, NAND gate NAND2 with Phase inverter INV5 short circuit point connection control signal output terminals A 2, NAND gate NAND3 are connected control with phase inverter INV7 short circuit point Signal output part A1 processed, control signal output A0, A3 are connected with the first Double-phase switch controller, control signal output A1, A2 are connected with the second Double-phase switch controller, NAND gate NAND4, NAND gate NAND2, NAND gate NAND3, NAND gate NAND1 connect respectively external circuit offer two-phase complementation overlap signal C0,C1 and
- 2. phase selector according to claim 1, it is characterised in that：Phase inverter INV1, INV3, INV5, INV7 electricity Line structure is identical, phase inverter INV1 bag phase inverter input signals end VIN, inverter output signal end VOUT, transistor M5, M6, Transistor M5, M6 source electrode connection power vd D, transistor M5, M6 grid short circuit simultaneously connect input signal end VIN；Transistor M5, M6 drain electrode short circuit and one end and the output signal end VOUT for connecting load capacitance CL respectively；Transistor M6 source ground, Load capacitance CL other end ground connection.
- 3. phase selector according to claim 1, it is characterised in that：Phase inverter INV2, INV4, INV6, INV8 electricity Line structure is identical, phase inverter VIN2 include phase inverter input signal end VIN, inverter output signal end VOUT, transistor M7, M8、M9；Transistor M7 source electrode connection power vd D, transistor M7, M9 grid short circuit and the input signal end for connecting phase inverter VIN, transistor M7, M8 drain electrode short circuit simultaneously connect the output signal end VOUT of phase inverter；Transistor M8 grid connection is outside The bias voltage input VB that circuit provides, transistor M8 source electrode and transistor M9 drain electrode short circuit, transistor M9 source electrode Ground connection.
- 4. phase selector according to claim 1, it is characterised in that：NAND gate NAND4, NAND gate NAND2, NAND gate NAND3, NAND gate NAND1 circuit structure are identical, and NAND gate NAND1 includes input signal end IN1, IN2 of NAND gate, and non- The output signal end OUT and transistor M10, M12, M13, M14 of door；Transistor M10, M14 source electrode connect power supply respectively VDD, transistor M10, M12 grid short circuit simultaneously connect input signal end IN1；Transistor M11, M13 grid short circuit simultaneously connect Input signal end IN2；Transistor M10 drain electrode and transistor M11 source shorted, transistor M12, M13 drain electrode short circuit are simultaneously Transistor M11 drain electrode and transistor M14, M15 grid are connected respectively；Transistor M14, M15 drain electrode short circuit simultaneously connect The output signal end OUT of NAND gate；Transistor M12, M13, M15 source grounding.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510196901.7A CN104796135B (en) | 2015-04-23 | 2015-04-23 | A kind of low distortion peak restrained phase selector |
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| CN201510196901.7A CN104796135B (en) | 2015-04-23 | 2015-04-23 | A kind of low distortion peak restrained phase selector |
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| CN104796135B true CN104796135B (en) | 2017-12-26 |
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| CN106026991B (en) * | 2016-05-06 | 2018-08-10 | 龙迅半导体（合肥）股份有限公司 | A kind of phase interpolator and its control method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103259535A (en) * | 2012-02-15 | 2013-08-21 | 联咏科技股份有限公司 | Delay phase locking return circuit and delay phase locking method |
| CN103780252A (en) * | 2012-10-22 | 2014-05-07 | 联发科技股份有限公司 | Clock generating apparatus, method for clock generating apparatus, and fractional frequency divider |
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| US8487710B2 (en) * | 2011-12-12 | 2013-07-16 | Analog Devices, Inc. | RTWO-based pulse width modulator |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103259535A (en) * | 2012-02-15 | 2013-08-21 | 联咏科技股份有限公司 | Delay phase locking return circuit and delay phase locking method |
| CN103780252A (en) * | 2012-10-22 | 2014-05-07 | 联发科技股份有限公司 | Clock generating apparatus, method for clock generating apparatus, and fractional frequency divider |
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Granted publication date: 20171226 Termination date: 20180423 |