CN104795359A - Method of forming air gaps in dielectric layers among metal interconnections - Google Patents
Method of forming air gaps in dielectric layers among metal interconnections Download PDFInfo
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- CN104795359A CN104795359A CN201510173994.1A CN201510173994A CN104795359A CN 104795359 A CN104795359 A CN 104795359A CN 201510173994 A CN201510173994 A CN 201510173994A CN 104795359 A CN104795359 A CN 104795359A
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- dielectric layer
- metal interconnecting
- interconnecting wires
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- gap
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
Abstract
The invention relates to a method of forming air gaps in dielectric layers among metal interconnections. The method includes: forming a first dielectric layer on a substrate of a semiconductor device, forming a front metal interconnection in the first dielectric layer and a first barrier layer on the surface of the front metal interconnection and the surface of the first dielectric layer; forming multiple pores in the first barrier layer by means of photoetching and etching; wet-etching the part, below the pores, of the first barrier layer, and forming gaps in the first barrier layer, with the diameter of the pores being greater than that of the pores; forming a second dielectric layer on the first barrier layer; forming a rear metal interconnection on the second dielectric layer. By wet-etching the part, below the pores, of the first barrier layer, the gaps larger than the pores are formed in the first barrier layer; during deposition of the second dielectric layer, owing to poor covering ability of a step, the sealed air gaps are formed in the first dielectric layer, and the k-value of the dielectric layers among the metal interconnections is decreased.
Description
Technical field
The present invention relates to technical field of semiconductors, be specifically related to the method forming air-gap in the dielectric layer between a kind of metal interconnecting wires.
Background technology
Along with the development of CMOS integrated circuit fabrication process and reducing of critical size, much new materials and process is applied in device fabrication, in order to improve device performance.Metallic copper is lower due to resistivity, successfully replaces the main material that aluminium becomes integrated circuit last part interconnection now.Porous low k material can realize the dielectric constant (dielectric constant of air is 1, so porous material can obtain very low k value) of about 2.5, and the RC that effectively can reduce integrated circuit postpones.In addition, between metal interconnecting wires, form air gap is also that a kind of media bulk k that well reduces is worth method.
Refer to Fig. 1, existing back segment interconnection process comprises:
Step L01: deposited barrier layer and low-k material successively in semiconductor device substrates; Here, after the first groove of front and continued interconnection process is formed and fills metal, at substrate surface deposited copper diffusion impervious layer, nitrogen doped silicon carbide (NDC) is generally, then at copper diffusion barrier layer surface deposition low-k material;
Step L02: carry out ultra-violet curing technique to low-k material, to form porous low-k material; Pore-foaming agent in this process in low-k material is driven out of and is formed porous, simultaneously film generation thickness contraction.
Step L03: through photoetching and etching technics, forms the second groove in porous low-k material, and etches away the barrier layer of the second channel bottom, to expose the filling metal in the first groove; Here, before photoetching, also relate to buffer thin film layer, the deposition etc. of metallic mask layer and antireflection film.
Step L04: carry out metal filled in the second groove, then carries out cmp to porous low-k material surface to filled metal; Thus in porous low k material, form copper interconnecting line (generally speaking using the final step of cmp as certain one deck metal connecting line of formation).At the deposited on sidewalls copper diffusion barrier layer metal of through hole and groove before metal filled, be generally TaN/Ta, its objective is and prevent copper from spreading in lowk material; The fill method of metal comprises copper plating etc.First groove and interior filling metal thereof and the second groove and interior filling metal thereof form through-hole interconnection;
Step L05: at porous low-k material surface and the metal surface deposited barrier layer of filling; Here, barrier layer is nitrogen doped silicon carbide.
Therefore, improve existing interconnection process between interconnection line, to form air-gap there is important value.
Summary of the invention
In order to overcome above problem, the present invention aims to provide the method forming air-gap in the dielectric layer between a kind of metal interconnecting wires, to reduce the k value of dielectric layer.
To achieve these goals, the invention provides the method forming air-gap in the dielectric layer between a kind of metal interconnecting wires, it comprises the following steps:
Step 01: form first medium layer in semiconductor device substrates, forms leading portion metal interconnecting wires and surperficial and described first medium layer surface deposition first barrier layer at described leading portion metal interconnecting wires in described first medium layer;
Step 02: through photoetching and etching technics, forms multiple hole in described first barrier layer;
Step 03: described first barrier layer portions below hole described in wet etching, forms space in described first barrier layer; The diameter in described space is greater than the diameter in described hole;
Step 04: form second dielectric layer on described first barrier layer, to form the air-gap of sealing in first medium layer.
Preferably, also step 05 is comprised after described step 04: in described second dielectric layer, form back segment metal interconnecting wires.
Preferably, the thickness on described first barrier layer is 150 ~ 500A.
Preferably, the material of described first medium layer or described second dielectric layer is porous low-k material.
Preferably, also comprised before described formation leading portion metal interconnecting wires in described step 01: ultra-violet curing technique is carried out to described first medium layer; Or also comprise in described step 04: ultra-violet curing technique is carried out to described second dielectric layer.
Preferably, the diameter in described hole is 20 ~ 50nm.
Preferably, in described step 02, described etching technics is plasma dry etch process.
Preferably, in described step 03, the liquid that described wet etching adopts is dilute hydrofluoric acid.
Preferably, described step 04 also comprises: carry out planarization to described second dielectric layer top.
Preferably, also comprise after described step 05: on described second dielectric layer surface and described back segment metal interconnecting wires surface deposition second barrier layer.
The method of air-gap is formed in dielectric layer between metal interconnecting wires of the present invention, by forming multiple hole in the first barrier layer, wet etching is isotropism, by these pitting corrosions to the first barrier layer portions below it, thus in the first barrier layer, form the space larger than hole, when follow-up second dielectric layer deposits, because dielectric layer is in the Step Coverage ability in space, thus in first medium layer, form the air-gap of sealing, and then reduce the k value of the dielectric layer between metal interconnecting wires.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of existing back segment interconnection process
Fig. 2 be a preferred embodiment of the present invention metal interconnecting wires between dielectric layer in form the schematic flow sheet of the method for air-gap
Each step schematic diagram of the method for air-gap is formed in dielectric layer between the metal interconnecting wires that Fig. 3 ~ 8 are a preferred embodiment of the present invention
Embodiment
For making content of the present invention clearly understandable, below in conjunction with Figure of description, content of the present invention is described further.Certain the present invention is not limited to this specific embodiment, and the general replacement known by those skilled in the art is also encompassed in protection scope of the present invention.
The method of air-gap is formed in dielectric layer between metal interconnecting wires of the present invention, by forming multiple hole in the first barrier layer, wet etching is isotropism, by these pitting corrosions to the first barrier layer portions below it, thus in the first barrier layer, form the space larger than hole, when follow-up second dielectric layer deposits, because dielectric layer is in the Step Coverage ability in space, thus in first medium layer, form the air-gap of sealing.
Below in conjunction with accompanying drawing 2 ~ 8 and specific embodiment, the method forming air-gap in the dielectric layer between metal interconnecting wires of the present invention is described in further detail.It should be noted that, accompanying drawing all adopt simplify very much form, use non-ratio accurately, and only in order to object that is convenient, that clearly reach aid illustration the present embodiment.
Refer to Fig. 2, form the method for air-gap in the dielectric layer between the metal interconnecting wires in the present embodiment, comprise the following steps:
Step 01: refer to Fig. 3, semiconductor device substrates is formed first medium layer 01, forms leading portion metal interconnecting wires 02 and surperficial and first medium layer 01 surface deposition first barrier layer 03 at leading portion metal interconnecting wires 02 in first medium layer 01;
Concrete, in the present embodiment, the material of first medium layer 01 is porous low-k material, and the process forming first medium layer 01 can comprise: first, semiconductor device substrates adopts PECVD method deposit low-k material; Then, ultra-violet curing technique is carried out to low-k material, form porous low-k material.After forming porous low-k material, the formation of leading portion metal interconnecting wires comprises: in porous low-k material, etch groove, then deposit diffusion barriers stops that the porous low-k material that the metal of follow-up filling enters into trenched side-wall spreads in the trench, can be TaN/Ta; Then, at the diffusion impervious layer surface deposition metal of groove, such as, copper plating is adopted to fill metallic copper; Finally, the mode of cmp is adopted to grind filled metal top to porous low-k material surface.The material on the first barrier layer 03 can be nitrogen doped silicon carbide, and the thickness on barrier layer is 150 ~ 500A.It should be noted that, in above-mentioned plasma dry etch process, also inevitably can remove a part of porous low-k material.
Step 02: refer to Fig. 4 a ~ 4b, through photoetching and etching technics, forms multiple hole 04 in the first barrier layer 03;
Concrete, in the present embodiment, first, deposited bottom anti-reflecting layer and photoresist successively, then, through exposure and development, forms sectional hole patterns in the photoresist; Be that mask using plasma dry etch process etches and portals 04 in the first barrier layer 03 again with photoresist; Here, hole 04 pattern can be circular hole pattern, also can be polygonal hole pattern, can also be other sectional hole patterns; The number in hole 04 and distribution design according to actual needs, and main Consideration comprises overall k value and the mechanical performance of first medium layer between interconnection line or second dielectric layer.In the present embodiment, Fig. 4 b is the position relationship schematic diagram in leading portion metal interconnecting wires and hole in Fig. 4 a, hole 04 is distributed between leading portion interconnect metallization lines 02, can be distributed a round 04 between interconnect metallization lines 02, also can distribute many rounds 04, designs according to the spacing between the area on actual first barrier layer and interconnect metallization lines; The diameter in hole 04 is 20 ~ 50nm.
Step 03: refer to Fig. 5, the first barrier layer 03 part below wet etching hole 04, forms space 05 in the first barrier layer 03; The diameter in space 05 is greater than the diameter in hole 04;
Concrete, in the present embodiment, the liquid that wet etching adopts is dilute hydrofluoric acid; Material due to the first barrier layer 03 is nitrogen doped silicon carbide, is difficult to be corroded by hydrofluoric acid, can stop that hydrofluoric acid corrodes the porous low-k material below it at non-bore region well.Because wet etching has isotropism, the space being greater than the first barrier layer mesoporous can be formed in the porous low-k material of below corresponding to the first barrier layer mesopore.It should be noted that, the size in the final space formed depends on the degree of depth of dry etching in the size of the first barrier layer mesopore, the time of wet etching and step 02.
Step 04: refer to Fig. 6, the first barrier layer 03 forms second dielectric layer 06, to form the air-gap 05 ' of sealing in first medium layer 01;
Concrete, in the present embodiment, the material of second dielectric layer 06 is porous low-k material; First, PECVD method is adopted to deposit low-k material on the first barrier layer; Then, ultra-violet curing technique is carried out to low-k material, form porous low-k material.Here, the thickness of porous low-k material is 1000 ~ 3000A.Due in PECVD processing procedure, be greater than the deposition rate bottom it in the deposition rate at top, space, space is sealed soon, forms air-gap; But, in the position of corresponding first barrier layer mesopore, porous low-k material surface still has a pit, and the size of its pit depends on the aperture in hole and the step coverage (namely the size of space deposited atop speed and the deposition rate bottom it) of porous low-k material deposition process.
In one embodiment of this invention, porous low-k material surface is had to the situation of pit, adopt chemical mechanical milling tech to carry out planarization to porous low-k material, pit is polished, to avoid causing harmful effect to follow-up photoetching and etching technics.
Step 05: refer to Fig. 7, forms back segment metal interconnecting wires 07 in second dielectric layer 06.
Concrete, in the present embodiment, in second dielectric layer 06, form groove then through photoetching and plasma dry etch process, at trench sidewall surface deposit diffusion barriers, then, then the first barrier layer bottom etching groove, then adopt copper plating to fill metallic copper in the trench; Finally, the metallic copper adopting chemical mechanical milling tech planarization to fill is to second dielectric layer 06 surface.
In the present embodiment, refer to Fig. 8, also comprise after step 05: on second dielectric layer 06 surface and back segment metal interconnecting wires 07 surface deposition second barrier layer 08; The material on the second barrier layer 08 can be nitrogen doped silicon carbide.
In sum, the method of air-gap is formed in dielectric layer between metal interconnecting wires of the present invention, by forming multiple hole in the first barrier layer, wet etching is isotropism, by these pitting corrosions to the first barrier layer portions below it, thus in the first barrier layer, form the space larger than hole, when follow-up second dielectric layer deposits, because dielectric layer is in the Step Coverage ability in space, thus in first medium layer, form the air-gap of sealing, and then reduce the k value of the dielectric layer between metal interconnecting wires.
Although the present invention discloses as above with preferred embodiment; right described embodiment is citing for convenience of explanation only; and be not used to limit the present invention; those skilled in the art can do some changes and retouching without departing from the spirit and scope of the present invention, and the protection range that the present invention advocates should be as the criterion with described in claims.
Claims (10)
1. form a method for air-gap in the dielectric layer between metal interconnecting wires, it is characterized in that, comprise the following steps:
Step 01: form first medium layer in semiconductor device substrates, forms leading portion metal interconnecting wires and surperficial and described first medium layer surface deposition first barrier layer at described leading portion metal interconnecting wires in described first medium layer;
Step 02: through photoetching and etching technics, forms multiple hole in described first barrier layer;
Step 03: described first barrier layer portions below hole described in wet etching, forms space in described first barrier layer; The diameter in described space is greater than the diameter in described hole;
Step 04: form second dielectric layer on described first barrier layer, to form the air-gap of sealing in first medium layer.
2. form the method for air-gap in the dielectric layer between metal interconnecting wires according to claim 1, it is characterized in that, also comprise step 05 after described step 04: in described second dielectric layer, form back segment metal interconnecting wires.
3. form the method for air-gap in the dielectric layer between metal interconnecting wires according to claim 1, it is characterized in that, the thickness on described first barrier layer is 150 ~ 500A.
4. form the method for air-gap in the dielectric layer between metal interconnecting wires according to claim 1, it is characterized in that, the material of described first medium layer or described second dielectric layer is porous low-k material.
5. form the method for air-gap in the dielectric layer between metal interconnecting wires according to claim 4, it is characterized in that, also comprised before described formation leading portion metal interconnecting wires in described step 01: ultra-violet curing technique is carried out to described first medium layer; Or also comprise in described step 04: ultra-violet curing technique is carried out to described second dielectric layer.
6. form the method for air-gap in the dielectric layer between metal interconnecting wires according to claim 1, it is characterized in that, the diameter in described hole is 20 ~ 50nm.
7. form the method for air-gap in the dielectric layer between metal interconnecting wires according to claim 1, it is characterized in that, in described step 02, described etching technics is plasma dry etch process.
8. form the method for air-gap in the dielectric layer between metal interconnecting wires according to claim 1, it is characterized in that, in described step 03, the liquid that described wet etching adopts is dilute hydrofluoric acid.
9. form the method for air-gap in the dielectric layer between metal interconnecting wires according to claim 1, it is characterized in that, described step 04 also comprises: carry out planarization to described second dielectric layer top.
10. form the method for air-gap in the dielectric layer between metal interconnecting wires according to claim 1, it is characterized in that, also comprise after described step 05: on described second dielectric layer surface and described back segment metal interconnecting wires surface deposition second barrier layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510173994.1A CN104795359A (en) | 2015-04-13 | 2015-04-13 | Method of forming air gaps in dielectric layers among metal interconnections |
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| CN201510173994.1A CN104795359A (en) | 2015-04-13 | 2015-04-13 | Method of forming air gaps in dielectric layers among metal interconnections |
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Cited By (1)
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| CN106019813A (en) * | 2016-05-30 | 2016-10-12 | 上海华力微电子有限公司 | Photoetching mask, photoetching method of interconnection line graphics and preparation method of interconnection line |
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Application publication date: 20150722 |