CN104779276B - IGBT with super junction structure and preparation method thereof - Google Patents
IGBT with super junction structure and preparation method thereof Download PDFInfo
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- CN104779276B CN104779276B CN201410116773.6A CN201410116773A CN104779276B CN 104779276 B CN104779276 B CN 104779276B CN 201410116773 A CN201410116773 A CN 201410116773A CN 104779276 B CN104779276 B CN 104779276B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 14
- 150000002500 ions Chemical class 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 13
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 238000001020 plasma etching Methods 0.000 description 8
- 238000009826 distribution Methods 0.000 description 7
- 230000004907 flux Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
Abstract
The invention discloses an IGBT with a super-junction structure, which comprises a collector electrode, a drift region, a P-type base region and an N-type emitter region, wherein gate grooves are formed in the P-type base region and the N-type emitter region, gate electrodes are arranged in the gate grooves, a P-type region is arranged between the bottom of the gate grooves and the collector electrode, the P-type regions are respectively connected with the bottom of the gate grooves and the collector electrode, and the adjacent P-type regions are filled with insulating media. The invention also discloses a preparation method of the IGBT with the super junction structure. The IGBT with the super junction structure can generate a transverse electric field so as to improve the breakdown voltage of a device and reduce the saturation voltage drop; the preparation method of the IGBT with the super junction structure provided by the invention has the advantage of short processing time.
Description
Technical Field
The invention relates to an IGBT, in particular to an IGBT with a super junction structure and a preparation method thereof.
Background
The IGBT is a short term for an insulated Gate Bipolar Transistor (insulated Gate Bipolar Transistor), and is a novel composite power electronic device that was first born in the eighties and developed rapidly in the nineties. The semiconductor power devices that were mainstream internationally after 1980 were developed from thyristors to more advanced Insulated Gate Bipolar Transistors (IGBTs).
Generally, a higher breakdown voltage increases the saturation voltage drop vce (sat), which reduces the performance of the inverter, and a novel Field Stop Trench IGBT is generated to compromise the higher breakdown voltage and the lower saturation voltage drop, and fig. 2 is a schematic diagram of a common IGBT.
The field-resistance trench type IGBT is the most popular IGBT structure at present and can well compromise breakdown voltage and saturation voltage drop. However, the structure still has a serious defect that the electric field is distributed in one dimension in the silicon, namely the electric field is distributed along the Y direction, and the electric field distribution still has larger saturation voltage drop.
Disclosure of Invention
In view of the above defects of the existing IGBT, the present invention provides an IGBT with a super junction structure and a method for manufacturing the same, which can generate a lateral electric field to improve the breakdown voltage of the device and reduce the saturation voltage drop, and the time for manufacturing and processing is short.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
an IGBT with a super-junction structure comprises a collector electrode, a drift region, a P-type base region and an N-type emitter region, wherein a gate trench is arranged in the P-type base region and the N-type emitter region, a gate electrode is arranged in the gate trench, a P-type region is arranged between the bottom of the gate trench and the collector electrode, the P-type regions are respectively connected with the bottom of the gate trench and the collector electrode, and the adjacent P-type regions are filled with an insulating medium.
According to one aspect of the invention, a gate oxide layer is disposed between the gate electrode and the gate trench.
In accordance with an aspect of the invention, an insulating layer is provided on top of the gate electrode.
In accordance with one aspect of the invention, the insulating dielectric is silicon dioxide.
In accordance with one aspect of the invention, the insulating dielectric is polysilicon.
According to an aspect of the invention, a P + collector region layer and a buffer layer are further disposed between the collector and the drift region, the collector being adjacent to the P + collector region layer, and the buffer layer being adjacent to the drift region.
A preparation method of an IGBT with a super junction structure comprises the following steps:
extending an N buffer layer and an N-drift region layer on the P + collector region layer substrate;
then, manufacturing a P-type base layer and an N + emitter layer;
forming a groove from the N + emitter layer to the P + collector region;
injecting P-type ions into the side wall of the groove to form a P-type area;
filling the groove with an insulating medium;
continuously etching a larger gate trench on the filled trench;
and adding a gate oxide layer and a gate electrode in the gate trench.
According to one aspect of the present invention, the step of implanting P-type ions into the trench sidewall to form a P-type region uses a large angle ion implantation method T.
In accordance with one aspect of the invention, the insulating dielectric used to fill the trenches with the insulating dielectric is silicon dioxide.
According to one aspect of the present invention, the adding of the gate oxide layer and the gate electrode in the gate trench is specifically: gate oxide and in-situ doped poly deposition.
The implementation of the invention has the advantages that: the IGBT with the super junction structure keeps the original structure, and adopts the mode that the P-type region and the insulating medium filling region are additionally arranged below the gate trench, the P-type region is respectively connected with the gate trench and the P-type collector, so that transverse electric field distribution is formed between the P-type regions below two adjacent gate trenches, namely the X-axis direction, according to the super junction theory, the electric flux generated by the positive charge of almost each ionization donor is absorbed by the negative charge of the ionization acceptor nearby, namely the electric lines of the electric field are transverse, namely the electric field of the drift region is in two-dimensional distribution. The mutual compensation relationship among the transverse charges can be roughly considered as intrinsic for the longitudinal direction, so that the doping concentration of each region is very high, the conductivity of a drift region is very high when the IGBT is conducted, the saturation voltage drop of the IGBT is effectively reduced, and the breakdown voltage is improved; according to the method for preparing the IGBT with the super junction structure, each zone layer is formed in a mode of step-by-step epitaxy and ion implantation, and the ion implantation is adopted, so that the method has the advantage of short processing time compared with the prior art.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an IGBT with a super junction structure according to the present invention;
fig. 2 is a schematic structural diagram of an IGBT according to the background art of the present invention;
fig. 3, fig. 4, fig. 5, fig. 6, fig. 7, fig. 8 and fig. 9 are schematic method steps of a method for manufacturing an IGBT with a super junction structure according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, an IGBT with a super junction structure includes a collector 1, a drift region 2, a P-type base region 3, and an N-type emitter region 4, wherein a gate trench 5 is provided in the P-type base region 3 and the N-type emitter region 4, a gate electrode 6 is provided in the gate trench 5, a P-type region 7 is provided between the bottom of the gate trench 5 and the collector 1, the P-type regions 7 are respectively connected to the bottom of the gate trench 5 and the collector 1, and the adjacent P-type regions 7 are filled with an insulating medium 8; the scheme reserves the original structure, and adopts the mode that a P-type region 7 and an insulating medium 8 filling region are additionally arranged below a gate trench 5, the P-type region 7 is respectively connected with the gate trench 5 and a P-type collector 1, so that transverse electric field distribution is formed between the P-type regions 7 below two adjacent gate trenches 5, namely the X-axis direction, according to the super junction theory, the electric flux generated by the positive charge of almost each ionization donor is absorbed by the negative charge of the nearby ionization acceptor, namely the electric lines of the electric flux are transverse, namely the electric field of a drift region 2 is in two-dimensional distribution. The mutual compensation relationship between the transverse charges can be roughly considered as intrinsic for the longitudinal direction, so that the doping concentration of each region is very high, the conductivity of the drift region 2 is very high when the IGBT is conducted, the saturation voltage drop of the IGBT is effectively reduced, and the breakdown voltage is improved.
A gate oxide layer 51 is arranged between the gate electrode 6 and the gate trench 5; an insulating layer 61 is arranged on the top of the gate electrode; the insulating medium 8 can be silicon dioxide or polysilicon; a P + collector region layer 11 and a buffer layer 21 are further arranged between the collector 1 and the drift region 2, the collector 1 is adjacent to the P + collector region layer 11, and the buffer layer 21 is adjacent to the drift region 2;
a preparation method of an IGBT with a super junction structure comprises the following steps:
the method comprises the following steps: extending an N buffer layer and an N-drift region layer on the P + collector region layer substrate;
as shown in fig. 3, an N + -type buffer layer 200 and an N-type drift layer 300 are epitaxially grown in this order on the main surface of the p + -type collector region layer substrate 100.
Step two: manufacturing a P-type base layer and an N + emitter layer;
as shown in fig. 4, the P-type base layer 400 and the N + emitter layer 500 are continuously formed to extend on the N-type drift layer 300.
Step three: forming a groove from the N + emitter layer to the P + collector region;
as shown in fig. 5, the trench 600 is formed by forming a mask such as a resist on the upper surface of the N + -type emitter layer 500 in the region where the trench is not formed, and then performing partial etching in the thickness direction thereof. The etching may be achieved by Reactive Ion Etching (RIE), for example, and Inductively Coupled Plasma (ICP) RIE is particularly preferably used. For example, the etching may be carried out by ICP-RIE using SF6 or a mixed gas of SF6 and O2 as a reaction gas.
Step four: injecting P-type ions into the side wall of the groove to form a P-type area;
as shown in fig. 6, P-type ions are implanted into the sidewall of the trench 600 to form a P-type region 601, and a large angle ion implantation is used.
Step five: filling the groove with an insulating medium;
as shown in fig. 7, the trench 600 is filled with an insulating dielectric 602, for example, the trench 600 is filled with silicon dioxide; the trench 600 is filled, for example, with polysilicon.
Step six: continuously etching a larger gate trench on the filled trench;
as shown in fig. 8, a larger gate trench 700 is etched on the trench 600 after it has been filled with an insulating dielectric such as silicon dioxide or polysilicon. The etching may be achieved by Reactive Ion Etching (RIE), for example, and Inductively Coupled Plasma (ICP) RIE is particularly preferably used. For example, the etching may be carried out by ICP-RIE using SF6 or a mixed gas of SF6 and O2 as a reaction gas
Step seven: adding a gate oxide layer and a gate electrode in the gate trench;
as shown in fig. 9, a gate oxide layer 701, that is, an insulating film is formed in the etched gate trench 700, and then a gate electrode 702 is formed by deposition.
Injecting P-type ions into the side wall of the groove to form a P-type area by adopting a large-angle ion injection mode; the insulating medium adopted by filling the groove with the insulating medium is silicon dioxide; the method for adding the gate oxide layer and the gate electrode in the gate trench specifically comprises the following steps: gate oxide and in-situ doped poly deposition
The implementation of the invention has the advantages that: the IGBT with the super junction structure keeps the original structure, and adopts the mode that the P-type region and the insulating medium filling region are additionally arranged below the gate trench, the P-type region is respectively connected with the gate trench and the P-type collector, so that transverse electric field distribution is formed between the P-type regions below two adjacent gate trenches, namely the X-axis direction, according to the super junction theory, the electric flux generated by the positive charge of almost each ionization donor is absorbed by the negative charge of the ionization acceptor nearby, namely the electric lines of the electric field are transverse, namely the electric field of the drift region is in two-dimensional distribution. The mutual compensation relationship among the transverse charges can be roughly considered as intrinsic for the longitudinal direction, so that the doping concentration of each region is very high, the conductivity of a drift region is very high when the IGBT is conducted, the saturation voltage drop of the IGBT is effectively reduced, and the breakdown voltage is improved; according to the method for preparing the IGBT with the super junction structure, each zone layer is formed in a mode of step-by-step epitaxy and ion implantation, and the ion implantation is adopted, so that the method has the advantage of short processing time compared with the prior art.
The above description is only an embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention disclosed herein are intended to be covered by the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. An IGBT with a super-junction structure is characterized by comprising a collector electrode, a P + type collector region layer, a drift region, a P type base region and an N type emitter region, wherein a gate trench is arranged in the P type base region and the N type emitter region, a gate electrode is arranged in the gate trench, a P type region is arranged between the bottom of the gate trench and the P + type collector region layer, the P type region is respectively connected with the bottom of the gate trench and the P + type collector region layer, and the adjacent P type regions are filled with an insulating medium;
the preparation method of the IGBT with the super junction structure comprises the following steps:
the method comprises the following steps: epitaxially growing an N + -type buffer layer (200) and an N-type drift layer (300) on the main surface of the p + -type collector region layer substrate (100) in this order;
step two: continuing to extend and manufacture the P-type base layer (400) and the N + emitter layer (500) on the N-type drift layer (300);
step three: forming a groove from the N + emitter layer to the P + type collector region layer;
step four: injecting P-type ions into the side wall of the groove by adopting a large ion angle injection mode to form a P-type area;
step five: filling the groove with an insulating medium;
step six: continuously etching a larger gate trench on the filled trench;
step seven: and adding a gate oxide layer and a gate electrode in the gate trench.
2. The IGBT with the super junction structure according to claim 1, wherein a gate oxide layer is arranged between the gate electrode and the gate trench.
3. The IGBT having a super junction structure according to claim 2, wherein the gate electrode is provided with an insulating layer on top.
4. The IGBT with a superjunction structure according to claim 1, wherein the insulating dielectric is silicon dioxide.
5. The IGBT having a super junction structure according to claim 1, wherein the insulating medium is polysilicon.
6. The IGBT having a super junction structure according to any one of claims 1 to 5, wherein a buffer layer is further provided between the P + -type collector region layer and the drift region, the collector is adjacent to the P + -type collector region layer, and the buffer layer is adjacent to the drift region.
7. A preparation method of an IGBT with a super junction structure is characterized by comprising the following steps:
extending an N buffer layer and an N-drift region layer on the P + type collector region layer substrate;
manufacturing a P-type base layer and an N + emitter layer;
forming a groove from the N + emitter layer to the P + type collector region layer;
injecting P-type ions into the side wall of the groove to form a P-type area;
filling the groove with an insulating medium;
continuously etching a larger gate trench on the filled trench;
adding a gate oxide layer and a gate electrode in the gate trench;
the P-type region is arranged between the bottom of the gate trench and the P + type collector region layer and is respectively connected with the bottom of the gate trench and the P + type collector region layer.
8. The method for manufacturing the IGBT with the superjunction structure according to claim 7, wherein the step of implanting P-type ions into the trench sidewall to form the P-type region is performed by high angle ion implantation.
9. The method for manufacturing the IGBT with the superjunction structure according to claim 7, wherein the insulating medium used for filling the trench with the insulating medium is silicon dioxide.
10. The method for manufacturing the IGBT with the super junction structure according to any one of claims 7 to 9, wherein the adding of the gate oxide layer and the gate electrode in the gate trench is specifically: gate oxide and in-situ doped poly deposition.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101019235A (en) * | 2004-09-03 | 2007-08-15 | 皇家飞利浦电子股份有限公司 | Vertical semiconductor devices and methods of manufacturing such devices |
| CN102142378A (en) * | 2011-03-04 | 2011-08-03 | 电子科技大学 | Method for manufacturing super-junction semiconductor device with extended groove |
| CN102569354A (en) * | 2010-12-16 | 2012-07-11 | 三菱电机株式会社 | Insulated gate bipolar transistor and manufacturing method thereof |
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| TWI462295B (en) * | 2011-11-15 | 2014-11-21 | Anpec Electronics Corp | Trench type power transistor device and fabricating method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101019235A (en) * | 2004-09-03 | 2007-08-15 | 皇家飞利浦电子股份有限公司 | Vertical semiconductor devices and methods of manufacturing such devices |
| CN102569354A (en) * | 2010-12-16 | 2012-07-11 | 三菱电机株式会社 | Insulated gate bipolar transistor and manufacturing method thereof |
| CN102142378A (en) * | 2011-03-04 | 2011-08-03 | 电子科技大学 | Method for manufacturing super-junction semiconductor device with extended groove |
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Address after: 201405 Room 101, 88 Tong Fu Road, Fengxian District, Shanghai. Patentee after: Shanghai Tiniu Technology Co.,Ltd. Address before: No. 88 Tangfu Road, Fengxian District, Shanghai, 201405 Patentee before: SHANGHAI STN ELECTROMECHANICAL EQUIPMENT Co.,Ltd. |
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