CN104779204A - Wafer processing method - Google Patents

Wafer processing method Download PDF

Info

Publication number
CN104779204A
CN104779204A CN201510013400.0A CN201510013400A CN104779204A CN 104779204 A CN104779204 A CN 104779204A CN 201510013400 A CN201510013400 A CN 201510013400A CN 104779204 A CN104779204 A CN 104779204A
Authority
CN
China
Prior art keywords
wafer
along
preset lines
grinding
segmentation preset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201510013400.0A
Other languages
Chinese (zh)
Other versions
CN104779204B (en
Inventor
广泽俊一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Disco Corp
Original Assignee
Disco Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Disco Corp filed Critical Disco Corp
Publication of CN104779204A publication Critical patent/CN104779204A/en
Application granted granted Critical
Publication of CN104779204B publication Critical patent/CN104779204B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B28WORKING CEMENT, CLAY, OR STONE
    • B28DWORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B28WORKING CEMENT, CLAY, OR STONE
    • B28DWORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • B28D5/0005Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by breaking, e.g. dicing
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B28WORKING CEMENT, CLAY, OR STONE
    • B28DWORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • B28D5/0005Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by breaking, e.g. dicing
    • B28D5/0011Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by breaking, e.g. dicing with preliminary treatment, e.g. weakening by scoring
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/268Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836Wafer tapes, e.g. grinding or dicing support tapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Optics & Photonics (AREA)
  • Electromagnetism (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Dicing (AREA)
  • Laser Beam Processing (AREA)

Abstract

The invention provides a wafer processing method. The bending strength of a chip is not reduced, and a thick chip can be formed. A wafer is provided with a plurality of crossed predetermined cutting lines. The wafer processing method is characterized by comprising a groove forming step, a protective belt pasting step, a laser processing step and a grinding step. In the groove forming step, a plurality of grooves at certain depths are formed in the front side of the wafer along the predetermined cutting lines, and the wafer does not reach the final thickness. In the protective belt pasting step, a protective belt is pasted on the front side of the wafer. In the laser processing step, the focus of a laser beam which has a certain length and can penetrate the wafer is positioned on the position, in the wafer, being closer to the back side relative to the final thickness, the laser beam irradiates the back side of the wafer along the predetermined cutting lines, a deteriorative layer along the predetermined cutting line is formed in the wafer, and a crack layer which extends from the deteriorative layer to grooves and along the predetermined cutting lines. In the grinding step, a grinding member is employed to grind the back side of the wafer, and the wafer becomes thinner and reaches the final thickness, furthermore, the deteriorative layer is removed, and the wafer is cut along the predetermined cutting lines to form chips.

Description

The processing method of wafer
Technical field
The present invention relates to the processing method of the wafers such as semiconductor wafer.
Background technology
In the manufacture process of semiconductor device, on the front of the roughly semiconductor wafer of circular plate shape, by being formed as forming the devices such as IC (IntegratedCircuit: integrated circuit), LSI (large scale integration: large scale integrated circuit) respectively in multiple regions that cancellate segmentation preset lines (spacing track) marks off, and each region of this device is formed along the segmentation of segmentation preset lines, produce device chip thus.
As segmenting device semiconductor wafer being divided into device chip one by one, generally have employed the topping machanism being referred to as cutter sweep, this topping machanism utilizes the cutting tool with very thin cutting edge to cut along segmentation preset lines semiconductor wafer, semiconductor wafer is divided into device chip one by one.The various electronic equipment such as mobile phone, computer is widely used in after the device chip be partitioned into like this is packed.
, when to cut such as thickness when using cutting tool being more than 300 μm equal thickness thicker wafer, existing and often occurring that the back side collapses broken such problem.Therefore, broken in order to suppress the back side to collapse, can consider to adopt and such as disclosed in Japanese Laid-Open Patent Publication 64-38209 publication, first mark processing method disclosed in reduction (DBG:Dicing Before Grinding) and WO2003-077295 publication (SDBG:Stealth Dicing Before Grinding).
First marking reduction is following such technology: from the slot segmentation of the degree of depth (degree of depth suitable with the completion thickness of device chip) that the front of semiconductor wafer specifies along the formation of segmentation preset lines, and grinding is carried out to the back side of the semiconductor wafer being formed with slot segmentation in front and slot segmentation is exposed overleaf, be divided into device chip one by one thus, this first marks reduction can be machined to less than 100 μm by the thickness of device chip.
On the other hand, SDBG method is technology laser processing and method for grinding combined, and be following such technology: first, to wafer illumination, wafer is had to the laser beam of radioparent wavelength, metamorphic layer is formed in the position (position more than degree of depth suitable with the completion thickness of device chip with the front distance of wafer) of the degree of depth of regulation along segmentation preset lines, and form the crackle layer that the face side from metamorphic layer to wafer extends, then, grinding is carried out to the back side of wafer, making wafer thinning is completion thickness, and utilize grinding force with crackle layer for segmentation starting point by wafer separation for device chip one by one.
Patent documentation 1: Japanese Laid-Open Patent Publication 64-38209 publication
Patent documentation 2:WO2003-077295 publication
; first mark in reduction at citing document 1; there is following problems: if form the hemisect groove of the degree of depth over half of wafer thickness; then after groove is formed; need to paste boundary belt in the front of wafer; this boundary belt is used for protecting the device being formed at front when back side grinding afterwards, but during operation when pasting boundary belt, wafer can be damaged.
In addition, also following problems is there is: because the crackle layer that can extend from a metamorphic layer is about 150 μm in the SDBG method of citing document 2, therefore, if the chip sides in order to avoid bending strength deterioration not after grinding remains metamorphic layer, be then difficult to the chip of the thickness of formation more than 150 μm.
Summary of the invention
The present invention completes in view of the above problems, its object is to provide a kind of and does not make bending strength worsen and can form the processing method of the wafer of the chip of thicker thickness.
According to the present invention, a kind of processing method of wafer is provided, wafer is set with many segmentation preset lines of intersection, the feature of the processing method of wafer is, the processing method of wafer comprises: groove forming step, forms multiple grooves of the degree of depth not reaching completion thickness from the front of wafer along this segmentation preset lines; Boundary belt gluing steps, after implementing this groove forming step, pastes boundary belt in the front of wafer; Keep step, after implementing this boundary belt gluing steps, utilize chuck table to keep wafer across this boundary belt; Laser machining process, after implementing this maintenance step, the focal point of laser beam wafer to radioparent wavelength is positioned at the position than this completion thickness backrest surface side of inner wafer, this laser beam is irradiated along this segmentation preset lines in the back side towards wafer, form the metamorphic layer along this segmentation preset lines at inner wafer, and form the crackle layer along this segmentation preset lines extended from this metamorphic layer towards this groove; With grinding step, after implementing this laser machining process, utilize grinding component to carry out grinding to the back side of wafer and be thinned to this completion thickness to make this wafer, and removing this metamorphic layer, is chip along this segmentation preset lines by wafer separation.
In processing method of the present invention, after forming groove in the front of wafer, paste boundary belt, therefore, even if form metamorphic layer and crackle layer at inner wafer, protection also can be utilized to bring maintaining rigidness, can not operability be damaged.
In addition, owing to removing metamorphic layer by grinding, and along segmentation preset lines segmentation wafer, therefore, chip can not remain metamorphic layer, and bending strength can not be made to worsen.
Accompanying drawing explanation
Fig. 1 is the face side stereogram of semiconductor wafer.
Fig. 2 is the stereogram that groove forming step is shown.
Fig. 3 is the cutaway view that groove forming step is shown.
Fig. 4 is the cutaway view that boundary belt gluing steps is shown.
Fig. 5 illustrates the partial cut away side views keeping step.
Fig. 6 is the partial cut away side views that laser machining process is shown.
Fig. 7 is the partial cut away side views that grinding step is shown.
Fig. 8 is the cutaway view of the wafer after grinding step.
Label declaration
10: cutting unit;
11: semiconductor wafer;
13: segmentation preset lines;
15: device;
16: cutting tool;
19: groove;
20: concentrator (laser head);
21: boundary belt;
23: metamorphic layer;
24: grinding unit (grinding component);
25: crackle layer;
27: device chip.
Embodiment
Below, with reference to accompanying drawing, embodiments of the present invention are described in detail.With reference to Fig. 1, show the face side stereogram of semiconductor wafer 11.On the front 11a of semiconductor wafer (following, to exist only referred to as the situation of wafer) 11, in each region marked off by many segmentations preset lines (spacing track) 13, be formed with the devices such as IC, LSI 15.The recess 17 of the mark as the crystal orientation representing wafer is formed in the periphery of wafer 11.
In the processing method of wafer of the present invention, first implement groove forming step, in this groove forming step, form multiple grooves of the degree of depth not reaching completion thickness from the front 11a of wafer 11 along segmentation preset lines 13.Fig. 2 is the stereogram that groove forming step is shown, Fig. 3 is its cutaway view.In figs. 2 and 3, the chuck table that suction keeps wafer 11 is eliminated.
In fig. 2, the cutting unit (cutting member) 10 of topping machanism comprises: main shaft 14, and it is accommodated in main shaft housing 12 in the mode that can rotate; With cutting tool 16, it is installed on the terminal part of main shaft 14.
In groove forming step, the degree of depth (not reaching the degree of depth of the completion thickness of wafer) that the segmentation preset lines 13 making the cutting tool 16 along arrow A direction High Rotation Speed cut wafer 11 specifies, and, while make not shown chuck table carry out processing feeding along arrow X1 direction, form the groove 19 of the degree of depth not reaching completion thickness from the front 11a of wafer 11 along segmentation preset lines 13.
The each spacing making cutting unit 10 correspond to segmentation preset lines 13 carries out index feed, and forms groove 19 along all segmentation preset lines 13 extended on the 1st direction.Then, make suction remain the not shown chuck table 90-degree rotation of wafer 11, form identical groove 19 along the segmentation preset lines 13 extended on the 2nd direction vertical with the 1st direction.
In this groove forming step, formation Billy uses the groove 19 first marking the depth as shallow of the groove that reduction is formed in the past.Owing to forming more shallow groove 19 like this, therefore, it is possible to use containing the cutting tool 16 of small particle diameter abrasive particle, thus can collapse broken in the front of restrain tank when being formed.
After implementing groove forming step, implement the boundary belt gluing steps pasting boundary belt 21 at the front 11a of wafer 11.Fig. 4 is the cutaway view after the enforcement of boundary belt gluing steps is shown.
After implementing boundary belt gluing steps, implement to keep step, in this maintenance step, as shown in Figure 5, utilize the chuck table 18 of laser processing device to keep wafer 11 across boundary belt 21.When implementing this maintenance step, the back side 11b of wafer 11 exposes.
After implementing maintenance step, implement laser machining process, in this laser machining process, as shown in Figure 6, by concentrator 20, the focal point P of laser beam LB wafer 11 to radioparent wavelength is positioned at the position of the ratio completion thickness t backrest surface 11b side of wafer 11 inside, towards the back side 11b of wafer 11 along segmentation preset lines 13 illuminating laser beam LB, form the metamorphic layer 23 along segmentation preset lines 13, further, the crackle layer 25 along segmentation preset lines 13 extended from metamorphic layer 23 towards groove 19 is formed.Completion thickness t is such as 300 μm.
The each spacing making chuck table 18 correspond to segmentation preset lines 13 carries out index feed, and implement this laser machining process along all segmentation preset lines 13 extended on the 1st direction, then, make chuck table 18 90-degree rotation, next also implement this laser machining process in the same manner along all segmentation preset lines 13 extended on the 2nd direction.
The such as setting as following of processing conditions in this laser machining process.
Light source: LD encourages Q switching Nd:YVO4 pulse laser
Wavelength: 1064nm
Pulse exports: 0.2W
Repetition rate: 80kHz
Optically focused spot diameter: φ 1 μm
Processing feed speed: 100mm/ second
After implementing laser machining process, implement grinding step, in this grinding step, the back side 11b of grinding component to wafer 11 is utilized to carry out grinding to make it thinning to completion thickness t, meanwhile, remove metamorphic layer 23, along segmentation preset lines 13, wafer 11 is divided into device chip 27.With reference to Fig. 7, this grinding step is described.
As shown in Figure 7, in grinding step, utilize the chuck table 22 of grinding attachment to carry out suction across the 11a side, front of boundary belt 21 pairs of wafers 11 and keep, the 11b side, the back side of wafer 11 is exposed.
The grinding unit (grinding component) 24 of grinding attachment comprises: main shaft 26, and it is driven by a motor and rotates; Wheel seat 28, it is fixed on the end of main shaft 26; With emery wheel 30, it is fixed on wheel seat 28 by multiple screw in the mode that can load and unload.Emery wheel 30 is made up of following part: the wheel pedestal 32 of ring-type; With multiple grinding tool 34, they are fixedly installed in the lower end periphery portion of wheel pedestal 32 in the form of a ring.
In grinding step, while make chuck table 22 rotate along arrow a direction with such as 300rpm, while make emery wheel 30 rotate along the direction identical with chuck table 22 and arrow b direction with such as 6000rpm, further, make not shown grinding unit feed mechanism action thus grinding tool 34 is contacted with the back side 11b of wafer 11.
Then, make emery wheel 30 with the grinding and feeding speed of the regulation amount that specifies of grinding and feeding implement the grinding of wafer 11 downwards.If proceed grinding to make wafer 11 thinning towards completion thickness t, then metamorphic layer 23 is removed, and grinding force acts on the crackle layer 25 along segmentation preset lines 13, wafer 11 is divided into as shown in Figure 8 device chip 27 one by one.
Processing method according to the present embodiment, because the rear side of device chip 27 realizes segmentation based on crackle layer 25, therefore can suppress to collapse broken generation.In addition, because the 11a side, front at wafer 11 is formed with groove 19, therefore, even if chip adjacent in grinding process contacts with each other, also can not there is front and collapse broken, thus can not damage device 15.
Because the 11a side, front at wafer 11 is formed with groove 19, therefore, wafer 11 being divided into device chip 27 and the wafer 11 being split into chip being transferred to after in cutting belt, clean, fully can clean device 15 side of chip 27 thus.
In addition, the wafer that the processing method of wafer of the present invention is formed with TEG (Test Element Group: testing element group) etc. for the segmentation preset lines 13 along wafer 11 is effective.

Claims (1)

1. a processing method for wafer, wafer is set with many segmentation preset lines of intersection,
The feature of the processing method of wafer is,
The processing method of wafer comprises:
Groove forming step, forms multiple grooves of the degree of depth not reaching completion thickness from the front of wafer along this segmentation preset lines;
Boundary belt gluing steps, after implementing this groove forming step, pastes boundary belt in the front of wafer;
Keep step, after implementing this boundary belt gluing steps, utilize chuck table to keep wafer across this boundary belt;
Laser machining process, after implementing this maintenance step, the focal point of laser beam wafer to radioparent wavelength is positioned at the position than this completion thickness backrest surface side of inner wafer, this laser beam is irradiated along this segmentation preset lines in the back side towards wafer, form the metamorphic layer along this segmentation preset lines at inner wafer, and form the crackle layer along this segmentation preset lines extended from this metamorphic layer towards this groove; With
Grinding step, after implementing this laser machining process, utilizes grinding component to carry out grinding to the back side of wafer and is thinned to this completion thickness to make this wafer, and removing this metamorphic layer, is chip along this segmentation preset lines by wafer separation.
CN201510013400.0A 2014-01-15 2015-01-12 The processing method of chip Active CN104779204B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2014-004796 2014-01-15
JP2014004796A JP6230422B2 (en) 2014-01-15 2014-01-15 Wafer processing method

Publications (2)

Publication Number Publication Date
CN104779204A true CN104779204A (en) 2015-07-15
CN104779204B CN104779204B (en) 2019-07-02

Family

ID=53620603

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510013400.0A Active CN104779204B (en) 2014-01-15 2015-01-12 The processing method of chip

Country Status (4)

Country Link
JP (1) JP6230422B2 (en)
KR (1) KR102163441B1 (en)
CN (1) CN104779204B (en)
TW (1) TWI625810B (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106409762A (en) * 2015-08-03 2017-02-15 株式会社迪思科 Workpiece processing method
CN107039260A (en) * 2015-11-05 2017-08-11 株式会社迪思科 The processing method of chip
CN107919274A (en) * 2016-10-05 2018-04-17 株式会社迪思科 processing method
CN108630739A (en) * 2017-03-22 2018-10-09 东芝存储器株式会社 Semiconductor device and its manufacturing method
CN109119336A (en) * 2017-06-22 2019-01-01 株式会社迪思科 The processing method of machined object
CN109391241A (en) * 2017-08-02 2019-02-26 株式会社迪思科 The manufacturing method of elastic wave device substrate
CN109590288A (en) * 2018-11-28 2019-04-09 四川大学 The method of laser cleaning light transmission medium transmission plane impurity
CN109743877A (en) * 2016-10-03 2019-05-10 琳得科株式会社 The manufacturing method of semiconductor machining adhesive tape and semiconductor device
CN110783250A (en) * 2018-07-31 2020-02-11 株式会社迪思科 Method for processing wafer
CN110945630A (en) * 2017-07-28 2020-03-31 浜松光子学株式会社 Method for manufacturing laminated element
CN112400217A (en) * 2018-07-19 2021-02-23 东京毅力科创株式会社 Substrate processing system and substrate processing method
CN114160958A (en) * 2021-12-07 2022-03-11 华东光电集成器件研究所 Method for combining laser invisible cutting and mechanical cutting of wafer

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6558541B2 (en) * 2015-12-09 2019-08-14 株式会社ディスコ Wafer processing method
KR102399356B1 (en) * 2017-03-10 2022-05-19 삼성전자주식회사 Substrate, method of sawing substrate, and semiconductor device
JP2019024038A (en) * 2017-07-24 2019-02-14 株式会社ディスコ Wafer processing method
JP7027234B2 (en) * 2018-04-16 2022-03-01 株式会社ディスコ Wafer processing method
US12020936B2 (en) * 2018-12-21 2024-06-25 Tokyo Electron Limited Substrate processing apparatus and substrate processing method
TWI722642B (en) * 2019-11-07 2021-03-21 長豐光學科技股份有限公司 Laser cutting method for thin wire
JP7433725B2 (en) 2020-06-26 2024-02-20 株式会社ディスコ Chip manufacturing method
CN111987146A (en) * 2020-09-21 2020-11-24 上海擎茂微电子科技有限公司 Wafer for preparing semiconductor device and back thinning method of wafer

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101057317A (en) * 2004-11-12 2007-10-17 浜松光子学株式会社 Laser beam machining method and semiconductor chip
CN102097310A (en) * 2009-11-18 2011-06-15 株式会社迪思科 Processing method for optical device wafer
CN103489772A (en) * 2012-06-07 2014-01-01 株式会社迪思科 Method for machining wafer

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6438209A (en) 1987-08-04 1989-02-08 Nec Corp Preparation of semiconductor device
ATE518242T1 (en) * 2002-03-12 2011-08-15 Hamamatsu Photonics Kk METHOD FOR SEPARATING SUBSTRATES
JP4440582B2 (en) * 2003-09-10 2010-03-24 浜松ホトニクス株式会社 Semiconductor substrate cutting method
JP2007134454A (en) * 2005-11-09 2007-05-31 Toshiba Corp Method of manufacturing semiconductor device
US20070155131A1 (en) * 2005-12-21 2007-07-05 Intel Corporation Method of singulating a microelectronic wafer
JP5789802B2 (en) * 2011-03-22 2015-10-07 株式会社ソシオネクスト Manufacturing method of semiconductor chip
JP5803049B2 (en) * 2011-06-13 2015-11-04 株式会社東京精密 Semiconductor substrate cutting method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101057317A (en) * 2004-11-12 2007-10-17 浜松光子学株式会社 Laser beam machining method and semiconductor chip
CN102097310A (en) * 2009-11-18 2011-06-15 株式会社迪思科 Processing method for optical device wafer
CN103489772A (en) * 2012-06-07 2014-01-01 株式会社迪思科 Method for machining wafer

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106409762A (en) * 2015-08-03 2017-02-15 株式会社迪思科 Workpiece processing method
CN107039260B (en) * 2015-11-05 2021-10-15 株式会社迪思科 Method for processing wafer
CN107039260A (en) * 2015-11-05 2017-08-11 株式会社迪思科 The processing method of chip
CN109743877B (en) * 2016-10-03 2022-06-10 琳得科株式会社 Adhesive tape for semiconductor processing and method for manufacturing semiconductor device
CN109743877A (en) * 2016-10-03 2019-05-10 琳得科株式会社 The manufacturing method of semiconductor machining adhesive tape and semiconductor device
CN107919274A (en) * 2016-10-05 2018-04-17 株式会社迪思科 processing method
CN108630739A (en) * 2017-03-22 2018-10-09 东芝存储器株式会社 Semiconductor device and its manufacturing method
CN108630739B (en) * 2017-03-22 2021-12-21 东芝存储器株式会社 Semiconductor device and method for manufacturing the same
CN109119336A (en) * 2017-06-22 2019-01-01 株式会社迪思科 The processing method of machined object
CN109119336B (en) * 2017-06-22 2024-02-09 株式会社迪思科 Method for processing object to be processed
CN110945630A (en) * 2017-07-28 2020-03-31 浜松光子学株式会社 Method for manufacturing laminated element
CN110945630B (en) * 2017-07-28 2023-10-31 浜松光子学株式会社 Method for manufacturing laminated element
US11817319B2 (en) 2017-07-28 2023-11-14 Hamamatsu Photonics K.K. Laminated element manufacturing method
CN109391241A (en) * 2017-08-02 2019-02-26 株式会社迪思科 The manufacturing method of elastic wave device substrate
CN112400217A (en) * 2018-07-19 2021-02-23 东京毅力科创株式会社 Substrate processing system and substrate processing method
CN110783250A (en) * 2018-07-31 2020-02-11 株式会社迪思科 Method for processing wafer
CN109590288B (en) * 2018-11-28 2021-06-04 四川大学 Method for cleaning impurities on transmission surface of light-transmitting medium by laser
CN109590288A (en) * 2018-11-28 2019-04-09 四川大学 The method of laser cleaning light transmission medium transmission plane impurity
CN114160958A (en) * 2021-12-07 2022-03-11 华东光电集成器件研究所 Method for combining laser invisible cutting and mechanical cutting of wafer

Also Published As

Publication number Publication date
JP2015133435A (en) 2015-07-23
TWI625810B (en) 2018-06-01
JP6230422B2 (en) 2017-11-15
CN104779204B (en) 2019-07-02
TW201528410A (en) 2015-07-16
KR102163441B1 (en) 2020-10-08
KR20150085474A (en) 2015-07-23

Similar Documents

Publication Publication Date Title
CN104779204A (en) Wafer processing method
US9620415B2 (en) Wafer processing method
KR102419485B1 (en) Method of reducing wafer thickness
KR102368338B1 (en) Processing method of wafer
CN103084950B (en) Wafer processing method
JP6180223B2 (en) Wafer manufacturing method
CN105047612A (en) Wafer processing method
CN107591361B (en) Method for manufacturing semiconductor device chip
CN103715082A (en) Processing method of wafer
JP2005032903A (en) Semiconductor device and its manufacturing method
CN109698161A (en) The processing method of chip
CN108987268A (en) The processing method of chip
CN106505035A (en) The processing method of chip
CN102693941B (en) Wafer cutting process
CN109285771A (en) The processing method of chip
JP2009283802A (en) Method of manufacturing semiconductor device
JP5534793B2 (en) Wafer processing method
US11158601B2 (en) Laminated element manufacturing method
US9455149B2 (en) Plate-like object processing method
JP2017216274A (en) Processing method for wafer
CN102157446A (en) Method for processing wafer
JP2020009864A (en) Grinding method of workpiece
JP4553878B2 (en) Manufacturing method of semiconductor device
CN108115295A (en) The processing method of chip
KR20220076308A (en) Method for processing wafer

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant